Unit 3- PIC 8259 Prepared by R.Kavitha Page 1 8259 programmable interrupt controller PIC is a device which is used to increase the interrupt handling capacity of the microprocessor. The 8259A is a programmable interrupt controller designed to work with intel microprocessor 8080 A, 8085, 8086, 8088. The Programmable Interrupt Controller (PlC) functions as an overall manager in an Interrupt- Driven system. It accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination . Features: 1)Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the processor in place of one INTR/INT pin. 2)It is possible to locate vector table for these additional interrupts request anywhere in the memory map. However, all the eight interrupt are spaced at the interval of either four or eight location. 3)By cascading 8259, it is possible to get 64 priority interrupts. 4) Mask each interrupt request individually. 5) 8259 can be programmed to accept either the level triggered or edge triggered interrupt request. 6) With the help of 8259 user can get information of pending interrupts, in service interrupt and masked interrupts. 7) It minimize the software and real-time overhead in handling multiple interrupt priorities.
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Unit 3- PIC 8259
Prepared by R.Kavitha Page 1
8259 programmable interrupt controller
PIC is a device which is used to increase the interrupt handling capacity of the
microprocessor.
The 8259A is a programmable interrupt controller designed to work with intel microprocessor
8080 A, 8085, 8086, 8088.
The Programmable Interrupt Controller (PlC) functions as an overall manager in an Interrupt-
Driven system. It accepts requests from the peripheral equipment, determines which of the
incoming requests is of the highest importance (priority), ascertains whether the incoming
request has a higher priority value than the level currently being serviced, and issues an
interrupt to the CPU based on this determination .
Features:
1)Handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on the
processor in place of one INTR/INT pin.
2)It is possible to locate vector table for these additional interrupts request anywhere in the
memory map. However, all the eight interrupt are spaced at the interval of either four or eight
location.
3)By cascading 8259, it is possible to get 64 priority interrupts.
4) Mask each interrupt request individually.
5) 8259 can be programmed to accept either the level triggered or edge triggered interrupt
request.
6) With the help of 8259 user can get information of pending interrupts, in service interrupt
and masked interrupts.
7) It minimize the software and real-time overhead in handling multiple interrupt priorities.
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Pin Diagram
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Internal Block Diagrma
• Data bus buffer: This 3- state, bidirectional 8-bit buffer is used to interface the 8259A to
the system data bus. Control words and status information are transferred through
the data bus buffer.
• Read/Write logic: This is typical read/write control logic.
• Control Logic: This has 2 pins INT (interrupt) and INTA *interrupt acknowledge as input.
The INT is connected to MPU. Whereas the INTA* is interrupt acknowledge from MPU.
• Interrupt request register (IRR): IRR stores all the interrupt inputs that are requesting
service. Basically, it keeps track of which interrupt inputs are asking for service.
• In service register (ISR): The in service registers keeps tracks of which interrupt inputs
are currently being serviced. For each input that is currently being serviced the
corresponding bit will be set in the in service register.
• Interrupt mask register (IMR): The IMR is used to disable (Mask) or enable (Unmask)
individual interrupt inputs. Masking of higher priority input will not affect the interrupt
request lines of lower priority. 0-Enable 1- Disable.
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• Priority Resolver: This logic block determines the priorities of the set in the IRR. The bit
corresponding to the highest priority interrupt input pin is set in the ISR during the
INTA* input.
• Cascade buffer/comparator: This section generates control signal necessary for cascade
operations. 8259A can be cascaded with the other 8259 to increase the interrupt
handling capability. In such case, the former is called as master, and the later are called
as slaves. The 8259 can be set up as a master or a slave by the SP*/EN*.
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Interrupt sequence of 8259
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Programming the 8259A
The command words of 8259A are classified in two groups
1. Initialization command words (ICW) and
2. Operation command words (OCW).
The 8259 can be initialized with four ICWs. The first two are compulsory, and the other two
are optional based on the modes being used. After initialization, the 8259 can be set up to
operate in various modes by using three different OCWs. This is the initialization flow chart :
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Operation Command Word
• After initialization, the 8259 is ready to process interrupt requests. And during
operation, it might be necessary to change the mode of processing the interrupts.
Operation Command words are used for this purpose. They may be loaded after the
initialization of 8259 to alter the priority modes.
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• OCW is used for enabling or disabling the recognition of specific interrupt requests by
programming the IMR.
• M=1 indicates that the interrupt is to be masked, and M=0 indicates that it is to be
unmasked.
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Priority Modes of 8259
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End Of Interrupt
The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command.
Two types of EOI command;
a)Specific
b)Non-specific
The non-specific EOI command automatically reset the highest ISR bit.
When a mode that may disturb the fully nested structure, the specific EOI command is issued to
reset a particular ISR bit.
• Specific Rotation: In automatic rotation, a device after being serviced, receives the
lowest priority. Where as in this mode, the lowest priority can be assigned to any
interrupt input (IR0 to IR7).
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• Special mask mode: some application may require an interrupt service routine to
dynamically alter the system priority structure during its execution under software
control. For example the routine may wish to inhibit lower priority requests for a
portion of its execution, but enable some of them for another portion.
• Poll command: The interrupt output is not used. The microprocessor checks the status