UNIT-2: COURSE MATERIAL PROGRAMMABLE READ ONLY MEMORY (PROM) MEMORY: The memory is a device in which information can be stored for future use. Memory consists of several locations each location being identified by unique address. The process of entering information into the memory location is known as WRITE operation and the process of accessing information from the memory location is known as READ operation. The maximum number of information bits that can be stored in a memory is nothing but MEMORY CAPACITY. It is specified by the number of address lines (m) x number of bits stored per location (n). i.e., memory can be specified as 2 m xn. Let m=11 and n=8; then such a memory can be specified as 2 11 x8 = 2Kx8 = 2KB memory. This means the device has 2048 memory location and in each location it can accommodate 8- bits. The time required for the contents of a location to be available at the output of the memory is known as ACCESS TIME. The time elapsed from the start of one memory operation to the time another memory operation can be initialised is called CYCLE TIME. Memories, in general, can be classified into two categories: 1. Sequential access memory 2. Random access memory In a sequential access memory, a piece of data may be accessed by sequential searching all the information bits stored on the device until the desired data is found. It means the access time depends on the contents prior to the desired data. Example: Magnetic Tapes, Floppy Discs, Gramophone recorders, etc. Ina a random access memory the desired information can be accessed directly and randomly by providing the address location of where the data is? Hence the access time depends only on the access time of the desired data. One of the most popular random access memory is the Read Only memory (ROM). Example: ROM, RAM. In ROM once the data is stored, it cannot be altered in future. The four basic variations of read only memories are: 1. Mask programmed ROM 2. Programmable ROM or PROM 3. Erasable PROM or EPROM 4. Electrically Erasable PROM or EEPROM
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UNIT-2: COURSE MATERIAL
PROGRAMMABLE READ ONLY MEMORY (PROM)
MEMORY:
The memory is a device in which information can be stored for future use. Memory consists
of several locations each location being identified by unique address.
The process of entering information into the memory location is known as WRITE operation
and the process of accessing information from the memory location is known as READ
operation.
The maximum number of information bits that can be stored in a memory is nothing but
MEMORY CAPACITY. It is specified by the number of address lines (m) x number of bits
stored per location (n). i.e., memory can be specified as 2m
xn.
Let m=11 and n=8; then such a memory can be specified as 211
x8 = 2Kx8 = 2KB memory.
This means the device has 2048 memory location and in each location it can accommodate 8-
bits.
The time required for the contents of a location to be available at the output of the memory is
known as ACCESS TIME.
The time elapsed from the start of one memory operation to the time another memory
operation can be initialised is called CYCLE TIME.
Memories, in general, can be classified into two categories:
1. Sequential access memory
2. Random access memory
In a sequential access memory, a piece of data may be accessed by sequential searching all
the information bits stored on the device until the desired data is found. It means the access
time depends on the contents prior to the desired data.
Example: Magnetic Tapes, Floppy Discs, Gramophone recorders, etc.
Ina a random access memory the desired information can be accessed directly and randomly
by providing the address location of where the data is? Hence the access time depends only
on the access time of the desired data. One of the most popular random access memory is the
Read Only memory (ROM).
Example: ROM, RAM.
In ROM once the data is stored, it cannot be altered in future.
The four basic variations of read only memories are:
1. Mask programmed ROM 2. Programmable ROM or PROM
3. Erasable PROM or EPROM 4. Electrically Erasable PROM or EEPROM
MASK PROGRAMMED ROM:
Mask Programmed ROMs are often referred to as basic ROM. They are programmed by the
manufacturer as per the user‟s specifications and cannot be altered after manufacturing.
PROM:
This type of read only memory is available with all conductive elements intact. This is
programmed by the user .The major drawback of the PROM is that, once programmed they
cannot be altered further. Thus, if an error is made by the user while programming, the
PROM must be discarded. Hence, the user must be very careful at the time he programs the
PROM as it is a One Time Programmable device.
EPROM:
EPROMs were pioneered by Intel Corporation. They differ from PROMs in that they can be
erased and reprogrammed again and again, where as PROMs can be programmed only once.
The date in an EPROM is erased by exposing the device to ultraviolet light for that special
windows are built into the device package to provide access to ultraviolet light.
The major advantage of EPROMs is that they can be programmed with certain content; they
can be used and then reprogrammed with different content in later time. It is flexible and
more over it is a low cost device.
The disadvantages of EPROMs are
1. They have to be removed from the circuit in order to be erased
2. Only block erasure is possible
3. Package with a quartz window is expensive.
EEPROM:
EEPROMs avoid many of the problems of EPROMs. They are similar to EPROMs, except
that they are erased and reprogrammed using electrical pulses. This feature allows both
erasing and programming to be done without disturbing the chips in the host system. Erasing
can be accomplished by using a byte erase mode or a block erase mode. In the block erase
mode, the entire chip is erased, whereas in the byte erase mode, the content of a single
addressed location is erased.
The two most important characteristics of EEPROMs, as far as the users are concerned, are
endurance and data retention. Endurance in an EPROM specification referred to the
maximum number of times each cell in the memory can be erased and reliably rewritten. Date
retention is the ability to an EEPROM cell to retain charge over long period of time.
PROGRAMMABLE LOGIC ELEMENT (PLE):
A PLE is essentially a PROM with a programmable OR array being driven by a fixed AND
array. These include both combinational and sequential (registered) units. The combinational
group consists of eleven devices:
PLE5P8/A PLE9P4 PLE10P8 PLE12P4
PLE8P4 PLE9P8 PLE11P4 PLE12P8
PLE8P8 PLE10 P4 PLE11P8
The numbers preceding and succeeding “P” in a device specify the number of inputs and
outputs .The letter “P” denotes that the output of the device is a non-registered.
Figure: Block diagram of combinational PLE devices
The inputs to each device (Except PLE5P8) are portioned into two subsets, “l” and “m”
which drive the column and the row decoder respectively. The PLE5P8 does not have a
column decoder.
There are four PLE devices with on-chip D flip-flops. These are:
PLE9R8 PLE10R8 PLE11RA8 PLE11RS8
The letter “R” denotes that the output of the device is registered. The “A” and “S” indicates
that the tri-state buffers at the output of the corresponding device are enabled independent of
the clock and in synchronization with the clock.
SEQUENTIAL PLE DEVICES:
The sequential devices are two types:
1. Synchronous
2. Asynchronous
The PLE11RAS are asynchronous and PLE11RS8 are synchronous devices.
Figure: Block diagram of sequential PLE devices
TOTALLY SELF- CHECKING CHECKER FOR BERGER CODES:
A Berger code is length “n” has “i” information bits and “k” check bits where k=log(i+1) and
n=(i+k). The “k” check bits are the binary number corresponding to the number of “0”s in
the information bits.
For example if i=10101000, then the “k” check bits are derived a follows:
Number of “0”s in information bits are “5”
Binary equivalent of 5 is “0101”
i=10101000 k=0101 and the Berger code becomes “10101000 0101”
Berger code can detect all single and unidirectional errors in a code-word.
Figure: Totally Self-checking checker for Berger codes
C is a combinational network which generates the complements of the check bits from the
information bits. The totally self-checking checker circuit compares the k check bits with the
output of C. It has two outputs f and g; the signals observed on the outputs f and g should
always be complementary (i.e., f=0, g=1 or f=1, g=0) if and only if every pair of inputs to the
checker is also complementary.
The check bit generator and the totally self-checker of figure 2.5 can also be
implemented by two PLE8P4 devices.
Figure: Implementation of Totally Self-checking checker for Berger codes using PLE8P4
1-OUT-OF-n DETECTOR:
A 1-out-of-n detector is a network whose output is logic “1” if and only if, a single out of the
n inputs to the network is at logic “1”, otherwise the output of the network is at logic “0”
A 1-ot-of-n detector, for large n, can be built from PLE devices. The number of inputs n, is
divided into smaller groups of m inputs so that the detector can be constructed with PLEs
having m inputs each. In such a detector design, the output of a PLE can be in one of the
three states corresponding to m inputs. These states are all “0”, a single “1”, and two or more
“1”s. Since the state of all “0”s can be identified from the knowledge of the other two states
each PLE requires two outputs. One output indicate logic “1” only when the number of “1”s
in the input is two or more; the other indicates logic “1” when the number of “1”s at input is
exactly one.
We shall illustrate the design procedure for 1-out-of-90 detector. The first stage of the
detector consists of 9[n/m=90/10] PLE10P4 devices. Only two out of four outputs of each
device are required. The outputs of the PLEs, which represent the state of “the number 1‟s is
exactly “1” are connected to the inputs of a PLE9P4. The outputs of the PLE10P4
representing the state “the number of „1‟s is two or more” are connected to A(0-4) inputs of
a PLE11P4 and the A9 and A10 inputs of the device are driven by the outputs O1 and O2