Unit 08 – Advanced Microprocessor 1 Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing 1. Features of 80386 The 80386 microprocessor is an enhanced version of the 80286 microprocessor Memory-management unit is enhanced to provide memory paging. The 80386 also includes 32-bit extended registers and a 32-bit address and data bus. These extended registers include EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and EFLAGS. The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual memory with up to 64TBytes. The 80386 is operated in the pipelined mode, it sends the address of the next instruction or memory data to the memory system prior to completing the execution of the current instruction This allows the memory system to begin fetching the next instruction or data before the current is completed. This increases access time. The instruction set of the 80386 is enhanced to include instructions that address the 32-bit extended register set. The 80386 memory manager is similar to the 80286, except the physical addresses generated by the MMU are 32 bits wide instead of 24-bits. The concept of paging is introduced in 80386 80386 support three operating modes: 1) Real Mode (default) 2) Protected Virtual Address Mode (PVAM) 3) Virtual Mode The memory management section of 80386 supports virtual memory, paging and four levels of protection. The 80386 includes special hardware for task switching. 2. 80386 Architecture The internal architecture of the 80386 includes six functional units that operate in parallel. The parallel operation is called as pipeline processing. Fetching, decoding execution, memory management, and bus access for several instructions are performed simultaneously. The six functional units of the 80386 are 1) Bus Interface Unit 2) Code Pre-fetch Unit 3) Instruction Decoder Unit 4) Execution Unit 5) Segmentation Unit 6) Paging Unit
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Transcript
Unit 08 – Advanced Microprocessor
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Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing
1. Features of 80386 The 80386 microprocessor is an enhanced version of the 80286 microprocessor
Memory-management unit is enhanced to provide memory paging.
The 80386 also includes 32-bit extended registers and a 32-bit address and data bus. These
extended registers include EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and EFLAGS.
The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual
memory with up to 64TBytes.
The 80386 is operated in the pipelined mode, it sends the address of the next instruction or
memory data to the memory system prior to completing the execution of the current
instruction
This allows the memory system to begin fetching the next instruction or data before the
current is completed. This increases access time.
The instruction set of the 80386 is enhanced to include instructions that address the 32-bit
extended register set.
The 80386 memory manager is similar to the 80286, except the physical addresses
generated by the MMU are 32 bits wide instead of 24-bits.
The concept of paging is introduced in 80386
80386 support three operating modes:
1) Real Mode (default)
2) Protected Virtual Address Mode (PVAM)
3) Virtual Mode
The memory management section of 80386 supports virtual memory, paging and four
levels of protection.
The 80386 includes special hardware for task switching.
2. 80386 Architecture The internal architecture of the 80386 includes six functional units that operate in parallel.
The parallel operation is called as pipeline processing.
Fetching, decoding execution, memory management, and bus access for several
instructions are performed simultaneously.
The six functional units of the 80386 are
1) Bus Interface Unit
2) Code Pre-fetch Unit
3) Instruction Decoder Unit
4) Execution Unit
5) Segmentation Unit
6) Paging Unit
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Figure: 80386 Architecture
The Bus Interface Unit connects the 80386 with memory and I/O. Based on internal
requests for fetching instructions and transferring data from the code pre-fetch unit, the
80386 generates the address, data and control signals for the current bus cycles.
The code pre-fetch unit pre-fetches instructions when the bus interface unit is not
executing the bus cycles. It then stores them in a 16-byte instruction queue for decoding by
the instruction decode unit.
The instruction decode unit translates instructions from the pre-fetch queue into micro-
codes. The decoded instructions are then stored in an instruction queue (FIFO) for
processing by the execution unit.
The execution unit processes the instructions from the instruction queue. It contains a
control unit, a data unit and a protection test unit.
The control unit contains microcode and parallel hardware for fast multiply, divide and
effective address calculation. The unit includes a 32-bit ALU, 8 general purpose registers
and a 64-bit barrel shifter for performing multiple bit shifts in one clock. The data unit
carries out data operations requested by the control unit.
The protection test unit checks for segmentation violations under the control of microcode.
The segmentation unit calculates and translates the logical address into linear addresses at
the request of the execution unit.
The translated linear address is sent to the paging unit. Upon enabling the paging
mechanism, the 80386 translates these linear addresses into physical addresses.
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If paging is not enabled, the physical address is identical to the linear address and no
translation is necessary.
3. Register organization of 80386 The Register organization of 80386 is as follows:
Figure:80386 General Purpose, Index and Pointer Register
3.1. General Purpose Register
Registers EAX, EBX, ECX, EDX, EBP, EDI and ESI are regarded as general purpose or
multipurpose registers.
EAX (ACCUMULATOR):The accumulator is used for instructions such as multiplication,
division and some of the adjustment instructions. In 80386 and above, the EAX register
may also hold the offset address of a location in memory system.
EBX (BASE INDEX): This can hold the offset address of a location in the memory system in
all version of the microprocessor. It the 80386 and above EBX also can address memory
data.
ECX (count): This acts as a counter for various instructions.
EDX (data): EDX is a general-purpose registers that holds a part of the result for
multiplication or part of the division. In the 80386 and above this register can also address
memory data.
3.2. Pointer and Index Register
EBP (Base Pointer): EBP points to a memory location in all version of the microprocessor
for memory data transfers.
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ESP (Stack Pointer): ESP addresses an area of memory called the stack. The stack memory
is a data LIFO data structure. The register is referred to as SP if used in 16 bit mode and
ESP if referred to as a 32 bit register.
EDI (Destination index): EDI often addresses string destination data for the string
instruction. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose register.
ESI (Source index): ESI can either be used as ESI or SI. It is often used to the address
source string data for the string instructions. Like EDI ESI also functions as a general-
purpose registers.
Figure:80386 Segment Register
CS (Code): The code segment is a section of memory that holds the code used by the
microprocessor. The code segment registers defines the starting address of the section of
memory holding code.
SS (Stack): The stack segment defines the area of memory used for the stack. The stack
entry point is determined by the stack segment and stack pointer registers. The BP
registers also addresses data within the stack segment.
DS (Data): The data section contains most data used by a program. Data are accessed in
the data segment by an offset address of the contests of other registers that hold the offset
address.
ES (extra): The extra segment is used to hold information about string transfer and
manipulation
FS and GS: These are supplementing segment registers available in the 80386 and above
microprocessors to allow two additional memory segments for access by programs.
EIP (Instruction Pointer): EIP addresses the next instruction in a section of memory
defined as a code segment. This register is IP (16bit) when microprocessor operates in the
real mode and EIP (32 bits) when 80386 and above operate in protected mode
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Figure: 80386 Instruction Pointer
3.3. Flag Register:
Indicates the condition of the microprocessor and controls its operations. Flag registers are
also upward compatible since the 8086-80268 have 16bit registers and the 80386 and
above have EGLAF register (32 bits)
Figure: 80386 Flag Register
IOPL (I/O Privilege level): IOPL is used in protected mode operation to select the
privilege level for I./O devices. IF the current privilege level is higher or more trusted than
the IOPL, I/O executed without hindrance. If the IOPL is lover than the current privilege
level, an interrupt occurs, causing execution to suspend. Note that an IPOL is 00 is the
highest or more trusted; if IOPL is 11, it’s the lowest or least trusted.
NT (Nested Task): The nested task flag is used to indicate that the current task is nested
within another task in protected mode operation. This flag is when the task I nested by
software.
RF (Resume): The resume flag is used with debugging to control the resumption of
execution after the next instruction.
VM (Virtual Mode): The VM flag bit selects virtual mode operation in a protected mode
system.
Note: All the other flag bit is having similar description as in 8086 flag register.
3.4. System Address Register:
Four memory management registers are used to specify the locations of data structures
which control segmented memory management.
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GDTR (Global Descriptor Table Register) and IDTR (Interrupt Descriptor Table Register) be
loaded with instructions which get a 6 byte data item from memory
LDTR (Local Descriptor Table Register) and TR (Task Register) can be loaded with
instructions which take a 16-bit segment selector as an operand.
3.5. Special 80386 Register
Control Register: Four Control Register (CR0-CR3)
Debug Register: Eight Debug Register (DR0-DR7)
Test Register: Two Test Register (TR6-TR7)
3.5.1. Control Register in detail.
The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global machine
status independent of the executed task.
Load and store instructions are available to access these registers
Common tasks performed by control registers include interrupt control, switching the
addressing mode, paging control, and coprocessor control.
Figure: Control Register
CR0:
CR0 contains system control flags, which control or indicate conditions that apply to the
system as a whole, not to an individual task.
PE (Protection Enable, bit 0): Setting PE causes the processor to begin executing in
protected mode. Resetting PE returns to real-address mode.
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MP (Math Present, bit 1): MP controls the function of the WAIT instruction, which is used
to coordinate a coprocessor.
EM (Emulation, bit 2):EM indicates whether coprocessor functions are to be emulated.
TS (Task Switched, bit 3):The processor sets TS with every task switch and tests TS when
interpreting coprocessor instructions.
ET (Extension Type, bit 4):ET indicates the type of coprocessor present in the system
(80287 or 80387).
PG (Paging, bit 31): PG indicates whether the processor uses page tables to translate
linear addresses into physical addresses.
CR2:
CR2 is used for handling page faults when PG is set. The processor stores in CR2 the linear
address that triggers the fault.
Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the
address the program attempted to access is stored in the CR2 register.
CR3:
Used when virtual addressing is enabled, hence when the PG bit is set in CR0, CR3 enables
the processor to translate linear addresses into physical addresses by locating the page
directory and page tables for the current task.
Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which
stores the physical address of the first page directory entry.
Note: Reserved field shown in figure are kept reserved by manufacturer
3.5.2. Debug Register
Debugging of 80386 allows data access breakpoints as well as code execution breakpoints.
80386 contains 6 debug registers to specify
1) 4 breakpoints
2) Breakpoint Control options
3) Breakpoint Status
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Figure: 80386 Debug Register
Linear Breakpoint Address Registers:
The breakpoint addresses specified are 32-bit linear addresses
While debugging, Intel 386 h/w continuously compares the linear breakpoint addresses in
DR0-DR3 with the linear addresses generated by executing software.
3) The choices of data breakpoints are 1byte, 2bytes & 4bytes
4) For instruction execution breakpoint, the length is 1(beginning byte address)
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Table: LENi Encoding
RWi(i=0 - 3): Memory Access Qualifier Bit
1) 2 bit field for each breakpoint
2) Specifies the type of usage which must occur inorder to activate the associated
breakpoint
Table: Table: RWii Encoding
GD: Global Debug Register Access Detect
Debug registers can only be accessed in real mode or at privilege level 0 in protected mode
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GD bit, when set, provides extra protection against any Debug Register access even in Real
Mode or at privilege level 0 in Protected Mode.
The GD bit, when set, causes an exception 1 fault if an instruction attempts to read or write
any Debug Register.
The GD bit is then automatically cleared when the exception 1 handler is invoked, allowing
the exception 1 handler free access to the debug registers.
GE and LE bit: Exact data breakpoint match, global and local
Gi and Li(i=0 - 3): Breakpoint Enable, global and local
If either Gi or Li is set then the associated breakpoint is enabled.
Debug Status Register:
A Debug Status Register allows the exception 1 handler to easily determine why it was
invoked.
It can be invoked as a result of one of several events:
1) DR0 Breakpoint fault/trap.
2) DR1 Breakpoint fault/trap.
3) DR2 Breakpoint fault/trap.
4) DR3 Breakpoint fault/trap.
5) Single-step (TF) trap.
6) Task switch trap.
7) Fault due to attempted debug register access when GD = 1.
Figure: Debug Status Register
Bi : Debug fault/trap due to breakpoint 0 -3
Four breakpoint indicator flags, B0-B3, correspond one-to-one with the breakpoint
registers in DR0-DR3.
A flag Bi is set when the condition described by DRi, LENi, and RWi occurs.
BD: Debug fault due to attempted register access when GD bit is set
This bit is set if the exception 1 handler was invoked due to an instruction attempting to
read or write to the debug registers when GD bit was set.
BS: Debug trap due to single step
This bit is set if the exception 1 handler was invoked due to the TF bit in the flag register
being set
BT: Debug trap due to task switch
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This bit is set if the exception 1 handler was invoked due to a task switch occurring to a
task having an Intel386.
3.5.3. Test Register
Two more test register are provided by 80386 for page caching
They are used to control the testing of Translation Look-aside Buffer(TLB) of Intel386.
TR6 is the command test register
TR7 is the data register which contains the data of Translation Look-aside buffer test.
Figure: Test Register
3.6. Program-Invisible registers
The global and local descriptor tables are found in the memory system.
In order to access and specify the address of these tables, the program invisible registers
used.
The program invisible registers are not directly addressed by software so they are given
name.
The GDTR (global descriptor table register) and IDTR (interrupt descriptor table register)
contain the base addresses of the descriptor table and its limit.
The limit of each descriptor table is 16 bits because the maximum table length is 64 Kbytes.
When the protected mode operation is desired, the address of the global descriptor table
and its limit are loaded into the GDTR.
4. Real Modes of 80386 Default Mode
After reset, the 80386 starts from the memory location FFFFFFF0 H under real address
mode.
In real address mode, 80386 works as a fast 8086 with 32 bit registers and data types.
Real-address mode is in effect after a signal on the RESET pin. Even if the system is going to
be used in protected mode, the start-up program will execute in real-address mode
temporarily while initializing for protected mode.
The addressing techniques, memory size, interrupt handling in this mode of 80386 are
similar to the real addressing mode of 80286.
In real address mode, the default operand size is 16 bit but 32 bit operands and addressing
modes may be used with the help of override prefixed.
Maximum physical memory = 1Mega byte (1MB)
The only way to leave real-address mode is to switch to protected mode.
5. PVAM of 80386
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Introduced in the 80386 processor.
32-bit address bus => access up to 232 bytes = 22. 230 B = 4 GB
Base address => 32-bit value
Offset =>16-bit or 32-bit value
Linear address = base address + offset
Linear address → physical address with paging
In protected mode, the segment registers contain an index into a table of segment
descriptors.
Each segment descriptor contains the start address of the segment, to which the offset is
added to generate the address.
In addition, the segment descriptor contains memory protection information.
This includes an offset limit and bits for write and read permission.
This allows the processor to prevent memory accesses to certain data.
Protected mode is accessed by placing a logic 1 into the PE bit of CR0
This system contains one data segment descriptor and one code segment descriptor with
each segment set to 4G bytes in length.
PVAM mode support memory management, virtual memory, multitasking, protection,
debugging, segmentation and paging.
6. Virtual Mode of 80386 In its protected mode of operation, 80386DX provides a virtual 8086 operating
environment to execute the 8086 programs.
The real mode can also use to execute the 8086 programs along with the capabilities of
80386, like protection and a few additional instructions.
Once the 80386 enters the protected mode from the real mode, it cannot return back to the
real mode without a reset operation.
Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086
programs while in protected mode.
The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086
real mode.
In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in
the 4Gbytes address space of the protected mode of 80386.
Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of memory.
In virtual mode, the paging mechanism and protection capabilities are available at the
service of the programmers.
The 80386 supports multiprogramming, hence more than one programmer may be using
the CPU at a time.
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Paging unit may not be necessarily enable in virtual mode, but may be needed to run the
8086 programs which require more than 1Mbyts of memory for memory management
function.
In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size.
Each of the pages may be located anywhere in the maximum 4Gbytes physical memory.
The virtual mode allows the multiprogramming of 8086 applications.
The virtual 8086 mode executes all the programs at privilege level 3.
Any of the other programmers may deny access to the virtual mode programs or data.
Even in the virtual mode, all the interrupts and exceptions are handled by the protected
mode interrupt handler.
To return to the protected mode from the virtual mode, any interrupt or execution may be
used.
As a part of interrupt service routine, the VM bit may be reset to zero to pull back the
80386 into protected mode.
7. Segment in 80386 In protected mode the contents of segment register is called selectors shown below:-
Figure: Segment Selector
Descriptor Index: Selects any one of the 8192(213) descriptor from a descriptor table
TI – Table Indicator
TI=1 Local Descriptor Table
TI=0 Global Descriptor Table
RPL (Requested Privilege Level)(2-bit): Refers the privilege of that segment. They are used
while protection checks to indicate whether access to segment is allowed or not allowed.
7.1. 80386 Descriptor Need of Descriptor
Segments are the memory area defined by programmer and can be code, stack and data
segment.
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80386 segments are also assigned to have attributes viz. privilege level, segment type,
segment limit.
So, it’s not possible to use a 16 bit segment register to represent all the info regarding a
segment. therefore the Solution is Descriptor
Segment sizes vary from 1byte to 4GB in 80386.
Figure: Segment Descriptor in Protected Mode
Offset Bit Description
40 A(Accessed) 80386 sets this bit to 1 whenever a memory reference to a segment
defined by this descriptor is made.
41-43 TYPE 3-bit field describes the type of segment
000 Data segment , read only
001 Data segment , read/write
010 Stack segment, read only
011 Stack segment, read/write
100 Code segment, execute-only, non-conforming
101 Code segment, execute/read, non-conforming
110 Code segment, execute-only, conforming
111 Code segment, execute/read, conforming
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44 S(System) 0 – Specifies system segment descriptor
E.g. LDS, TSS, Gates
1 – Specifies non system segment descriptor
E.g. code, stack or data
45-46 DPL (Descriptor
Privilege level)
Indicates privilege level associated with memory space. 0 - most
privileged 3 – least privileged
47 Present If set 0 , indicates that the address range that is specified by the
descriptor is temporarily not present.
52 U(User) Undefined bit.
53 X Reserved by Intel
54 D(Default Size) 0 – Operands within this segments are assumed to be 16 bits.
1 – Operands assumed to be 32 bits
55 G(Granularity
bit)
0 – Unit of limit field is 1 byte.
1 – Unit of limit field is of 4096 bytes (or 1 page).
The Above figure is the format of the code/data descriptor; one descriptor is 64-bit long.
As we can see, a descriptor actually includes a 32-bit base address and a 20-bit limit and some
attributes, the 32-bit base address indicate where the segment starts, and the 20-bit limit
indicates the length of the segment.
However, a problem comes up, 20-bit limit can only represent 2^20 = 1MB memory, to access
a 4GB memory space, descriptor uses G bit to indicate whether the limit use 4K or 1 byte for
one unit, that means if G bit is set then we get 2^20*4K = 4GB memory, if it is unset then we
only use a memory space under 1MB.
7.2. Descriptor tables in 80386
The segment descriptors that we defined are grouped together and placed in a continuous
memory location. The group arrangement called Descriptor Table.
Each descriptor requires 8byte in order to store the info of a particular segment.
Descriptor table can contain 8192(8K) descriptors at the max.
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The maximum length of a descriptor table is a 64Kbytes.
The descriptor tables define all the segments used in the 80386 when it operates in the
protected mode.
There are three types of descriptor tables: the global descriptor table (GDT), the local
descriptor table (LDT), and the interrupt descriptor table (IDT).
The registers used by the 80386to address these three tables are called the global descriptor
table register (GDTR), the local descriptor table register (LDTR), and the interrupt descriptor
table register (IDTR).
These registers are loaded with the LGDT, LLDT, and LIDT instructions, respectively.
The local and global descriptor tables hold up to 8192 entries each, and the interrupt
descriptor table holds up to 256 entries.
A descriptor is indexed from either the local or global descriptor table by the selector that
appears in a segment register.
Whenever a new selector is placed into one of the segment registers, the 80386 accesses one of
the descriptor tables and automatically loads the descriptor into a program-invisible cache
portion of the segment register.
1) Global Descriptor Table (GDT):
This is the main table of descriptors.
The same GDT can be used by all programs to refer to segment of memory.
80386 can have many LDT’s but only one GDT.
Figure: Global Descriptor Table
2) Local Descriptor Table (LDT) :
A multi-tasking system is defined on a per task basis.
The main purpose of an LDT would be combined with GDT in order to expand the total
number of available descriptors.
Generally, each task can have its own LDT and can also be shared with other task.
8. Paging
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Paging is one of the memory management techniques
The paging mechanism allows any linear (logical) address, as it is generated by a program,
to be placed into any physical memory page, as generated by the paging mechanism.
A linear memory page is a page that is addressed with a selector and an offset in either the
real or protected mode.
A physical memory page is a page that exists at some actual physical memory location.
For example, linear memory location 20000H could be mapped into physical memory
location 30000H, or any other location, with the paging unit. This means that an instruction
that accesses location 20000H actually accesses location 30000H. Each 80386 memory
page is 4K bytes long.
Paging allows the system software to be placed at any physical address with the paging
mechanism.
Three components are used in page address translation: the page directory, the page table,
and the actual physical memory page.
The segmentation scheme may divide the physical memory into a variable size segments
but the paging divides the memory into a fixed size pages.
The segments are supposed to be the logical segments of the program.
The pages are just fixed size portions of the program module or data.
Advantage:
The advantage of paging scheme is that the complete segment of a task need not be in the
physical memory at any time.
Only a few pages of the segments, which are required currently for the execution need to be
available in the physical memory.
Thus the memory requirement of the task is substantially reduced, relinquishing the
available memory for other tasks.
8.1. Page Directory
The page directory contains the location of up to 1024 page translation tables, which are
each four bytes long.
Each page translation table translates a logical address into a physical address.
The page directory is stored in the memory and accessed by the page descriptor address
register (CR3).
Control register CR3 holds the base address of the page directory, which starts at any 4K-
byte boundary in the memory system.
Each entry in the page directory translates the leftmost 10 bits of the memory address. This
10-bit portion of the linear address is used to locate different page tables for different page
table entries.
8.2. Page Table
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The page table contains 1024 physical page addresses, accessed to translate a linear
address into a physical address.
8.3. Page Directory Entry
Total Page Directory Entries are1024
Each directory entry is of 4byte
Figure: Page Directory Entry
8.4. Page Table Entry
The page table entries contain the starting address of the page and the statistical
information about the page.
Total Entries are1024
Each page table entry is of 4byte
Figure: Page Table Entry
D-bit: Dirty bit is undefined for page table directory entries by the 80386 microprocessor
and is provided for use by the operating system.
A-bit: Accessed bit is set to logic 1 whenever the microprocessor accesses the page
Directory entry.
R/W (Read/write) & U/S (user/supervisor) are both used in the protection scheme. Both
bits combine to develop paging priority level protection for level 3, the lowest user level.
P-bit: Present bit, if logic1 indicates that the entry can be used in address translation. If P =
0, the entry cannot be used for translation. When P = 0, the remaining bits of the entry can
be used to indicate the location of the page on the disk memory system.
Difference between page directory and page table entry:
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The main difference is that the page directory entry contains the physical address of a page
table, while the page table entry contains the physical address of a 4K-bytephysical page of
memory.
The other difference is the D (dirty bit), which has no function in thepage directory entry,
but indicates that a page has been written to in a page table entry.
8.5. Page Translation Mechanism in 80386
A page frame is a 4K-byte unit of contiguous addresses of physical memory. Pages begin on
byte boundaries and are fixed in size.
A linear address refers indirectly to a physical address by specifying a page table, a page
within that table, and an offset within that page
Figure: Format of Linear Address
The below figure of page translation shows, how processor converts the DIR, PAGE, and
OFFSET fields of a linear address into the physical address by consulting two levels of page
tables.
The addressing mechanism uses the DIR field as an index into a page directory, uses the
PAGE field as an index into the page table determined by the page directory, and uses the
OFFSET field to address a byte within the page determined by the page table.
In the second phase of address transformation, the 80386 transforms a linear address into
a physical address.
This phase of address transformation implements the basic features needed for page-
oriented virtual-memory systems and page-level protection.
Page translation is in effect only when the PG bit of CR0 is set.
Figure: Page Translation
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9. Features of 80486 The 32-bit 80486 is the next evolutionary step up from the 80386.
One of the most obvious feature included in a 80486 is a built in math coprocessor. This
coprocessor is essentially the same as the 80387 processor used with a 80386, but being
integrated on the chip allows it to execute math instructions about three times as fast as a
80386/387 combination.
80486 is an 8Kbyte code and data cache.
To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid array
package instead of the 132 pin PGA used for the 80386.
Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
It consists of parity generator/checker unit in order to implement parity detection and
generation for memory reads and writes.
Supports burst memory reads and writes to implement fast cache fills.
Three mode of operation: real, protected and virtual 8086 mode.
The 80486 microprocessor is a highly integrated device, containing well over 1.2 million
transistors.
10. Pentium Processor Features
It consists of all the features of 80486. The additional enhancements that Pentium provides
are:
1) Wider data bus width :
It has 64 bit data bus and 32 bit address bus.
It allows 8 byte of data info to be transferred to and from memory.
Bus cycle pipelining has been added to allow two bus cycles to be in progress
simultaneously.
2) Improved Cache Structure:
8KB dedicated instruction cache which gives instruction to its execution units and floating
point unit via dual instruction pipeline.
Cache is organized in a 2 way set associate cache with 32 byte line(256 lines).
8KB data cache which gives data to its execution unit.
This allows 32 byte transfer from cache to pre-fetch buffer which is of 64 bytes.
3) Two parallel integer execution unit :
It allows the execution of two instructions to be executed simultaneously in a single
processor clock.
4) Faster floating point unit :
The floating point unit has been completely redesigned over 80486.
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Faster algorithms provide up to ten times speed – up for common operations including add,
multiply etc.
5) Branch prediction logic:
The Pentium uses tech called branch prediction.
To implement this Pentium has two pre-fetch buffers, one to pre-fetch code in linear
fashion, and one that pre-fetches code according to the Branch Target Buffer (BTB).
Therefore, needed code is almost pre-fetched before it is required for execution.
6) Data Integrity and Error Detection:
The Pentium have added significant data integrity and error detection capability.
Data parity checking is still byte-by-byte basis.
Address parity checking has also been added.
7) Functional Redundancy Checking: (provides maximum error detection)
Two or more Pentium Processor can participate in functional redundancy checking.
One processor (the master) fetching the instruction and executes the instruction in normal
fashion.
Other processor (the checker) (connected directly to the master processor’s buses) verify
correctness of master processor.
Checker executes the instruction same as the master but doesn’t drive the buses.
Checker samples master’s output and compares the values with the internal computed
values. An error signal is asserted in case if mismatch occurs.
8) Super Scalar Architecture:
Processor is capable of parallel instruction execution of multiple instructions are known as
superscalar processors.
Pentium is capable in some cases of executing two integer of two floating point instruction
simultaneously and thus support superscalar architecture.
10.1 Architecture
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Figure: Pentium Architecture
Features of 80486
The 32-bit 80486 is the next evolutionary step up from the 80386.
One of the most obvious feature included in a 80486 is a built in math coprocessor. This
coprocessor is essentially the same as the 80387 processor used with a 80386, but being
integrated on the chip allows it to execute math instructions about three times as fast as a
80386/387 combination.
80486 is an 8Kbyte code and data cache.
To make room for the additional signals, the 80486 is packaged in a 168 pin, pin grid array
package instead of the 132 pin PGA used for the 80386.
Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
It consists of parity generator/checker unit in order to implement parity detection and
generation for memory reads and writes.
Supports burst memory reads and writes to implement fast cache fills.
Three mode of operation: real, protected and virtual 8086 mode.
The 80486 microprocessor is a highly integrated device, containing well over 1.2 million
transistors.
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Explain Architecture of 80486 Processor.
The architecture of the 80486DX is almost identical to the 80386. Added to the 80386
architecture inside the 80486DX is a math coprocessor and an 8K-byte level 1 cache
memory.
Figure: 80486 Architecture
BIU:
BIU generates address, data and control signals for a bus cycle it is supported with an
additional parity detection/generation for memory reads and writes.
During memory write operation, the 486 generates even parity bit for each byte outputs
these bits.
These bits will be stored in a separate parity memory bank.
During read operation, stored parity bits will be read from the parity memory.
80486 checks the parities of data bytes read and compare them with the DP0 – DP3 signals
and generates parity check error, if it occurs.
Instruction Pre-fetch Unit :
It pre-fetches the instruction bytes in advance and holds them in a 32–byte code queue.
Instruction Decoder :
Decodes the instructions in the queue and passes the control and protection test unit.
Execution Unit:
Executes the instruction with the help of Barrel Shifter, ALU and Register bank.
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Segmentation Unit and Paging Unit :
They are part of MMU(which manages virtual memory of system). Helpful in generation of
Physical Address.
Work same as they work in 80386.
Floating Point Unit:
Responsible for performing the floating point operations.
The 80486 has a built in math co-processor . It performs the floating point operations.
It executes math instructions 3 times faster than the 386/387 combination.
Cache Unit:
8KB cache
Additional high speed cache memory provides a way of improving overall system
performance.
It contains the recently used instructions, data or both.
The main aim is that the microprocessor unit access code and data in the cache most of
time, instead from the main memory.
EFLAG Register
The extended flag register EFLAG is illustrated in the figure below:-
The only new flag bit is the AC alignment check, used to indicate that the microprocessor
has accessed a word at an odd address or a double word boundary.
Figure: EFLAG Register of The 80486
Unit 10 – ARM Processor
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Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing
1. ARM architecture Feature:
The ARM architecture has been designed to allow very small, yet high-performance
implementations. The architectural simplicity of ARM processors leads to very small
implementations, and small implementations allow devices with very low power consumption.
The ARM is a Reduced Instruction Set Computer (RISC), as it incorporates these typical RISC
architecture features:
A large uniform register file
A load/store architecture, where data-processing operations only operate on register
contents, not
Directly on memory contents
Simple addressing modes, with all load/store addresses being determined from register
contents and instruction fields only
Uniform and fixed-length instruction fields, to simplify instruction decode.
In addition, the ARM architecture gives you:
Control over both the Arithmetic Logic Unit (ALU) and shifter in every data-processing
instruction to maximize the use of an ALU and a shifter
Auto-increment and auto-decrement addressing modes to optimize program loops
Load and Store Multiple instructions to maximize data throughput
Conditional execution of all instructions to maximize execution throughput.
2. ARM7TDMI Processor
The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit
microprocessors.
The ARM family offers high performance for very low-power consumption and gate count.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles. The
RISC instruction set, and related decode mechanism are much simpler than those of
Complex Instruction Set Computer (CISC) designs.
This simplicity gives:
a high instruction throughput
an excellent real-time interrupt response
a small, cost-effective, processor macrocell.
The ARM7TDMI processor uses a pipeline to increase the speed of the flow of instructions
to the processor. This enables several operations to take place simultaneously, and the
processing, and memory systems to operate continuously.
Unit 10 – ARM Processor
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Figure: ARM7TDMI Core
A three-stage pipeline is used, so instructions are executed in three stages:
Fetch
Decode
Execute.
The ARM7TDMI processor has a Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Only load, store, and swap instructions can access data
from memory.
Data can be 8-bit bytes, 16-bit half-words, or 32-bit words. Words must be aligned to 4-
byte boundaries. Half-words must be aligned to 2-byte boundaries.
The ARM7TDMI processor has two instruction sets:
The 32-bit ARM instruction set
The 16-bit Thumb instruction set
Unit 01 – Introduction to Microprocessor
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Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing
1. Introduction
Microprocessor (MP) is a programmable logic device that is capable of data handling and performing data processing operations.
More elaborately, it is –
Digital device: understands binary.
Programmable device: It can perform multiple tasks and can be instructed (i.e. programmed) to perform specific task (within its capability)
Clock driven: requires clock for its operation.
Capable of data handling: Storing data, communicating data with other devices, etc.
Capable of data processing: Performing various arithmetic and logic operations like addition, subtraction, magnitude comparison, ANDing, ORing, etc.
Available in the form of an Integrated circuit (IC).
2. Components of Microprocessor
Primary component of any programmable system, e.g. computer, and is also referred as Central Processing Unit (CPU). CPU popularly consist of three main units viz. Arithmetic and logic unit (ALU), Register array (memory limited in size) and Control unit (CU).
Figure1: Central processing unit
ARITHMETIC AND LOGIC UNIT (ALU)
This unit performs all the logical and arithmetic operations.
Various arithmetic operations are: addition, subtraction, increment and decrement etc.
Various logical operations are: AND, OR, NOT, XOR, etc.
TIMING AND CONTROL UNIT
This unit controls the entire operations being performed by the system.
It controls the operations of ALU, input/output devices and memory unit.
This unit interprets the instructions and generates various timing and control signals.
Unit 01 – Introduction to Microprocessor
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REGISTERS
A register is a very small amount of very fast memory that is built into the CPU in order to store the current data and instructions which are being executed by the CPU.
SYSTEM BUS
A bus in a microprocessor-based system is defined as a group of separate wires which work together to perform a particular task.
A microprocessor-based system, or microcomputer, has three types of buses which combine to transfer information between the microprocessor and other parts of the system, such as memory or input/output devices.
Typical tasks performed by these buses include selecting the source or destination location address for a data transfer, actually moving the data from one part of the system to another, and finally, controlling and synchronizing the electronic devices involved in the data transfer process.
The three microprocessor buses are called the address bus, data bus and control bus, and these names give a strong clue as to their function:
1) Address Bus
The address bus contains the connections between the microprocessor and memory that carry the addresses at which the CPU is processing at that time, such as the locations that the CPU is reading from or writing to.
The width of the address bus corresponds to the maximum addressing capacity of the bus, or the largest address within memory that the bus can work with.
The addresses are transferred in binary format, with each line of the address bus carrying a single binary digit. Therefore the maximum address capacity is equal to two to the power of the number of lines present (2^lines).
2) Data Bus
This is used for the exchange of data between the processor, memory and peripherals, and is bi-directional so that it allows data flow in both directions along the wires.
The number of wires used in the data bus (sometimes known as the 'width') can differ.
Each wire is used for the transfer of signals corresponding to a single bit of binary data.
As such, a greater width allows greater amounts of data to be transferred at the same time.
3) Control Bus
The control bus carries the signals relating to the control and co-ordination of the various activities across the computer, which can be sent from the control unit within the CPU.
Each line is used to perform a specific task. For instance, different, specific lines are used for each of read, write and reset requests.
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3. Microprocessor System with Bus Organization
To design any meaningful application microprocessor requires support of other auxiliary devices.
In most simplified form a microprocessor based system consist of a microprocessor, I/O (input/output) devices and memory.
These components are interfaced (connected) with microprocessor over a common communication path called system bus. Typical structure of a microprocessor based system is shown in Figure 2.
Figure 2: Microprocessor based system
Here, microprocessor is master of the system and responsible for executing the program and coordinating with connected peripherals as required.
Memory is responsible for storing program as well as data. System generally consists of two types of memories ROM (Read only and non-volatile) and RAM (Read/Write and volatile).
I/O devices are used to communicate with the environment. Keyboard can be example of input devices and LED, LCD or monitor can be example of output device.
Depending on the application level of sophistication varies in a microprocessor based systems. For example: washing machine, computer.
03 – Microprocessor Architecture
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Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing
1. THE MAIN FEATURES OF 8085 MICROPROCESSOR:
It is an 8 bit microprocessor. It is manufactured with N-MOS technology. It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory
locations through A0-A15 The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7 Data bus is a group of 8 lines D0 – D7 It supports external interrupt request. . A 16 bit program counters (PC) A 16 bit stack pointer (SP) Six 8-bit general purpose register arranged in pairs: BC, DE, HL. It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock. It is enclosed with 40 pins DIP (Dual in line package).
03 – Microprocessor Architecture
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2. 8085 Microprocessor architecture:
Fig. 1 Block Diagram of 8085
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The architecture of microprocessor 8085 can be divided into five parts as follows:
2.1 Register Unit:
Fig. 2 Registers of 8085
General Purpose Data Register
8085 has six general purpose data registers to store 8-bit data. These registers are named as B, C, D, E, H and L as shown in fig. 1. The user can use these registers to store or copy a data temporarily during the execution of
a program by using data transfer instructions. These registers are of 8 bits but whenever the microprocessor has to handle 16-bit data,
these registers can be combined as register pairs – BC, DE and HL. There are two internal registers – W and X. These registers are only for internal operation
like execution of CALL and XCHG instructions and not available to the user. Program Counter (PC)
16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses which are why this is a 16-bit register. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next
byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one
to point to the next memory location.
Stack Pointer (SP) SP is also a 16-bit register used as a memory pointer.
It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer.
2.2 MUX/DEMUX unit
This unit is used to select a register out of all the available registers. This unit behaves as a MUX when data is going from the register to the internal data bus.
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It behaves as a DEMUX when data is coming to a register from the internal data bus of the microprocessor.
The register select will behave as the function selection lines of the MUX/DEMUX.
These registers hold the address/data, received from PC/internal data bus and then load the external address and data buses.
These registers actually behave as the buffer stage between the microprocessor and external system buses.
2.4 Control Unit:
The control unit generates signals within microprocessor to carry out the instruction,
which has been decoded. In reality it causes connections between blocks of the microprocessor to be opened or
closed, so that the data goes where it is required and the ALU operations occur. The control unit itself consists of three parts; the instruction registers (IR), instruction
decoder and machine cycle encoder and timing and control unit. Instruction Register
This register holds the machine code of the instruction. When microprocessor executes a program it reads the opcode from the memory, this
opcode is stored in the instruction register. Instruction Decoder & Machine Cycle Encoder
The IR sends the machine code to this unit. This unit, as its name suggests, decodes the opcode and finds out what is to be done in
response of the coming opcode and how many machine cycles are required to execute this instruction.
Timing & Control unit The control unit generates signals within microprocessor to carry out the instruction,
which has been decoded. In reality, it causes certain connections between blocks of the microprocessor to be opened
or closed, so that the data goes where it is required and the ALU operations occur.
1.5 Arithmetic & Logical Unit:
The ALU performs the actual numerical and logical operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’, etc.
ALU uses data from memory and from accumulator to perform the arithmetic operations and always stores the result of the operation in accumulator.
ALU consists of accumulator, flag register and temporary register.
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Accumulator The accumulator is an 8-bit register that is a part of ALU. This register is used to store 8-bit data and perform arithmetical and logical operations. The result of an operation is stored in the accumulator. It is also identified as register A.
Flags register Flag register includes five flip-flops, which are set or reset after an operation according to
the data conditions of the result in the accumulator and other registers. They are called zero (Z), carry (CY), sign (S), parity (P) and auxiliary carry (AC) flags; their
bit positions in the flag register are shown in fig. 3. The microprocessor uses these flags to set and test data conditions.
Fig. 3 Flag Register of 8085
The flags are stored in the 8-bit register so that the programmer can examine these flags by accessing the register through an instruction.
These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software instructions. For instance, JC (jump on carry) is implemented to change the sequence of a program when
CY flag is set. Z (Zero) Flag:
This flag indicates whether the result of mathematical or logical operation is zero or not. If the result of the current operation is zero, then this flag will be set, otherwise reset. CY (Carry) Flag:
This flag indicates, whether, during an addition or subtraction operation, carry or borrow is generated or not, if generated then this flag bit will be set.
AC (Auxiliary Carry) Flag:
It shows carry propagation from D3 position to D4 position.
Fig. 4 Auxiliary Carry Flag
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As shown in the fig., a carry is generated from D3 bit position and propagates to the D4 position. This carry is called auxiliary carry.
S (Sign) Flag:
Sign flag indicates whether the result of a mathematical operation is negative or positive. If the result is positive, then this flag will reset and if the result is negative this flag will be
set. This bit, in fact, is a replica of the D7 bit. P (Parity) Flag:
Parity is the number of 1’s in a number. If the number of 1’s in a number is even then that number is known as even parity number. If the number of 1’s in a number is odd then that number is known as an odd parity
number. This flag indicates whether the current result is of even parity (set) or of odd parity (reset).
1.6 Interrupt Control
The interrupt control unit has 5 interrupt inputs TRAP,RST 7.5, RST 6.5, RST 5.5 & INTR and one acknowledge signal INTA.
It controls the interrupt activity of 8085 microprocessor.
1.7 Serial IO control
8085 serial IO control provides two lines, SOD and SID for serial communication. The serial output data (SOD) line is used to send data serially and serial input data line
(SID) is used to receive data serially.
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3. 8085 PIN DIAGRAM
Fig. 5 pin diagram of 8085
Pin Function:
The following section describes pin functions
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ALE (Address Latch Enable):
This is a positive going pulse generated every time the 8085 begins an operation (machine cycle); it indicates that the bits on AD7-AD0 are address bits.
This signal is used primarily to latch the low-order address from the multiplexed bus and generate a separate set of eight address lines, A7-A0.
𝐑𝐃 (Read):
This is a Read control signal (Active Low). This signal indicates that the selected memory or I/O device is to be read and data are available on the data bus.
𝐖𝐑 (Write):
This is a write control signal (Active Low). This signal indicates that the data on the data bus are to be written into a selected memory or I/O location.
IO/𝐌 :
This is a status signal used to differentiate between I/O and memory operations.
When it is high, it indicates an I/O operation.
When it is low, it indicates a memory operation.
This signal is combined with RD (read) and WR (Write) to generate I/O and memory control signals.
S1 & S0:
These status signals, similar to IO/M, can be identify various operations, but they are rarely used in small systems.
Encoded status of the bus cycle:
Table 1 bus cycle status
AD8 – AD15Address Bus
The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes.
S1 S0 Operation
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
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READY (Input):
If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data.
If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.
HOLD (Input):
This pin indicates that another Master is requesting the use of the Address and Data Buses.
The CPU, upon receiving the Hold request will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed.
When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output): HOLD ACKNOWLEDGE
Indicates that the CPU has received the Hold request and it will relinquish the buses in the next clock cycle.
HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycles after HLDA goes low.
INTR (Input): INTERRUPT REQUEST
It is used as a general purpose interrupt.
It is sampled only during the next to the last clock cycle of the instruction.
If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.
The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.
𝐈𝐍𝐓𝐀 (Output) :INTERRUPT ACKNOWLEDGE; It is used instead of (and has the same timing as) RD during the Instruction cycle after an
INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.
03 – Microprocessor Architecture
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Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing
RESTART INTERRUPTS;
RST 5.5
RST 6.5
RST 7.5
These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted.
RST 7.5 has Highest Priority
RST 6.5 & RST 5.5 has Lower Priority.
The priority order of these interrupts is as shown above.
These interrupts have a higher priority than the INTR.
TRAP (Input): Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as
INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any
interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops.
None of the other flags or registers (except the instruction register) is affected.
The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output)
Indicates CPU is being reset and can be used as a system RESET.
The signal is synchronized to the processor clock.
SID (Input) :Serial input data line
The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.
SOD (output) :Serial output data line.
The output SOD is set or reset as specified by the SIM instruction.
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4. Basic Definitions:
Instruction Cycle
It is defined as the time required to complete the execution of an instruction.
The 8085 instruction cycle consists of one to six machine cycles or one to six operations
Machine Cycle
It is defined as the time required completing one operation of accessing memory, I/O, or acknowledging an external request.
This cycle may consist of three to six T-states.
T-state
It is defined as one subdivision of the operation performed in one clock period.
These subdivisions are internal states synchronized with the system clock, and each T-state is precisely equal to one clock period.
Unit 06 – Stack & Subroutines
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Kishan.K. Govani, EC Department
2150707 – Microprocessor and Interfacing
1. Stack:
The stack is a group of memory locations in Read/Write (R/W) Memory of microcomputer and is used to store the contents of a register, operand and memory address.
The starting location of the stack is defined by loading 16-bit address into the stack pointer, that space is reserved, usually at the top of the memory map.
Theoretically, the size of the stack is unlimited, but it is restricted only by the available R/W memory in a microcomputer system.
The stack can be initialized anywhere in the user memory map, but the stack is initialized at the highest user memory location so that there will not be any interference with the program.
In 8085, the beginning of the stack is defined in the program by using the instruction
LXI SP, 16 bit.
The 16-bit address is loaded into the stack pointer register.
Then the contents can be stored in stack memory locations by using the instruction PUSH and can be retrieved from the stack i by using the POP instruction.
The microprocessor keeps track of the next available stack memory location by incrementing or decrementing the address in the stack pointer.
The address in the stack pointer (register) always points to the top of the stack and indicates that the next memory location (SP + 1) is available to store information.
This method of information storage looks like the process of stacking books one above another.
Therefore, data is always retrieved from the top of the stack.
So data are stored in the stack on Last-In-First-Out (LIFO) principle.
The syntax of stack instructions to store data on and retrieve data from the stack are given below:
Unit 06 – Stack & Subroutines
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Kishan.K. Govani, EC Department
2150707 – Microprocessor and Interfacing
Instruction Description
LXI SP, 16-bit address
Load 16-bit address into the stack pointer register. This is a load instruction, similar to other 16-bit load instructions.
PUSH Rp
E.g.:
PUSH PSW
PUSH B
PUSH D
PUSH H
This is a 1-byte instruction and copies the contents of the specified register or index register onto the stack.
The instruction first decrements the stack pointer (register) and copies the high-order byte of the register pair of the index register on the stack location SP – 1. Then it again decrements the stack pointer and copies the low-order byte of the register pair or the index register onto the stack location SP – 2.
Instruction Description
POP Rp
E.g.:
POP PSW
POP B
POP D
POP H
This is a 1-byte instruction and copies the contents of the top two locations of the stack into the specified register pair or the index register.
First, the instruction copies the contents of the stack indicated by SP into the low-order register (for e.g., register C of the BC pair) or as a low-order byte into the index register and then increments the stack pointer to SP + 1. It copies the contents of the SP + 1 location into the high order register (for e.g., register B of the BC pair) or as a high-order byte into the index register and increments the stack pointer to SP + 2.
Fig. 1 shows a stack and stack top location. The SP register holds the address of stack top location, i.e. 8004H.
Example: A program is stored in memory locations starting from 7000H and the stack is initialized at the location 8004H.
Program
7000H – LXI SP, 8004H
7001H – PUSH D
7002H – POP D
7003H – HLT
Unit 06 – Stack & Subroutines
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2150707 – Microprocessor and Interfacing
The position of a stack before PUSH operation is depicted in fig. 1. When the program is executed, the contents of the register pair DE must be pushed to the stack.
After the PUSH operation, the stack position has been changes to 8001 H.
In the same way, the POP operation is used to transfer the contents from the stack to the register.
The stack position before and after the PUSH operation has been given in fig. 2 (a) and (b) respectively.
Fig. 3 (a) and (b) shows the stack position before and after the POP operation correspondingly.
Fig. 1 Stack and Stack Top Location
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Fig. 2 (a) Stack before PUSH operation (b) Stack after PUSH operation
Fig. 3 (a) Stack before POP instruction (b) Stack after POP instruction
Unit 06 – Stack & Subroutines
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From the above example, following points can be summarized:
1. During the executing of a program, a 16-bit address (8004H) is given to the SP register. The stack space grows upward in the numerically decreasing order of memory addresses. The contents of DE register pairs can be stored beginning from the next location (SP – 1).
2. The PUSH instructions are used to store contents of register pairs on the stack, and the POP instructions are used to retrieve the information from the stack. The address in the stack pointer register always points to the top of the stack, and the address is decremented as information is stored or retrieved, respectively.
3. The storage and retrieval of the content of registers on the stack should follow the LIFO sequence.
4. Information in the stack locations may not be destroyed until new information is stored in that memory location.
2. Subroutine:
When some operations/functions like multiplication and division are repeatedly performed in a main program like there is time delay between two operations and similar programs.
The groups of instructions are written to perform these operations and these groups of instructions are known as subroutine, which will be called by the main program whenever required.
When a main program calls a subroutine, the program execution is transferred to the subroutine and after the completion of the subroutine, the program execution returns to the main program.
The microprocessor uses the stack to store the return address of the subroutine.
For e.g., generally subroutines are written for sine, cosine, logarithms, square root, time delay multiplication functions in 8085 microprocessors.
The subroutine is implemented with two associated instructions, namely, CALL and RETURN.
CALL is used to call a subroutine and the CALL instruction is written in the main program.
RETURN is used to return from the subroutine and the Return instruction is written in the subroutine to return to the main program.
When a subroutine is called, the contents of the program counter are stored on the stack, and the program execution is transferred to the subroutine address.
When the RETURN instruction is executed at the end of the subroutine, the memory address stored in the stack is retrieved and the sequence of execution is resumed in the main program.
The syntax of CALL and RET are given below:
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Instruction Description
CALL 16-bit address Call subroutine unconditionally located at the memory address specified by 16-bit operand
This instruction places the address of the next instruction on the stack and transfers the program execution to the subroutine address.
RET Return unconditionally from the subroutine.
This instruction locates the return address on the top of the stack and transfers the program execution back to the calling program.
The general characteristics of CALL and RET instructions are given below:
1. The CALL instructions are 3-byte instruction; the second byte specifies the low-order byte, and the third byte specifies the high-order byte of the subroutine address.
2. The RET instructions are 1-byte instructions.
3. A CALL instruction must be used in conjunction with RET instruction (conditional or unconditional) in the subroutine.
The following types of subroutines generally are used in microprocessors:
2.1 Multiple Call Subroutines
Fig. 1 shows the basic concept of multiple CALL subroutines.
This is a subroutine called from many locations in the main program.
For example, the DELAY routine is a multiple call subroutine.
These types of routines are easy to trace and need minimal stack space.
Initially, stack pointer content is XX55H so that the return address can be stored on the stack.
When the CALL instruction starts to execute, the subroutine is called from the 8050H memory location.
The return address is stored on the stack and the stack pointer is decremented by two locations to XX53H.
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Fig. 1 Multiple Call Subroutines
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2.2 Nested Subroutines
When the subroutine is called by another subroutine, it is called nested subroutine.
When a subroutine calls another subroutine, all return addresses are stored on the stack.
Therefore, only the number of available stack locations limits the extent of nesting.
The structure of a nested subroutine is depicted in fig. 2.
The main program calls Subroutine I from location 8050H.
The address of the next instruction, 8053H, is placed on the stack, and the program is transferred to Subroutine I at 8150H.
During the execution of Subroutine I, Subroutine I calls Subroutine II from location 8190H.
The address 8193H is placed on the stack and the program is transferred to Subroutine II.
The sequence of execution and returns to the main program as shown in fig. 2.
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Fig. 2 Nested Subroutines
2.3 Multiple Ending Subroutines
When a subroutine can be terminated at more than one place, it is called a multiple ending subroutine, as illustrated in fig.3.
The subroutine has conditional such as RZ – Return On Zero and RC – Return On Carry.
This subroutine has an unconditional return – RET.
While the Z flag is set, the subroutine returns from location 8050H, and if the CY flag is set, it returns from location 8090H.
If neither flag is set, the subroutine returns from location 80A0H.
Fig. 3 Multiple Ending Subroutine
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3. Time Delay Loops
Microprocessors perform different operations in sequence and one operation at a time. To complete an operation, some time is required. When some time delay is required between two operations, a time delay loop is used to
provide it.
3.1 Time delay using single Register
Time delay can be generated using a register. Initially, a register is loaded with an operand or number and then the number is decremented until it reaches zero.
So a conditional jump instruction is used in a delay loop to come out from the loop. The time delay depends on the number, which is loaded in the register. Fig. 1 shows the flow chart of time delay loop using one register.
Fig. 1 Flowchart for time delay using one register
Calculation of Time Delay using One Register
The typical instructions of a time delay loop are given below:
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Memory
Address
Machine
Codes Labels Mnemonics Comments T-states
8000H 06H, 08H MVI B, 80H Initialize the B register 7
8002H 05H LOOP: DCR B Decrement B register 4
8003H C2H, 02H, 08H JNZ LOOP Jump not zero to LOOP 10/7
MVI B, 80H requires seven clock cycles.
DCR B requires 4 clock pulses.
JNZ requires 10 clock pulses during execution.
When these instructions are executed, MVI B, 80H instruction is executed once and the next two instructions are executed for N times, where N = 80 H = 128 in decimal
Hence, DCR B is executed 128 times.
The JNZ is also executed for 128 times, out of which (N – 1) = 127 times the program jumps to the level LOOP as the content of B register is not equal to zero and takes 10 states each time.
When the content of B register becomes zero, JNZ is executed and the program will out from LOOP.
For the last execution of JNZ instruction, only 7 T states are required.
The detailed execution of instructions and T states are given below:
Instructions No. of times instruction executed T states
MVI B, 80H 1 7
DCR B 128 (128 x 4)
JNZ 128 (127 x 10) + (1 x 7)
Total T states = 1796
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The no. of T states for execution of LOOP is
= (N x T states for DCR B) + (N – 1) x T states for JNZ + 7
= (128 x 4) + [(128 -1) x 10] + [7 x 1] = 1789 T states
The delay time to execute the LOOP instruction is,
TL = T x no. of T states for execution of LOOP, where T is system clock period
When the microprocessor operator in 5 MHz clock frequency,
TL = (1/5) x (10-6) x 1789 = 357.8 μS
The total time delay TD is calculated from the summation of time to execute instruction of outside LOOP, TOL and time to execute LOOP instruction, TL.
TD = TOL + TL
= [(1/5) x 10-6 x 7] + [(1/5) x 10-6 x 1789]
= 359.2 μS
3.2 Time delay using Register Pair
For example, a 16-bit operand is loaded in the DE register pair.
Then DE register pair is decremented by one using DCX D instruction.
The DCX instruction does not set the zero flag.
Therefore, additional testing will be done using some extra instructions as the JNZ instruction is executed only when the zero flag is set.
Fig. 2 Flowchart for time delay using register pair
The typical instructions of time delay loop using a register pair are given below:
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Memory
Address
Machine
Codes Labels Mnemonics Comments
T-states
8100H 11H, 00H, 80H LXI D, 8000H Initialize the DE register pair
10
8103H 1BH LOOP: DCX D Decrement DE register pair 6
8104H 7BH MOV A, E Copy the content of E register in accumulator
4
8105H B2H ORA D ORing of D with accumulator
4
8106H C2, 03H, 81H JNZ LOOP Jump not zero to LOOP 10/7
Calculation of Time Delay using Register Pair
In time delay loop using register pair, LXI D, 8000H is executed once and the other instructions DCX D, MOV A,E ORA D and JNZ are executed many times.
Instructions No. of times instruction executed T states
LXI D, 8000H 1 10
DCX D 32768 32768 x 4
MOV A, E 32768 32768 x 4
ORA D 32768 32768 x 4
JNZ 32768 [(32768 -1) x 10] + [1 x 7]
Total T states = 720903
The no. of T-states for execution of LOOP is,
TL = (N x T states for DCX D) + (T states for MOV A, E) + (N x ORA D)
+ (N – 1 x T states for JNZ) + 7 {where, N = 8000H = 3276810}
= [32768 x (4 + 4 + 4)] + [(32768 - 1) x 10] + [1 x 7]
= 720893
If the microprocessor clock frequency is 5 MHz, time delay in LOOP is equal to TL.
TL = T x no. of T states for execution of LOOP
= (1/5) x 10-6 x 720893
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= 144.1786 msec
The total time delay TD is calculated from the summation of time to execute instruction of outside LOOP, TOL, and time to execute LOOP instruction, TL.
TD = TOL + TL
= [(1/5) x 10-6 x 10] + [(1/5) x 10-6 x 720893]
= 144.1806 msec
3.3Time delay using two loops
The time delay can also be generated by using two loops as depicted in Fig. 3.
The C register is used in the inner loop (LOOP – 1) and B register is used in the external loop (LOOP – 2).
Here, both B and C registers are loaded with numbers.
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Fig. 3 Flowchart for time delay using two loops
The C register is decremented until it becomes zero.
When the content of C register is zero, decrement B register.
If the content of B register is not zero, load the C register with initial value and repeat the process.
The example of time delay using two loops is given below:
Memory
Address
Machine
Codes
Labels
Mnemonics Comments T-
states
8200H 06H,08H MVI B, 80H Initialize B register 7
8202H 0EH,FFH LOOP2
MVI C, FFH Initialize C register 7
8204H 0DH LOOP1
DCR C Decrement C register 4
8205H C2H,04H,82H JNZ LOOP1 Jump not zero to LOOP1 10/7
8208H 05H DCR B Decrement B register 4
8209H C2H,02H,82H JNZ LOOP2 Jump not zero to LOOP2 10/7
820CH C9H RET Return to main program 10
In time delay generation using two loops as given above MVI B, 80H is executed once and the other instructions MVI C, FFH , DCR C, JNZ, DCR B and JNZ are executed for many times.
The detail execution of instructions and T states are given below:
Instructions No. of times instruction executed T states
MVI B, 80H 1 7 x 1
MVI C, FFH 128 128 x 7
DCR C 255 x 128 255 x 128 x 4
JNZ LOOP1 255 x 128 [(255 -1) x 128 x 10] + [1 x 7]
DCR B 128 128 x 4
JNZ LOOP2 128 [(128 - 1) x 10] + [1 x 7]
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RET 1 10 x 1
Total T states = 458389
Time delay will be calculated based on the time delay for LOOP1 and LOOP2. Total no. of T states for LOOP1 and LOOP2 are equal to
= [128 x 7] + [255 x 128 x 4] + [(255 - 1) x 128 x 10] + [1 x 7] + [128 x 4] + [(128 – 1) x 10] + [1 x 7] = 458372
If the microprocessor clock frequency is 5 MHz, time delay in LOOP1 and LOOP2 is equal to TL,
TL= T x no. of T states for execution of LOOP1 and LOOP2 = (1/5) x 10-6 x 458372
= 91.674 msec Total delay time,
TD = TOL + TL = [(1/5) x 10-6 x 17] + 91.6744 msec = 91.677 msec
4. BCD Arithmetic
4.1 BCD to Binary Conversion
Convert a 2 digit BCD number stored at memory address 2200H into its binary equivalent number
and store the result in memory location 2300H.
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Flowchart
Program:
LDA add
MOV B,A
ANI 0FH
MOV C,A
MOV A.B
ANI F0H
RRC
RRC
RRC
RRC
MOV B,A
XRA A
MVI D, 0AH
X: ADD D
DCR B
JNZ X
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ADD C
STA 2300H
HLT
4.2 Binary to BCD Conversion
Flowchart
Program:
START: LXI SP,STACK
LXI H,BINBYT
MOV A,M
CALL PWRTEN
HLT
PWRTEN: LXI H,OUTBUF
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MVI B, 64H
CALL BINBCD
MVI B, 0AH
CALL BINBCD
MOV M,A
RET
BINBCD:
MVI M,FFH
NXTBUF: INR M
SUB B
JNC NXTBUF
ADD B
INX H
RET
4.3 BCD to Seven Segment Code Conversion
A set of five packed BCD numbers are stored in memory location starting at 6000H. The seven segment codes of digits 0 to 9 for LED are stored in memory location starting at
6200H and output store at 7000h and select an appropriate seven segment code for each digit.
Program:
LXI H,6200H LXI D,6000H LXI B,7000H BACK : LDAX D MOV L,A MOV A,M STAX B INX D INX B MOV A,C CPI O5H JNZ BACK HLT
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4.4 Binary to ASCII Code
Write a program to convert the content of 5 memory locations starting from 2000H into ASCII character. Place the result in five memory locations starting from 2200H.
LXI SP, 27FFH
LXI H, 2000H
LXI D, 2200H
MVI C, 05H
X: MOV A,M
CALL ASCII
STAX D
INX H
INX D
DCR C
JNZ X
HLT
ASCII: CPI 0AH
JNC Y
ADI 30H
JMP Z
Y: ADI 37H
Z: RET
4.5 BCD Addition
Add two 2-digit BCD numbers in memory location 2200H and 2201H and store the result in memory location 2300H.
LXI H, 2200H
MOV A,M
INX H
ADD M
DAA
STA 2300H
HLT
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4.6 Subtraction of Two BCD Numbers
Subtract the BCD number stored in E register from the number stored in D register.
Process:
(i) Find 100’s complement of subtrahend
(ii) Add two numbers using BCD addition
MVI A, 99H
SUB E
INR A
ADD D
DAA
HLT
Unit 9 – SUN SPARC Microprocessor
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Kishan.K. Govani, EC Department | 2150707 – Microprocessor and Interfacing
1. INTRODUCTION
SPARC is an acronym for Scalable Processor ARChitecture
Designed to optimize compilers and pipelined hardware implementations.
Offers fast execution rates.
SPARC, formulated at Sun Microsystems in 1985, is based on the RISC I & II designs
engineered at the University of California at Berkeley from 1980 through1982.
SPARCs are load/store RISC processors. Load/store means only loads and stores access
memory directly.
RISC (Reduced Instruction Set Computer) means the architecture is simplified with a
limited number of instruction formats and addressing modes.
SPARC was designed as a target for optimizing compilers and easily pipelined hardware
implementations.
SPARC implementations provide exceptionally high execution rates and short time-to-
market development schedules.
A SPARC processor logically comprises an integer unit (IU), a floating-point unit (FPU), and
an optional coprocessor (CP), each with its own registers.
All of the registers with the possible exception of the coprocessor’s — are 32 bits wide.
The processor can be in either of two modes: user or supervisor.
1) Supervisor Mode: The processor can execute any instruction, including the
privileged (supervisor-only) instructions.
2) User Mode: An attempt to execute a privileged instruction will cause a trap to
supervisor software. “User application” programs are programs that execute while
the processor is in user mode.
2. FEATURES:
Performance and Economy
Simplified instruction set
Higher number of instructions with fewer transistors
Scalability
Flexible integration of cache, memory and FPUs
Open Architecture
Compatible technology to multiple vendors
Base on RISC Architecture
64-bit addressing and 64-bit data bus
Increased bandwidth
Fault tolerance
Nine stage pipeline; can do up to 4 instructions per cycle
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On-chip 16Kb data and instruct caches with 2Mb external cache
A large “windowed” register file — at any one instant, a program sees 8 global integer
registers plus a 24-register window into a larger register file. The windowed registers can
be described as a cache of procedure arguments, local values, and return addresses.
3. Architecture
Figure: SUN Super SPARC Architecture
The SPARC processor is divided into three parts:
1) an Integer Unit (IU)
2) a Floating-Point Unit (FPU)
3) an optional CoProcessor (CP)
each with its own registers. (32-bits wide)
3.1 Integer Unit
Contains the general purpose registers and controls the overall operation of the processor.
May contain from 64 to 528 general-purpose 64-bit r registers. They are partitioned into 8
global registers, 8 alternate global registers, plus a circular stack of from 3 to 32 sets of 16
registers each, known as register windows.
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Executes the integer arithmetic instructions and computes memory addresses for loads
and stores.
Maintains the program counters and controls instruction execution for the FPU.
The Register Window
At any time, an instruction can access the 8 global registers and a 24-register window
A register window comprises a 16-register set- divided into 8 in and 8 local registers-
together with the 8 in registers of an adjacent register set, addressable from the current
window as its out registers.
When a procedure is called, the register window shifts by sixteen registers, hiding the old
input registers and old local registers and making the old output registers the new input
registers.
Input registers: arguments are passed to a function
Local registers: to store any local data.
Output registers: When calling a function, the programmer puts his argument in these
registers.
The current window into the r registers is given by the current window pointer (CWP)
register.
Fig: Three overlapping register windows
The active window is identified by the 5-bit Current Window Pointer (CWP).
Decrementing the CWP at procedure entry causes the next window to become active.
Incrementing the CWP at procedure entry causes the previous window to become active.
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Fig: Eight register windows forming a circular stack
Register window overflow and underflow conditions are handled in software by a kernel
trap handler.
The Window Invalid Mask (WIM) can tag any window so that an overflow or underflow
trap is generated whenever the CWP is about to point a tagged window.
ADVANTAGE
Make very fast procedure calls as they avoid the need to save a processor’s current in
memory, further reducing off-chip traffic.
Instead, the state variables are held in the current window, and the next window is opened
for the new procedure.
A refinement on this idea in that the input and output registers of adjacent windows
overlap, allowing variables and parameters to be passed to the next process without
physically moving data.
The additional registers are hidden from view until you call a subroutine or other function.
Where other processors would push parameters on a stack for the called routine to pop off,
SPARC processors just "rotate" the register window to give the called routine a fresh set of
registers.
The old window and the new window overlap, so that some registers are shared.
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3.2 Floating-point Unit (FPU)
The FPU has 32 32-bit (single-precision) floating-point registers, 32 64-bit (double-
precision) floating-point registers, and 16 128-bit (quad-precision) floating-point registers.
Double-precision values occupy an even-odd pair of single-precision registers.
Quad-precision values occupy an odd-even number pair of double precision registers.
Floating-point load/store instructions are used to move data between the FPU and
memory.
The memory address is calculated by the IU.
Floating-Point operate (FPop) instructions perform the floating-point arithmetic
operations and comparisons.
3.3 Coprocessor Unit (CU)
The instruction set includes support for a single, implementation-dependent coprocessor.
The coprocessor has its own set of registers.
Coprocessor load/store instructions are used to move data between the coprocessor
integer data types that are signed and unsigned bytes
16-bit half words
32-bit words
64-bit double words.
There is a tagged word format in which the 2 least significant bits serve as flags to indicate
the type of object.
The floating point numbers can be 32(single), 64 (double), or 128 (quad) bits long; they
conform to the IEEE 754 standard.
SPARC is "big-endian"- it stores multiple byte objects in memory with the most significant
byte at the lowest address.
5. SPARC Instruction Types
There are very few addressing modes on the SPARC, and they may be used only in certain very restricted combinations. The three main types of SPARC instructions are given below, along with
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the valid combinations of addressing modes. There are only a few unusual instructions which do not fall into these categories.
1. Arithmetic/Logical/Shift instructions
opcode reg1,reg2,reg3 !reg1 op reg2 -> reg3
opcode reg1,const13,reg3 !reg1 op const13 -> reg3
All "action" instructions (add, sub, and, or, etc.) take three operands.
The destination is always the third operand.
The middle operand may be a 13-bit signed constant (-4096...+4095).
Otherwise, all operands are registers.
Examples:
add %L1,%L2,%L3 !%L1+%L2->%L3
2. Load/Store Instructions
opcode [reg1+reg2],reg3
opcode [reg1+const13],reg3
Only load and store instructions can access memory. The contents of reg3 is read/written from/to the address in memory formed by adding
reg1+reg2, or else reg1+const13 (a 13- bit signed constant as above). The operands are written in the reverse direction for store instructions, so that the
destination is always last. One of reg1 or const13 can be omitted. The assembler will supply $g0 or 0. (This is a
shorthand provided by the assembler. Both are always there in machine language.) Examples:
ld [%L1+%L2],%L3 !word at address [%L1+%L2]->%L3
3. Branch Instructions
opcode address
Branch to (or otherwise use) the address given. There are actually 2 types of addresses but they look the same. Examples: