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UNDERSTANDING THE PHYSICS OF HARD AND SOFT FAILUREIN SILICON-GERMANIUM HETEROJUNCTION BIPOLAR

TRANSISTORS

A ThesisPresented to

The Academic Faculty

By

Rafael Perez Martinez

In Partial Fulfillmentof the Requirements for the Degree

Master of Science in theSchool of Electrical and Computer Engineering

Georgia Institute of Technology

May 2019

Copyright c© Rafael Perez Martinez 2019

UNDERSTANDING THE PHYSICS OF HARD AND SOFT FAILUREIN SILICON-GERMANIUM HETEROJUNCTION BIPOLAR

TRANSISTORS

Approved by:

Professor John D. CresslerSchool of Electrical and ComputerEngineeringGeorgia Institute of Technology

Professor Hua WangSchool of Electrical and ComputerEngineeringGeorgia Institute of Technology

Professor J. Stevenson KenneySchool of Electrical and ComputerEngineeringGeorgia Institute of Technology

Date Approved: April 26, 2019

To my parents,

for always supporting my education.

ACKNOWLEDGEMENTS

Coming all the way from Oaxaca, Mexico, to study in the US has been a privilege

for me. Many people take for granted what is like to have access to a world-class

education and do not make full use of such opportunities. I am very fortunate to

have done my bachelor and master’s degrees at Georgia Tech. Most importantly, I

am very fortunate to have learned many valuables life lessons in the last six years.

Georgia Tech has taught me to persevere anything that comes at me, regardless of

its size or difficulty. It has taught me to become a risk-taker and attempt to do the

“impossible.” But most importantly, it has taught me that hard work really pays off.

I would like to first thank my research advisor Prof. John D. Cressler for believing

in me. Not many people can say that they had the opportunity to work with a world-

class researcher, a passionate teacher, and an outstanding mentor. I can proudly say

I belong to that privileged group of students. Without his constant guidance and

support during the last four years, I would not be the microelectronics researcher

that I am today. His passion for teaching, research, and mentoring inspire me each

day I step into the lab. I hope to one day pursue the academic path and become a

professor like himself once I complete my Ph.D. in electrical engineering.

I would also like to thank the members of my reading committee: Prof. Hua

Wang and Prof. J. Stevenson Kenney. I appreciate the time taken from their busy

schedules to provide me with helpful feedback on this thesis in addition to being my

teachers at Georgia Tech.

Additionally, I would like to thank all the members of the SiGe Circuits and

Devices Team at Georgia Tech. In particular, I would like to thank Dr. Uppili S.

Raghunathan, Dr. Brian R. Wier, Hanbin (Victor) Ying, Harrison Lee, Dr. Zachary

E. Fleetwood, Dr. Michael A. Oakley, Delgermaa Nergui, Dr. Anup Omprakash,

Prof. Saeed Zeinolabedinzadeh, Sunil Rao, Arya Moradinia, Yunyi Gong, and Jeffrey

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Teng for all of their help and technical support.

A big thank you to Prof. Christina Bourgeois for her support in technical writing

and general life advice. I enjoyed my time being a GTA for your ECE 3005 class.

I am also in debt with Prof. Biing-Hwang (Fred) Juang for his constant support

and guidance at Georgia Tech. I learned so much from you since my second-year of

my undergraduate studies.

I would like to acknowledge Prof. Paul L. Voss, Dr. Chris Bishop, and Dr. Yacine

Halfaya from Georgia Tech Lorraine for introducing me to the realm of microelec-

tronics back in Summer 2015.

Special thanks to my past and present friends at Georgia Tech. In particular, I

would like to thank Jack Zhang, Erick Leal, Eugene Bouya, Ahmed Elsabbagh, Ben

Nguyen, Fares Elsabbagh, Sanghoon Lee, Yusuf Kuris, Chris Tran, David Munzer,

Lara Orlandic, Karan Shah, Neel Shah, and Fernando Lopes. All of you guys made

my last six years at Georgia Tech “bearable.”

Lastly, I would like to thank my amazing parents, Margarita and Rafael, and my

sisters, Zenhia and Karina. Without their love and support in the past 23 years, I

would not have made it through this long and difficult journey.

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TABLE OF CONTENTS

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 SiGe BiCMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 The SiGe HBT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Avalanche Multiplication due to Impact Ionization . . . . . . . . . . 4

1.4 Breakdown Voltages and Base Current Reversal . . . . . . . . . . . . 6

2 Reliability Physics of SiGe HBTs . . . . . . . . . . . . . . . . . . . . 8

2.1 Damage Spectrum of SiGe HBTs . . . . . . . . . . . . . . . . . . . . 9

2.2 Mixed-Mode Stress Degradation . . . . . . . . . . . . . . . . . . . . . 10

2.3 High-Current Stress Degradation . . . . . . . . . . . . . . . . . . . . 12

2.4 Current Gain Enhancement Effects (CGE) in SiGe HBTs . . . . . . 14

3 Hard Failures and Maximum Usable Range of SiGe HBTs . . . . 17

3.1 Physics of Hard Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.2 Measurement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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3.3 Analysis of Measurement Results . . . . . . . . . . . . . . . . . . . . 22

3.3.1 Geometry Dependence . . . . . . . . . . . . . . . . . . . . . . 23

3.3.2 Layout Configuration Dependence . . . . . . . . . . . . . . . . 25

3.3.3 Temperature Dependence . . . . . . . . . . . . . . . . . . . . 27

3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 Soft Failure Mechanisms in High-Breakdown SiGe HBTs . . . . . 30

4.1 Testing Set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 The Medium-Breakdown SiGe HBT . . . . . . . . . . . . . . . . . . . 34

4.3 Mixed-Mode Stress Degradation in Medium-Breakdown SiGe HBTs . 37

4.4 High-Current Stress Degradation in Medium-Breakdown SiGe HBTs . 38

4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.1 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2.1 Modeling Hard Failures in SiGe HBTs . . . . . . . . . . . . . 45

5.2.2 TCAD Modeling of Soft Failure Mechanisms in Medium-BreakdownSiGe HBTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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SUMMARY

The objective of this work is to investigate hard and soft failure mechanisms

observed when silicon-germanium heterojunction bipolar transistors (SiGe HBTs) are

operated outside of traditionally defined electrothermal safe operating areas (SOAs).

In Chapter 1, the need for studying the reliability physics of SiGe HBTs is mo-

tivated. Important physical mechanisms in SiGe HBTs such as avalanche multipli-

cation, breakdown mechanisms, and base current reversal are briefly discussed to

provide some insight on the physics of failure in later chapters.

Chapter 2 provides an overview of the reliability physics of SiGe HBTs. The

damage spectrum of the SiGe HBT is introduced in order to showcase the different

soft failure mechanisms when operating a SiGe HBT in typical RF and mixed-signal

circuits. All of the relevant damage mechanisms in scaled SiGe HBTs are described

in greater detail to understand the impact on overall device performance.

Chapter 3 introduces the concept of hard failures in SiGe HBTs. A new failure

metric in SiGe HBTs, known as the hard failure point, is proposed in order to provide

additional understanding to the physics of hard failure. This failure metric represents

the bias condition at which the device transistor action fails, and the device becomes

purely resistive as a result of catastrophic junction failure. An advanced SiGe HBT

technology (GlobalFoundries 9HP) was chosen and measured in a variety of ways

as a function of geometry, layout configuration, and temperature. Through TCAD

simulations and experimental data, two modes of failures in SiGe HBTs were shown.

The takeaway is that knowing specific details, such as the exact location of hard

failures, the physics that drives them, and what they depend upon, can greatly aid

circuit designers to exploit the design space between PDK specified SOAs and hard

failures. The analysis presented in Chapter 3 has been published and presented at

the 2017 IEEE Bipolar/BiCMOS Circuits and Technology Meeting [1].

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Chapter 4 presents the use of high-breakdown SiGe HBTs in RF integrated cir-

cuits. A medium-breakdown variant in a fourth-generation SiGe BiCMOS technol-

ogy is described from a processing perspective to understand any subtle differences

between its high-performance counterpart. Reliability stress measurement data is

shown to provide insight into the differences between high-performance and medium-

breakdown SiGe HBTs when biased under high-current and mixed-mode stress condi-

tions. Trade-offs in reliability and performance are described to showcase advantages

and disadvantages when using either device variant. Part of the analysis presented

in Chapter 4 will be submitted for publication to the 2019 IEEE BiCMOS and Com-

pound Semiconductor Integrated Circuits and Technology Symposium.

Lastly, Chapter 5 summarizes the contributions presented in this thesis. A future

work section is provided to showcase any additional research work that will result

from the analysis done in Chapter 3 and 4.

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