Understanding the Optimized Power Supply Designs on the ... · Multi-phase Power devices optimized for Freescale T-Series QorIQ Processors to meet the dynamic, tight design requirements

1

Understanding the Optimized Power

Supply Designs on the QorIQ T-Series

Freescale Processors

– FTF-NET-F0432 How to Achieve < 3% Accuracy

Brooks Bailey – Sr. Application Engineer

Tony Ochoa – Sr. Marketing Manager

April 2014

For complete design information

http://mypower.irf.com/Freescale

•What are you going to learn?

• Who is IR and why they are “Proven Partner”

• The challenging power supply requirements of T-series

• How IR regulators helped Freescale solve the problem

• The power architecture of T4, T2, T1 Ref Designs

• How to modify the design for your own application

• Where to go for more information on T-series reference designs

powered by IR

Introduction

2

Who is IR

3

Enterprise

Power

Server

NetCom

Computing

Gaming

Automotive

Power Steering

Fuel Injection

Power Train

HID Lighting

Glow Plugs

Energy Saving

Products

Appliance

Display

Audio

Lighting

Industrial

Power Management

Devices

Consumer

Computing

Data and Telecom

Industrial

HiRel

Satellite

Aviation

Medical

Defense

Industrial

Digital &

Analog Voltage

Regulators

MOSFETs,

IGBTS,

Diodes,

Relays

DC/DC Converters

AC/DC Converters

Motor Controllers

- #1 MOSFET supplier in the World

- Pioneer & major supplier of Digital DC/DC Converters

- Major supplier of Analog DC/DC to Comms/Computing

International Rectifier is a “Proven Partner” on

Freescale’s Connect Program:

• All T-series reference designs fhave been carefully

tested by Freescale and International Rectifier to

insure strict adherence to the 3% specification.

• Results include scaling processor cores from

24 Cores to 4 Cores with Dhrystone Code.

• Design verified with Freescale on the RDB/QDS

boards and given to ODM/IDH partners to seed

production level reference designs

Use these reference designs “exactly as-is”

to ensure < 3% specification adherence.

Proven Partner Reference Designs

4

< 3%

voltage

accuracy T-Series QorIQ

IRF and Freescale collaboration

of a Power design

to scale from T4 to T1 processors

http://mypower.irf.com/Freescale

For Complete Design Information

Pre Calibrated Digital Controllers for T-series

• International Rectifier offers PRE-CALIBRATED

Multi-phase Power devices optimized for

Freescale T-Series QorIQ Processors to meet the

dynamic, tight design requirements from 10A to

80A for the core and memory rails.

You Don’t Do Any Configuration!

•All other IR devices in the power solution are

Analog (SupIRBucks & FETs) for the peripheral,

I/O & rails measurement & control.

5

Core and Memory Power

For T4 Designs:

IR3565BMFS01TRP

For T2/T1 Designs:

Core+DDR:

IR36021MFS01TRP

Core Only:

IR36021MFS02TRP

Samples Orderable at Digikey: Click this Link for IR3565BMFS01TRP at Digikey

Click this Link for IR36021MFS01TRP at Digikey

Click this Link for IR36021MFS02TRP at Digikey

The Challenge of QorIQ T-series:

Must meet < 3% total Voltage accuracy

6

Comparison of P- & T- Series Voltage Specs

7

Specification P-series T-series

Total TOB (AC, DC, Ripple) +/- 50mV (~ 5%) +/- 30mV (~ 3%)

Vos Allowance (mV) +100mV +50mV

Max Transient Loadstep

(best estimate) 16A @ 8A/uS 20A @ 12A/uS

VID Range 0.9V – 1.1V, 12.5mV LSB 0.9V – 1.1V, 12.5mV LSB

Vboot 1.05V, 1.035V 1.05V, 1.035V

• The T-series has a much tighter accuracy requirement and more strenuous transient

loadsteps. Thus P-series voltage regulators cannot be used. Instead, only voltage

regulators designed and verified for T-series should be used.

Why can’t I use my P-series power supply?

Does not have the required initial set-point accuracy

Does not have the bandwidth for the new fast, dynamic slew rates

Would require prohibitively expensive and bulky extra output caps

Why have the specs changed for T-series

8

P-series T-series Impact on Power Supply

45nm 28nm

Redesign for Increased accuracy due to

prevent voltage over-stress/reliability

issues with finer geometry process

Single Core Multi core Redesign for fast, dynamic slew rates

due to multi-core control

P- to T- Series SEVERE ACCURACY CHANGE!

• A simple analysis of the P-series and T-series specifications shows that T-

series would require nearly double the output capacitance of a P-series:

• ACCURACY +/- 50mV (5% TOB) +/-30mV (3% TOB)

• Total window has reduced from 100mV to 60mV, i.e. 40mV (40%) less!

• 100mV is about 1.67 * 60mV, so therefore CNEW ≤ 1.67 * COLD

• We conclude we need 1.67 x Cout_without changing anything else! This is a

very big change from previous generation and special care must be taken to

achieve 3% TOB capability.

• TRANSIENT 16A @ 8A/uS 20A @ 12A/uS (Educated Assumption)

• 16A in 2,000nS vs 20A in 1,667nS 1.5x the loadstep…

• This would indicate an additional 1.5x Cout… If our Vos was comparable!

VOS SPEC +100mV +50mV

• This would indicate an additional Cout requirement to satisfy Vos…

• Since we don’t want to just keep adding Cout (cost & space) to solve our

issue, what are our options?

9

How IR Converters helped Freescale

solve the power supply challenge

10

T2080 RDB Schematic for the Core Rail

11

Pre calibrated Digital

Controller IR3565BFS01 PowIRStages

(Driver+FETS) IR3550

Note: IR regulators for Memory

& Peripheral rails not shown.

Consult Reference Design.

Definitions

• VID = Vout set point, settable via I2C / PMBus (5mV LSB).

• Total TOB (Accuracy) = DC TOB + Vripple + AC TOB.

• DC TOB = difference between VID & output voltage during constant DC load (DMM).

• Vripple = Total dV across Vsen/Vrtn during constant DC load, constant VID (O-Scope).

• AC TOB = Total dV across Vsen/Vrtn during max loadstep / transient (O-Scope).

12

• Vdroop (Droop) = ABS MIN output

voltage level during Load Step,

referenced to VID.

• Vos (Overshoot) = ABS MAX output

voltage level during Load Release,

referenced to VID.

• Tos (Duration of Overshoot) =

Total excursion time that output

voltage is above the Total TOB limit.

3% total

accuracy

e.g. 12.0V to 1.0V, 4-Φ, 150nH, 400kHz Fsw

IR Regulator Accuracy Stack-up

COMPANY CONFIDENTIAL 13

Sources of inaccuracy IR Digital

Controllers Typical

Analog Competition

Initial Vref Accuracy over temp 0.3% (3mV) 1% (10mV)

NTC, FB resistors, etc. 1% (10mV) 1% (10mV)

Parasitic drop without differential remote sense 0% (0mV) 1.5% (15mV)

Low frequency ripple due to PWM jitter 0.2% (2mV) 0.5% (5mV)

Transient under/overshoot (Ex. 20A step) 1% (10mV) 2% (20mV)

Ripple due to PWM switching 0.5% (5mV) 0.5% (5mV)

TOTAL Error Stack Up (Worst Case) 3.0% (30mV) 6.5% (65mV)

IR achieves over 2X Better Accuracy (across temperature & current) than Analog Competition

The Ref Designs are carefully optimized for accuracy

The Ref Designs are finely tuned to meet 3% accuracy without incurring

extra cost and space:

1. Total Output Capacitance – Cout (uF)

• Kept to a minimum. Adding output capacitance is effective but costly!

2. # of Phases – n

• Adding more phases will help Droop but hurt costs & light-load efficiency.

3. Inductor Value – L (uH)

• Lowering L value will help Droop but make Overshoot worse.

4. Switching Frequency – Fsw (kHz)

• Increasing Fsw will help Droop, but make Efficiency worse.

5. Lower the ESL / ESR of the path from inductors to CPU

• Add more Copper, VIAs, etc.

• Remove Sense resistor, load switches and other resistive elements in load path

• Helps Droop & Overshoot

14

• The accuracy is related to how well the current is

sensed. This is largely dependent upon the current

sense amplifier and the temperature matching of

the inductor. IR’s digital controllers control these

parameters very carefully:

• Each phase uses Low offset differential current

sense amplifiers. The outputs of the amplifiers

are summed together internally

• Total current offset is trimmed to better than

0.00036mV*(loadline/DCR) at the factory

• Individual channel offsets are captured

digitally at startup and nulled for phase

balance

• An External RC network is used to set the

loadline and bandwidth

• A thermistor in the feedback provides

temperature compensation for the inductor

winding

Ref Design contains the optimized values

Controller is optimized for accuracy over temperature

Loadline and Temp Comp Circuit

Isense Amplifier Circuit

15

Ref Design Layout is optimized for 3% accuracy

16

The IR controller parameters and the Freescale reference designs have been fully

optimized for accuracy, thus the only remaining source of inaccuracy is in the layout. The

Freescale reference layout is also fully optimized and it is important that the layout is

maintained as is. In particular:

• Via placement for decoupling caps as the

placement affects the loop inductance:

• Placement of the input and out

decoupling caps (4 phase design

example):

Ref Design Layout optimizations continued...

17

• Use Kelvin sense connections (for

the DCR circuit) at points where

there is no current flow

• Recommended placement of small signal

components

T4240RDB Test Results

16A Load-Step (37.5A – 53.5A)

Vmin = 1.0250V

Droop ~ 25.0mV

TOB = +/- 30.0mV

Margin = 5.0mV

18

16A Load-Release (53.5A – 37.5A)

Vmax = 1.0796V

Overshoot ~ 29.6mV

TOB = +/- 30.0mV

Margin = 0.4mV

24 COREs using Freescale’s Dhrystone Code

(12.0V to 1.00V, Fsw=400kHz, L=150nH, 4Φ, 12 Bulk + 112 MLCC ~ 6,850uF Cout)

T4240RDB Test Results

Vmin = 1.0409V

Droop ~ 9.1mV

TOB = +/- 30.0mV

Margin = 20.9mV

19

8 COREs using Freescale’s Dhrystone Code

Vmax = 1.0629V

Overshoot ~ 12.9mV

TOB = +/- 30.0mV

Margin = 17.1mV

5A Load Release (42.5A – 37.5A) 5A Loadstep (37.5A – 42.5A)

Freescale’s QorIQ T-Series

Reference Designs

20

Freescale T4240 RDB Power Delivery System

IR Digital Power Multiphase solution

• High density, High efficiency

• Telemetry delivering system voltages,

currents, temperatures and faults

• Power Savings Modes

• IR Power Devices (PowIRstages)

• 3 Devices in 1 package for highest density,

• Exceptionally high current handling with very

low thermal operation

• Scalable solution for higher or lower current

• IR Analog point-of-load SupIRbuck devices

chosen for

• Very low noise with best-in-class low jitter

• High (<0.5%) native accuracy

• Scalable portfolio of efficient devices

T2080PCIE Reference Design

22

IR36021FS02

IR3553

IR3553 IR3473

IR3473

IR3473

IR3473

IR3473

IR3473

IR3475

1.0V

1.5V

2.5V

3.3V

1.8V

1.35V/1.5V DDR

0.67V

0.78V

5V

IR3473

IR3473 Vcore

12V Multiphase

Controller PowIRStage

Point-of-Load Regulators

T1042RDB Reference Design – Energy Star Rated!

23

IR3473

IR3473

IR3473

IR3473

Vcore

1.35V

1.8V

1.5V

2.5V

3.3V

IR3475

IR3473

5V_Slp Point-of-Load Regulators

How to Adapt the Reference Designs

24

Providing Scalable Power vs. Scalable Multi-Thread Processing Cores

25

DCCALIBRATION

FORACCURACY

TRANSIENTVS

LOAD

STABILITY

COMPONENT

SELECTION

LAYOUT

T4 - Series

24 Cores

T2 - Series

8 Cores

T1 - Series

4 CoresMulti-phase

Power Controller

+ Power Stage

(Pre-calibrated

for each T-series)CORE + Memory

Bus & I/O

PM Regulation,

Monitors,

& Control

SupIRBuck

Regulators

FETs

Logic Control,

Low Rds ON,

Current monitors,

Load control

OPTIMIZED POWER SOLUTIONMULTI-THREAD CORES

8WTO 60W

INTERNATIONAL RECTIFIER’S

OPTIMIZED POWER SOLUTIONS

FOR

VARIOUS MULTI-THREAD PROCESSOR CORE

(T4, T2, T1 SERIES)

Need

Various Power Solutions

for the entire

QorIQ T-series

Core Rail: Scale the PowIRstage

26

Part

Number

Current

Rating

Package

IR3550 60A PQFN 6x6 Footprint

Compatible IR3551 50A PQFN 5X6

IR3553 40A PQFN 4x6

IR3742 20A PWFN5x6

1

2

3

4

5

31

32

6

7 8 9 10 11 12 13 14 15

16

17

18

19

29 28 27 26 25 24 23 22 2130 20

IR3550

Integrated PowIRstages: Universal Layout

27

IR3551 IR3553

28

Other Rails: Scale the Regulator

4x5 mm ~2-10A

5x6 mm ~ 6-25A

5x7 mm ~20A-35A

1A 35A SupIRBuck

~ 1-3A 3.5x3.5 mm

SupIRBuck Gen 3

Single Output

Part

Current Pkg

Size

Dual Output

Part

Current Pkg

Size

IR3823 3A 3.5x3.5

Footprint

Compatible

IR3897 4A 4x5 IR3891 4A + 4A 5x6

IR3898 6A 4x5 IR3892 6A + 6A 5x6

IR3899 9A 4x5

Footprint

Compatible

IR3894 12A 5x6

IR3895 16A 5x6

Footprint

Compatible

IR3847 25A 5x6

IR3846 35A 5x7

IR CONFIDENTIAL

How To Validate for 3% Accuracy Specification

• Initial Power-on

• Only after ensuring Vin (12V), Vcc_ctl (3.3V) and Vdrv (5V) are all up and running,

enable the VR(s) w/ EN switch (HW PIN).

• Check DC RMS level of Vout and use offset to get to desired value.

• Ensure DC Ripple is reasonable for Fsw / L value, etc.

• DC Validation

• Test a “known” current and ensure our current reporting is accurate. If it is

NOT accurate enough, refer to DC Tuning note (only when needed).

• AC Validation

• We need to ensure we can maintain +/- 3% TOB for the largest loadstep

the CPU can produce. Freescale will provide software to exercise ALL

Cores at 100%, etc. Run this and ensure Vsen/Vrtn Vpk-pk < 3% TOB.

Refer to AC Tuning note only if not passing AC spec as-is. Remember you

have an additional +50mV Vos allowance.

29

Ordering Codes for the

Pre-calibrated Devices

For T4 Designs:

IR3565BMFS01TRP

For T2/T1 Designs:

Core+DDR:

IR36021MFS01TRP

Core Only:

IR36021MFS02TRP

All other devices are standard

parts and Standard ordering

• Ref Designs utilize IR Digital Converters, Analog Converters and MOSFETs

• Ref Designs have been tested by Freescale/IR and are built into RDB/QDS systems at

the ODM/IAH partners

• Use Ref Designs are optimized for peroformance/cost for T4, T2, T1

• Use Ref Designs “as is” for simplicity and are easily scalable for your own needs

Summary

30

IR Part# QorIQ Description

CPU Core & Memory Voltage

IR3565BFS01 T4 core + memory digital voltage controller

IR36021FS01 T2, T1 core + memory digital voltage controller

IR36021FS02 T2, T1 core digital voltage controller

I/O & Peripheral rails

IR3823 T4, T2, T1 3A regulator

IR3897/8/9/4/5 T4, T2, T1 4A/6A/9A/12A/15A regulators

IR3891/2 T4, T2, T1 dual 4A+4A, 6A+6A regulators

IR3473/5 T2, T1 6A/10A regulators for EnergyStar applications

WHERE TO GET MORE INFORMATION?

31

http://mypower.irf.com/Freescale

Freescale Reference Designs

• Power Design

• Design Guides

• Schematics

• Layout

• BOM

• Results

• Start Up & Test Procedures

Reference Designs - Freescale - IR at Avnet

Reference Designs - Freescale - IR at Arrow

Find Reference Design - Freescale - IR T4240

Coming Soon - Reference Designs - T1040 RDB - Freescale and IR Coming Soon - Reference Designs - T2080 RDB HSSI - Freescale and IR

Samples Orderable at Digikey: Click this Link for IR3565BMFS01TRP at Digikey

Click this Link for IR36021MFS01TRP at Digikey

Click this Link for IR36021MFS02TRP at Digikey

APPENDIX

32

Complete Power Solutions on Freescale Reference Designs

33

Reference Designs T-Series PN

Multi-phase

Controllers

VCORE (+DDR)

FET

Regulation, PM and Load Control, Monitors

Integrated Regulators

Point-of-Load Controllers

Bus & I/O Power

T4240-RDB T4240 IR3565B (4+2) / IR3550 (6) IR3897

T4240-PCIe-RDB T4240 IR3565B (4+2) / IR3550 IRFML8244 (3), IRLML6346 (5) (4) IR3898, (2) IR3897

T2080-HSSI T2080 IR36021 (2+1) / IR3550(1) IR3891, (3) IR3895, (2) IR3898,

(1) IR3899

T2080-PCIe-RDB T2080 IR36021 (2+0) / IR3553 IRF9321 (4) IRLML6346 (15) IRLML2502 (1) (8) IR3473, (2) IR3475

T1040_T2081-QDS T1040 / T2081 IR36021 (2+1) / IR3550 IRFH6200 (8), IRLML6346 (6)(2) IR3856, (1) IR3891, (3) IR3895,

(1) IR3898, (1) IR3899

T1040-RDB T1040 / T2081 IR36021 (2+0) / IR3553

IRFH6200 (3), IRFHM4226 (5), IRLML2030 (2),

IRF9321 (1) IRLML6346 (18) IRLML2502 (1)

IRLZ24NSPBF (1)

(8) IR3473, (2) IR3475

T1042-RDB T1042 (1) IR3475IRFH6200 (2), IRFHM4226 (2), IRLML2030 (3),

IRF9321 (1) IRLML6346 (14) IRLML2502 (1) (5) IR3473

• Digital controllers have superior transient and accuracy capability such as the ability to easily nullify

offsets and operate in non-linear modes (refer to appendices 2 & 3). International Rectifier’s digital

controllers are specially configured to meet the stringent accuracy requirements of the T-series

applications. The key tuned parameters (pre-calibrated in IR Production) that are required to meet

3% total accuracy are listed below and must never be altered:

Obtaining 3% accuracy with Digital Controllers

34

Pre-configured Parameter IR3565BFS01 IR36021FS01 IR36021FS02

Loop 1 / Loop 2 Phases

& Boot Voltages

4Φ VCORE & 2Φ DDR3

1.05V / 1.50V

2Φ VCORE & 1Φ DDR3-LV

1.025V / 1.35V

2Φ VCORE (only)

1.025V

Fsw & Cout Bulks (470uF 6mΩ SP)

MLCCs (10uF 0603)

400kHz / 6,850uF 12 BULK + 112 MLCC

500kHz / 2,625uF 4 BULK + 82 MLCC

500kHz / 2,625uF 4 BULK + 82 MLCC

DIFF Remote Sense Enabled (both loops) Enabled (both loops) Enabled

Output Inductor FP1007R3-R15-R

(L=150nH / DCR = 0.29mΩ)

FP1007R3-R22-R (L=215nH / DCR = 0.29mΩ)

FP1007R3-R22-R (L=215nH / DCR = 0.29mΩ)

DIFF Current Sense (RC=L/DCR) Rsen=2.40kΩ / Csen=0.22uF Rsen=3.40kΩ / Csen=0.22uF Rsen=3.40kΩ / Csen=0.22uF

NTC Temp Comp & Current Gain Rcs=3.40kΩ / Rs1_s2=2.87kΩ

Ccs=100pF / NTC = 10kΩ

Rcs=3.40kΩ / Rs1_s2=2.87kΩ

Ccs=100pF / NTC = 10kΩ

Rcs=3.40kΩ / Rs1_s2=2.87kΩ

Ccs=100pF / NTC = 10kΩ

Loadline setting

for Current Sensing Rll=1.00mΩ / BW=192kHz

(AVP disabled)

Rll=1.00mΩ / BW=192kHz (AVP disabled)

Rll=1.00mΩ / BW=192kHz (AVP disabled)

Control Loop Tuning Parameters Proportional (P), Integrative (I),

Differential (D),

& (2) Low-Pass Filters (LPF1_2)

Kp, Ki, Kd =

-20.6dB, -80.8dB, +12.0dB

LPF1,2 = 242.6kHz, 652.1kHz

Kp, Ki, Kd =

-19.2dB, -76.3dB, +16.9dB

LPF1,2 = 242.6kHz, 798.9kHz

Kp, Ki, Kd =

-19.2dB, -76.3dB, +16.9dB

LPF1,2 = 242.6kHz, 798.9kHz

Key Parameters Table

35 35

Parameter IR3565BMFS01TRP IR36021MFS01TRP IR36021MFS02TRP

Application T4 (CORE + DDR) T2/T1(CORE + DDR) T2/T1 (CORE Only)

Loop Configuration 4+2 2+1 2+0

Boot voltage (loop 1 & loop 2) 1.05V / 1.50V 1.025V / 1.35V 1.025V

BASE I2C / PMBus ADDR +

offset

FINAL I2C / PMBus ADDR

Base 0x36 / 0x76 + Offset =2

0x38 (I2C)

0x78 / 0x79 (PMBus loop1&2)

Base 0x36 / 0x76 + Offset =2

0x38 (I2C)

0x78 / 0x79 (PMBus loop1&2)

Base 0x36 / 0x76 + Offset =2

0x38 (I2C)

0x78 / 0x79 (PMBus loop1)

Loop1 & Loop2 Startup timing Both loops start together Both loops start together Only loop 1 starts

Vout Under/Over-voltage

thresholds +/- 350mV +/- 150mV +/- 150mV

Vin Under/Over-voltage

thresholds 10.500V < Vin < 15.938V 10.500V < Vin < 15.938V 10.500V < Vin < 15.938V

Loop 1/Loop 2 overcurrent

threshold 120A / 60A 60A / 30A 60A

Over temperature threshold 120 degC 120 degC 120 degC

Loop 1 & 2 Iout scaling factors 1.0006% / 1.0000% 1.0006% / 1.0006% 1.0006%

Automatic Powersaving Disabled Disabled Disabled

Vout slew rate 10mV/uS 10mV/uS 10mV/uS

Loadline for Current Sensing Rll=1.00mΩ / BW=192kHz Rll=1.00mΩ / BW=192kHz Rll=1.00mΩ / BW=192kHz

PWM frequency 400kHz / 400kHz 500kHz / 500kHz 500kHz

PID compensation & Low Pass

filters

Kp, Ki, Kd =

-20.6dB, -80.8dB, +12.0dB

LPF1,2 = 304.5kHz, 798.9kHz

Kp, Ki, Kd =

-16.1dB, -76.3dB, +22.9dB

LPF1,2 = 242.6kHz, 798.9kHz

Kp, Ki, Kd =

-16.1dB, -76.3dB, +22.9dB

LPF1,2 = 242.6kHz, 798.9kHz

Digital Controllers Used in QorIQ T Series Designs

36

IR3565B 4+2 Controller IR36021 2+1 Controller

What is a SupIRBuck?

Discrete Controller and MOSFETs integrated into 1 package

37

2 Focus Families for Freescale T-Series

SupIRBuck Families

Gen 3 Voltage Mode

IR389x for

Noise sensitive apps

Gen 2 COT

IR384x for

Light-Load Efficiency

38

39

Gen 2 COT SupIRBuck – Block Diagram

Features • VIN : 3V to 27V

• VOUT : 0.5V to 12V

• Programmable switching frequency

• Programmable soft start

• 0.5V +/-1% Precision Reference

• Starts up into a Pre-bias

• Temperature Compensated OCP

• 4 x 5mm QFN Package

Benefits • Compensation Loop not required

• Automatic light load efficiency

Application Schematic

IR3473: 6A Device

IR3475: 10A Device

SupIRBuck™ Online Design Tool

• Type Design Inputs

• Select Components

• Verify Design

• Specify PCB Layout

Download

• Schematics

• Bill Of Materials

• Waveforms

• Bode Diagram

• Efficiency

• Thermal analysis

Available at mypower.irf.com/SupIRBuck