UnderGradThesis_ritambhar

Studies on Short Channel Effects of Nanoscale MOSFETs Using Self Consistent Solution of Poissons and Schrdinger Equation

Project report submitted for the partial fulfillment of the requirement of the degree of

Bachelor of Electronics and Telecommunication Engineering, Jadavpur University

Submitted by

ritambhar burman soumyadeep chakrabarti EXAM ROLL: ETC-158041 EXAM ROLL: ETC-158035 CLASS ROLL: 001110701038 CLASS ROLL: 001110701032rEGISTRATION: 116081 of 11-12 rEGISTRATION: 116075 of 11-12

Under the supervision of

Ms. chandrima mondal

Department of Electronics and Telecommunication Engineering

Jadavpur University, Kolkata

India

2015

JADAVPUR UNIVERSITY KOLKATA - 700032, INDIA

Certificate of Approval

This is to certify that the project report entitled Studies on Short Channel Effects of Nanoscale MOSFETs Using Self Consistent Solution of Poisson and Schrdinger Equation submitted by Ritambhar Burman, Exam Roll no: ETC-158041, Registration no: 116081, and Soumyadeep Chakrabarti, Exam Roll no: ETC-158035, Registration no: 116075, for the partial fulfillment of the degree of Bachelor of Electronics and Telecommunication Engineering from Jadavpur University is based on their assigned project work during the session 2014-2015 under the supervision of Ms. Chandrima Mondal of Electronics and Telecommunication Engineering Department of Jadavpur University, Kolkata, West Bengal.

Signature of SupervisorSignature of Student(s)

Signature of Head of the DepartmentCopyrightSAURAV GUPTA, RITAMBHAR BURMAN, SOUMYADEEP CHAKRABARTI, DAMANLONG PONSHEM, chandrima mondal@ 2015

AcknowledgementsWe would like to thank our research supervisor, Ms. Chandrima Mondal. Without her thorough assistance and dedicated involvement in every step throughout the process, this project would have never seen the light of the day. We would like to thank you very much for your support and understanding over these past four years.We would also like to extend our heart-felt gratitude to our fellow batch-mates, Saurav Gupta and Damonlang Pohsnem, who worked on the solution of Poissons equation in this project. Without their commendable efforts, the project would not have been completed.And last but not the least; we would also like to thank Kansas State University for the custom made Microsoft Office Word 2007 template of Masters Thesis.

Table of ContentsAbstract viiList of Figures viiiList of Tables ixDedication xChapter 1 - INTRODUCTION 1 1.1 Brief History 1 1.2 Challenges 1 1.2.1 Short Channel Effects in FD-SOI MOSFETs 3 1.2.1.1 Threshold voltage roll-off 3 1.2.1.2 Increased Sub-Threshold slope 4 1.2.1.3 Drain Induced Barrier Lowering (DIBL) 4 1.2.1.4 Hot electron effects 5 1.2.1.5 Ballistic Transport 5 1.3 Channel Engineering 6 1.3.1 SOI 6 1.3.1.1 Fully Depleted (FD) and Partially Depleted (PD) MOSFET 7 1.3.2 GeOI 8 1.4 Gate Engineering 9 1.4.1 Gate Work Function Engineering 9 1.4.2 High-k dielectrics 10Chapter 2 - LITERATURE REVIEW 12 2.1 Poisson's Equation 12 2.2 Schrdinger equation 12Chapter 3 - THEORETICAL BACKGROUND 15 3.1 Weak and Strong Inversion 15 3.2 Flat Band Voltage 15 3.3 Threshold Voltage 16Chapter 4 - Model Formulation 17 4.1 Poissons Equation 17 4.1.1 Discretization 18 4.1.2 Generation of a System of Linear Equation 19 4.1.3 Solving Ax=b 20 4.1.4 Boundary Conditions 20 4.2 Schrdinger Equation 23 4.2.1 Discretization 23 4.2.2 Building the kinetic energy operator (double derivative) 25 4.2.3 Solving the Eigen value equation Boundary Condition 26 4.2.4 Boundary Condition 26 4.3 Algorithm 27 Chapter 5 - RESULTS AND DISCUSSION 29 5.1 Parameter Setup 30 5.2 Study of Threshold Voltage v/s channel length 31 5.3 Study of DIBL v/s channel length 32 5.4 Study of Variation of Sub-Threshold Voltage Slope v/s channel length 33 5.5 Surface Potential Plot 34Chapter 6 - CONCLUSION 36References 37 Appendix A - Abbreviations Used 41Appendix B - MATLAB GUI Model 42

AbstractA twodimensional (2-D) numerical model for measurement of the surface potential variation along the channel length/width in fully depleted silicon-on-insulator MOSFET is developed by recursively using self consistent solutions of Poissons equation with Schrdinger equation. The model developed is used to investigate the short-channel effects (SCEs). The model is extended to find the threshold voltage, sub-threshold slope and DIBL in the deep submicron regime of MOSFETs. The model is used to successfully find appropriate metal work function for the desired threshold voltage of FD-SOI MOSFET. A GUI in Matlab is created to facilitate the user interface of the model and make it more user-friendly.

List of FiguresFigure 1.1 Silicon on Insulator MOSFET 7Figure 4.1 Computational molecule for the 5-point star 19Figure 4.2 Algorithm for Self Consistent Poisson-Schrdinger Model 28Figure 5.1 Silicon/Germanium on Insulator MOSFET 29Figure 5.2 Comparisons of Threshold voltage variation with channel length 31Figure 5.3 Comparison of DIBL variation with channel length 32Figure 5.4 Comparison of Sub-threshold slope variation along with channel length 33Figure 5.5 Surface Potential Plot of SOI MOSFET 34Figure B.1 MATLAB GUI 42

List of TablesTable 5.1 Si NMOS: Device parameters used in the verification of FD-SOI MOSFET 30Table 5.2 Ge NMOS: Device parameters used in the verification of FD-SOI MOSFET 30

DedicationWe dedicate this thesis to Jadavpur University, which played a pivotal role in helping us achieve what we are today.

iv1. INTRODUCTION1.1Brief HistoryMetal-oxide-semiconductor field-effect transistor (MOSFET or MOS transistor) gained commercial significance two decades after the 1948 announcement of the invention of the transistor by Bell Laboratories. The underlying concept of the MOSFET-modulation of conductivity in a semiconductor triode structure by a transverse electric field-first appeared in a 1928 patent application, which was later confirmed experimentally in 1948. However surface problems were there in early transistors. Although these were solved at Bell Laboratories in 1958, Bell remained committed to earlier transistor technology. Development of the `other transistor' was first pursued elsewhere. It was finally the needs of computers and the opportunities created by integrated circuits that made the silicon MOSFET the basic element of late 20th-century digital electronics. Over the years, the dimensions of MOSFETs have continued to shrink in order to realize higher-speed and higher-packing density MOS integrated circuits. The number of transistors per square inch on integrated circuits had doubled every year since their invention. Moores law predicts that this trend will continue into the foreseeable future. 1.2ChallengesThe shortcoming of extremely large integration is that, the power consumption of modern VLSI circuits has become rather significant. The main principal concern of scientists is reducing this power. Choosing a lower power supply voltage is an effective method [1]. Still, it leads to the degradation of MOSFET current driving capability. Consequently, scaling of MOS dimensions is important in order to improve the drivability, and to achieve higher-performance and higher-functional VLSIs. Power supply scaling soothes this problem particularly well. Since power supply reduction below three times threshold voltage () will degrade circuit speed significantly, scaling of the power supply should be accompanied by threshold voltage reduction [1-2]. Moreover due to reduction in the channel length, the short channel effects and leakage current becomes an important issue that degrades the device performance in terms of leakage current and short channel effects [3].The rapid progress in semiconductor technology is progressively pushing the dimensions of electronic devices towards the nano-meter scale, where electronic properties will be increasingly dominated by quantum effects. This goes on until at some point of time, these effects become essential for the device to operate. At submicron level, the silicon band splits into discrete sub-bands, with most of the inversion layer electrons residing in the lowest sub-band, which can be described by the Schrdingers wave equation [4-5]. An accurate modelling of small geometry MOSFETs requires the numerical solution of two- or three-dimensional Poisson's equation and Schrdinger Equation. Conventional MOSFET models have been successfully used for the long-channel devices. However, the scaling down of MOSFETs to a deep sub micrometer regime leads to deviations from assumptions in the conventional models. The project aims to develop a MOSFET model for use in circuit simulators.Fully Depleted (FD) Silicon on Insulator (SOI) metal oxide field effect transistor (MOSFET) is the leading contender for sub 100 nm regime. This report presents the effects of reducing channel length from 100 nm to 10 nm in steps of 10 nm. This report further shows the effects of assigning channel thicknesses of 25 nm, 10 nm and 5 nm.As the channel length is made to go on decreasing, the following short channel effects (SCEs) come into picture:1) Threshold voltage roll-off2) Increased Sub threshold slope3) Drain Induced Barrier lowering4) Hot electron effects at increasing drain voltage5) Ballistic Transport6) Charge sharing by the gate and drain electric fields in the channel depletion layerSCE degrades the controllability of the gate voltage to drain current, which leads to the degradation of the sub threshold slope and so an increase in drain off-current. Thinning gate oxide and using shallow source/drain junctions are known to be effective ways of preventing SCEs. The short-channel effects are prominent when the gate length is reduced to the same order as the channel depth. When the channel length is shrunk, the absolute value of threshold voltage becomes smaller due to the reduced controllability of the gate over the channel depletion region by the increased charge sharing from source/drain.1.2.1Short Channel Effects in MOSFETA MOSFET device is considered to be short, when the channel length is of the same order of magnitude as the depletion-layer width () of the source and drain junction. As the channel length L is reduced to increase both the speed of operation and the number of components per chip, the so-called short-channel effects, arise [6].1.2.1.1 Threshold Voltage roll-offAs the channel length is reduced, the threshold voltage of the MOS device decreases. This is known as threshold voltage roll-off. The main reason for this threshold voltage roll-off is the presence of two-dimensional field pattern in short channel devices. These two dimensional field patterns originate from the proximity of the source-drain region.

1.2.1.2 Increased Sub-threshold SlopeSub-threshold Slope indicates how effectively the flow of drain current of a device can be stopped when is decreased below. When curve of a device is steeper sub-threshold slope will improve.Sub-threshold slope is given by equation 1.1 [6]: (1.1)Where .A device, characterized by steep sub-threshold slope, exhibits a faster transition between off (low current) and on (high current) states. It is observed that high metal gate work function leads to a better sub-threshold slope when the MOSFETs are scaled down [7].1.2.1.3 Drain Induced Barrier Lowering (DIBL)In the weak inversion regime, there is a potential barrier between the source and the channel region. The height of this barrier is a result of the balance between drift and diffusion current between these two regions. The barrier height for channel carriers should ideally be controlled by the gate voltage to maximize trans-conductance. The DIBL effect occurs when the barrier height for channel carriers at the edge of the source, reduces due to the influence of drain electric field, upon the application of a high drain voltage. This increases the number of carriers injected into the channel from the source leading to an increased drain off-current. Thus, the drain current is controlled not only by the gate voltage, but also by the drain voltage.For device modelling purposes, this parasitic effect can be accounted for by a threshold voltage reduction depending on the drain voltage. In addition to the surface DIBL, there are two unique features determining SCEs in thin-film SOI devices: 1) positive bias effect to the body due to the accumulation of holes generated by impact ionization near the drain and 2) the DIBL effect on the barrier height for holes at the edge of the source near the bottom of thin film.A measure of DIBL is given by equation 1.2.DIBL = Where is the threshold voltage when drain to souce voltage is and is the threshold voltage when drain to source voltage is .1.2.1.4 Hot Electron EffectsReducing the channel length, while maintaining the power supply, results in increased electric field strengths in the channel causing acceleration and heating of the charge carriers. Hot electrons cause tunnelling of charge carriers across the oxide which is undesired. Thin film SOI MOSFETs has lesser hot electron effects as compared to bulk MOSFETs [8].1.2.1.5 Ballistic TransportWhen MOSFET channel length becomes shorter and comparable to a carrier scattering length (), the carriers encounter less scattering events. On such a channel length scale, an interesting phenomenon, termed 'ballistic transport', occurs, which implies that the carriers can travel from source to drain like a shooting bullet. This basically indicates that gate has now lesser control over channel conductance. The characteristics of the quasi-ballistic transport and drain current in ultra small MOSFETs, taking into account the back-scattering and transmission coefficients, was studied by Kim et. al [9], which shows that it varies dramatically with temperature, doping concentration in the source, oxide thickness and drain and gate voltages.1.3Channel Engineering1.3.1 SOISilicon-On-Insulator (SOI) is a chip making process by replacing the bulk silicon wafers with wafers which have three layers; a thin surface layer of silicon (from a few nano-meters to several microns thick) where the transistors are formed, an underlying layer of insulating material and a support or "handle" silicon wafer. The insulating layer is made of silicon dioxide and referred to as the "buried oxide" or "BOX". It is usually a few hundred nano-meters thick. When transistors are built within the thin top silicon layer, they switch signals faster, run at lower voltages and are much less vulnerable to signal noise from background cosmic ray particles. Since each transistor on an SOI wafer is isolated from its neighbour by a complete layer of silicon dioxide, they are immune to "latch-up" problems, and can be spaced closer together than transistors built on bulk silicon wafers [10]. Building circuits on SOI allows for more compact chip designs, resulting in smaller IC devices (with higher production yield) and more chips per wafer (increasing fab productivity). In addition, for scaling devices into deep-submicron regime, SOI devices are more suitable with their steeper sub-threshold slope which facilitates scaling of the threshold voltage for low-voltage low-power applications.The full isolation in SOI device provides many advantages. The drain-to substrate capacitance can be neglected due to insulator (SiO2) that has dielectric constant lower than Silicon [11].

Source(VS=0) Front Gate(VFG)Drain (VDD)

P substrateBuried Oxide ~ 100nm thickFront Gate Oxide ~ 1- 6nm thickP channel~ 5nm-25nm thickn+n+

Vsub = 0 Figure 1.1: Silicon on Insulator MOSFET1.3.1.1 Fully Depleted (FD) and Partially Depleted (PD) MOSFETDepending on the thickness of the silicon layer, MOSFETs will operate in fully depleted (FD) or partially depleted (PD) regimes. When the channel depletion region extends through the entire thickness of the silicon layer, the transistor operates in a FD mode given by equation 1.3.1. Otherwise the transistor operates in a PD mode given by equation 1.3.2. (1.3.1) (1.3.2)Depletion layer thickness or space charge width is given by equation 1.4. (1.4)The main advantage of the PD SOI device is somewhat higher speed and lower leakage due to reduced source and drain area junction capacitances. However, from a static leakage and electrostatic scalability perspective, the PD SOI transistor looks the same as a bulk FET. The FD devices have several advantages compared to the PD devices. FD devices are free from kink effect [12], have enhanced sub-threshold swing [13], and highest gains in circuit speed, reduced power requirements and highest level of soft-error immunity [14]. Moreover the total masks needed in the front-end process for FD SOI devices are less than half of that required for bulk CMOS devices [15].Because of BOX layer the fully depleted silicon-on insulator (FD-SOI) has the advantages of lower parasitic junction capacitance and better sub-threshold swing, reduced short channel effects [16-17].1.3.2GeOIInternational Technology Roadmap for Semiconductors (ITRS) [3] states that thin EOTs 10) are mainly transition metal (TM) oxides. TM oxides have poor thermal stability and poor interface quality with the silicon substrate. In addition, the interface and oxide trap densities are one to three orders of magnitude larger than those in silicon oxide.Surface treatment prior to high- deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. There is almost 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO2/Si system [28]. Now-a-days germanium MOS structures are using ZrO2 [29], HfO2 [30]. In these recent works, surface treatments have been demonstrated to be essential to fabricate a germanium MOS device with CVD high- dielectrics.

LITERATURE REVIEW2.1Poissons EquationFD-SOI MOSFETs have a great potential to be the next-generation devices due to their superior short-channel immunity and ideal sub-threshold characteristics. There have been many reports on their modelling of devices [3133]. The basic assumption of charge sharing models is the constant surface potential. However it becomes invalid for sub-micrometer channel lengths. The solution of 2-D Poissons equation has been obtained using various approaches. Pseudo-2D solutions of Poissons equation [31, 34] and a quasi-2-D technique [35-36] have been reported in literature.Power series approach has been used to solve 2-D Poissons equation [37]. However, it requires that the higher order terms are neglected and, hence, its solution is not as accurate as the other approaches. Analytical solution of 2-D Poissons equation by means of Greens function [38] is another method to solve 2-D Poissons equation by separation of variables. However, the boundary conditions used in this case are applicable only for bulk MOSFETs. The proposed model in this project solves the 2-D Poissons equation by using separation of variable method.2.2Schrdinger EquationIn the past, models such as drift-diffusion formed the basis for simulating semiconductor devices. But such techniques are not adequate to model the new breed of quantum devices, where the quantum effects of a single electron can play a significant part in a device's operation. However, a concise quantum mechanical simulation of an entire semiconductor device is not feasible from the numerical point of view. So it has been stated that to model more complicated quantum devices, it is possible to use the fact that in many semiconductor devices quantum elects take place in a localized region (micro-structure), for example, within the active zone of a quantum well laser, whereas the rest of the device (macro-structure) can be described by classical models [39]. Therefore, it would be possible to follow a strategy where there can be a coupling of quantum mechanical and macroscopic models (similar to multi-scale modeling in other areas of engineering). An important aspect of quantum phenomena is the conservation of probability. For this reason, the promising time evolution numerical technique seems to be the Crank-Nicolson method, which is not only unconditionally stable but the time-stepping equations associated with it are unitary and thus inherently conserve probability. Then for the numerical solution of the Schrdinger equation one can simply use a finite-difference method for space discretization and then apply the Crank-Nicolson method for time evolution. In previous work, [40], more sophisticated techniques such as the finite element method have been used for spatial discretization. By using finite elements combined with high-order spatial discretization it is possible to model the wave function of a particle more accurately. Combining this system with the Crank-Nicolson time evolution method one can then model the time evolution of a wave function efficiently and accurately, rather than simply using a simple finite difference method [41]. One step beyond this is the use of finite elements in space and time which is known as the space-time finite element method [42].Another established method is the technique of adaptive mesh refinement (AMR) [43]. Here the motivation is to solve a differential equation numerically. The first step is a representative coarse grid. For a well behaved problem this will be sufficient, but in some cases there are regions, where the solution is difficult to estimate. It is them possible to simply refine the grid spacing, but this is often computationally much more costly than necessary. Instead the AMR method is followed, and the grid spacing is refined locally based on an identification of the regions requiring more resolution. This will in the end lead to fewer evaluations. Only the 1D case is considered, which is implemented in this work. The basic idea is to calculate the variation of the function at the endpoints of a given interval of the grid, and subdivide this interval further only if the variation of the function at one end point with respect to the other exceeds a fraction of the maximal function variation on the original coarse grid . In the case, where subdivision is found necesary the interval [a, b] is then initially subdivided into three equal intervals, and each of these are then consequently subjected to the same procedure involving possible subdivision as just described.As a conclusive remark concerning the AMR , for the physical problems treated in this work it is actually just as good and much faster to use a uniform mesh. For more complicated problems, it is therefore recommendable to use a uniform mesh combined with further improvements of the efficiency.

THEORETICAL BACKGROUND3.1Weak and Strong Inversion In weak inversion region, the small inversion charge, appearing at the front silicon film surface as in the case of the bulk MOSFET, can be neglected. The MOSFET operates in weak inversion region, when equation 3.1.1 is satisfied. The MOSFET operates in strong inversion region, when equation 3.1.2 is satisfied. (3.1.1) (3.1.2)3.2 Flat Band VoltageThe flat band voltage is defined as the applied gate voltage, which results in no band-bending in the semiconductor. So, zero net space charge is present in the channel region.In the gate oxide layer, the net fixed charge density is usually positive. The positive charge can be identified with broken or dangling covalent bonds near the oxide semiconductor interface. (3.4)where is the flat band voltage. is the oxide capacitance per unit area. is the charge present in the substrate (including accumulation charge) per unit area and is the work function difference between the gate and the channel and is given by equation 3.5. (3.5)where is the metal work function, is electron affinity of semiconductor, is the band gap energy, and e is the electronic charge. is the Fermi potential given by equation 3.6. (3.6)3.3Threshold VoltageThe analysis done in this report includes that for n-channel Metal Oxide Semiconductor (NMOS), with its extension to p-channel Metal Oxide Semiconductor (PMOS) device being straightforward. The threshold voltage of a n-channel MOSFET is classically given by equation 3.2. (3.2) is the flatband voltage (discussed below), is the Fermi potential for p-type substrate, is the oxide capacitance per unit area and is the depletion charge per unit area.The threshold voltage is defined to be the value of the gate voltage required to achieve the threshold inversion point given by equation 3.3.1 for PMOS and equation 3.3.2 for NMOS. 3.3.1 3.3.2 is the Fermi potential for p-type substrate and is the Fermi potential for n-type substrate.There are various ways of determining threshold voltages analytically; one such method is to find surface potential minima at the front gate for FD thin-film SOI [44-46]. Several other methods using graph are discussed and compared by Conde et. al [47]. Conventional numerical analysis techniques have been used to plot surface potential graph in this paper.

Model FormulationThe Poisson equation is a very powerful tool for modelling the behaviour of electrostatic systems, but unfortunately may only be solved analytically for 2D or 3D problems. Consequently, numerical simulation must be utilized in order to model the behaviour of complex geometries with practical value. Although there are several competing algorithms for achieving this goal, one of the simplest and more straightforward of these algorithms is the finite-difference method (FDM). At its core, FDM is nothing more than a direct conversion of a differential equation from continuous functions and operators into their discretely-sampled counterparts. This converts the entire problem into a system of linear equations that may be readily solved via matrix inversion. The accuracy of such a method is therefore directly tied to the ability of a finite grid to approximate a continuous system, and errors may be arbitrarily reduced by simply increasing the number of samples. The process of solving Poisson and Schrdingers equation can be aided by the use of FDM process and can be described in three main steps: mesh generation, discretization, and the generation of a system of linear equations. There are various ways of performing each step, but for the sake of this project, only one method of solving a general form of Poissons equation in a 2 dimensional space and a time-independent one-dimensional Schrdingers equation has been described underneath. 4.1Poissons EquationThe two dimensional Poissons equation takes the form as described in equation 4.1.1, which can be expanded to equation 4.1.2. ... 4.1.1 ... 4.1.2Where ... 4.2 is the ionized donor impurity concentration, is the ionized acceptor impurity concentration, is the hole charge carrier density and is the electron charge carrier density. is the volume charge density, is the permittivity of the semiconductor and is the surface potential. In addition, FDM requires the Poisson equation solution to adhere to a set of boundary conditions, given by equation 4.10.1, 4.10.2 and 4.11.A 2-dimensional grid with a step size h is created, where each point on the grid () is represented by and for where is the grid dimension. Using this method, the solution of is approximated as .4.1.1Discretization The finite difference method is used for the discretization step [48]. This is done by looking at the neighbours separately in the x and y direction, according to equations 4.3.1 and 4.3.2, which are then combined to form equation 4.3.3 ... 4.3.1 ... 4.3.2 ... 4.3.34.1.2Generation of a System of Linear Equations Equation 4.3.3 is substituted in Poissons equation 4.1.2 to generate a set of linear equations, given by equation 4.4.1, and ultimately equation 4.4.2, that can be solved to determine . ... 4.4.1 ... 4.4.2The equation 4.4.2 states that, every voltage sample is dependent only on and the voltages at the four nearest neighbours. A graphical depiction of this is called a computational molecule, and is shown in Fig 1. Because of its unique geometry, this five-point stencil is often referred to as the five point star.

Figure. 4.1 Computational molecule for the 5-point star. along the boundary is already known, since it is given by the boundary conditions given by equation 4.10.1 and 4.10.2.Because each voltage sample is linearly dependent on its four nearest neighbors, the solution over all () may be represented as a simple matrix-vector equation. This is readily achieved by defining the vector x that contains all of the voltage samples within the domain. For example, one simple method might be scanning row-wise along the voltage samples according to the convention given by equation 4.5. ... 4.5The next step is to express the linear relationship between voltage samples into a matrix A. This effectively converts the entire problem into a matrix-vector equation with the form given by equation 4.6.Ax = b ... 4.6where b contains all the information about any charge densities and boundary conditions. 4.1.3Solving Ax=bThe numerical solution to the system is finally found by simply inverting the matrix A, to arrive at the solution of x, as given by equation 4.7.

Using simple MATLAB command we can solve this equation given by equation 4.8.x = A\b ... 4.84.1.4Boundary ConditionsBecause a computer can only store a finite number of grid points, it is always necessary to truncate a simulation domain along some fixed boundary. Since the five-point star is not applicable at the boundary samples, it is necessary to specify boundary conditions in order to arrive at a unique solution to the problem. The two most basic forms of boundary condition are called the Dirichlet boundary and the Neumann boundary [48].The simplest boundary condition is the Dirichlet boundary, which may be stated as equation 4.9. = ... 4.9The function is a known set of values that defines along Dirichlet boundary. Thus, the Dirichlet boundary is nothing more than a forced solution to the potential function, given by equation 4.10.1 and equation 4.10.2, at specific points. ... 4.10.1

is the source boundary and is the drain boundary.In contrast, the Neumann boundary condition exists when the derivative of the potential function is known. Generally speaking, the derivative is defined with respect to the outward unit normal at the boundary, which is written as equation 4.11.

where n is the outward-pointing unit normal vector and specifies the set of known derivatives. is the Neumann boundary.Unlike the Dirichlet condition, the Neumann condition does not offer a direct solution to the voltage potentials on a discrete, sampled grid. Rather, the boundary point must be expressed in terms of the surrounding points by applying a new stencil. The simplest method for expressing this is by imagining a central-difference approximation between the boundary sample and the first inner sample, given by equation 4.12.

In our problem, the Neumann boundary condition is applied at the gate oxide and channel junction and is given by equation 4.13.

Equation 4.13 can be reduced as following to achieve equation 4.14.

where , . is the gate voltage, is the flat-band voltage, is the relative permittivity of the semiconductor used, is the relative permittivity of the gate oxide used and is the oxide thickness.Now at the gate boundary, there is the condition, as stated by equation 4.4.2.Discretizing equation 4.14, we achieve equation 4.15.

Substitution of equation 4.15 into equation 4.4.2 results in equation 4.16.

So equation 4.16 is the equation at the boundary.4.2Schrdinger EquationOne of the fundamental concepts of quantum physics is that of wave-particle duality: that is an object can show the natures of both a particle and a wave [49]. Einstein showed that a photon has a momentum equivalent to a particle moving with the same energy, even though it is considered as a wave packet. The dynamical behaviour of these quantum waves/particles can be described in a non-relativistic manner through the use of wave mechanics with its associated quantum states and quantum numbers. Erwin Schrdinger in 1926 published a partial differential equation to quantify the time-varying nature of a quantum state.The time-independent one-dimensional Schrdinger equation [50] is stated in equation 4.17.

where is the sum of the kinetic and potential energy parts of the particle, is the wave function of that particle, refers to h/2, where h is Plancks constant, refers to the position of the particle and is the potential energy of the system. For simple potential functions, analytic solutions are available. But for most real world applications, and particularly for SOI MOSFET analysis, numerical techniques are required.4.2.1DiscretizationTo solve numerically, a finite set of equations is required, which we can solve. For this, a number of discrete lattice points are needed. For each such lattice point, equation 4.17 is satisfied by a corresponding -value. Thus the differential equation is converted into a matrix equation, given by equation 4.18.

is an -dimension column vector displaying the value of at different points. And equation 4.17, taking the help of equation 4.18, reduces to equation 4.19.

where is a square matrix known as the Hamiltonian operator [51]. The above Eigen value equation is solved to find Eigen values and Eigen vectors. For large value of , MATLAB has been used to solve for this eigen-value equation. But first, the H matrix needs to be constructed.In differential form,

where is the Hamiltonian. So and parts in matrix form are solved independently and are summed to get the Hamiltonian matrix H.First, the potential matrix is built. Since is the potential function, it is simply multiplied with the wave function at every lattice point. Thus, it will be a diagonal matrix, given by equation 4.21.

4.2.2Building the kinetic energy operator (double derivative)The double derivative needs to be expressed in discrete form with the help of difference equations.We know,

where a is the lattice constant or minimum distance between two lattice points.Now the double derivative of at gives,

Simplifying using the expressions for first order derivatives,

Thus the matrix equation would appear as: 4.2.3Solving the Eigen value equationThe eigs operator of MATLAB has been used to solve the Eigen value equation 4.25.

The eigenvectors appear as N columns in matrix X and the eigen-values are the diagonal elements of the matrix Y. Num is the number of solutions calculated and SM specifies that the smallest Num solutions are taken.

The multiple solutions for wave function values at each point is multiplied with its corresponding conjugate and added up. This sum gives the probability density of finding the electron at that point, say .

These probability densities of different points are stored in a column matrix and sent to the Poisson Solver as input. The Poisson Solver is a module which solves the Poissons Equation taking as input and gives the potential matrix as output. This improved is again used to solve the Schrdinger equation using the above algorithm, resulting in a more accurate matrix. Thus the error between the real probability density and the analytically derived value of it is minimised using the above procedure. 4.2.4Boundary ConditionThe equation 4.29 encounters problems at the boundary regions and .

For example for ,

In the case of SCE study in MOSFET, Schrdinger equation is solved in a direction perpendicular to the channel, which is from one gate terminal to the other. In such cases, the electron probability is assumed to be zero at the extreme ends, as the gate is an insulator.Thus, and are the boundary conditions used to solve the above eigen value equation.4.3AlgorithmTo arrive at the self-consistent potential of a given quantum hetero-structure system, Schrdingers equation and Poissons equation come into assistance. Poisson's equation can be solved to calculate the electrostatic potential at each point of the semiconductor. Poisson's equation relates the potential to the charge density distribution in the semiconductor hetero-structure. The solution of Schrdinger's equation provides the Eigen-energies and the corresponding wave functions, which are used in the calculation of the charge density distribution. The charge density is calculated by running the sum over the square of the wave function solutions at each spatial distance of the semiconductor, and over all the populated bound states, and multiplying this quantity by the number of carriers in each bound state (sub-band). The flow chart below shows the algorithm used to arrive at self consistent solution.

Start

Solve Poissons equation with background doping density for V(x,y)

Solve Schrodinger equation using V(x,y) for Eigen energies and wave function

Calculate charge density (x,y)

Solve Poissons equation with charge density obtained for V(x,y)

is ? NO

YES

Self consistent solution found

Figure 4.2: Algorithm for Self Consistent Poisson-Schrdinger Model

RESULTS AND DISCUSSIONThe semiconductors used for the analysis of short channel effects of nano-channel MOSFETS are Silicon and Germanium. They are the most natural choice of semiconductors that are simple, and yet they are a representative of other similar semiconductors. Though we have used n-channel MOSFET but the concept can be easily extended to p-channel MOSFET as well. The device parameters are listed in table 5.1 for Si-NMOS and table 5.2 for Ge-NMOS. The parameters chosen in Table 5.1 and 5.2 are such that the threshold voltage of the device is 0.34V at 100 nm channel length and 25 nm channel thickness.The project is further assisted by MATLAB, along with a Graphical User Interface to make it more user-friendly. Further details about the MATLAB GUI used in the project is given in Appendix B, figure B.2 by taking Si as the semiconductor.

Source(VS=0) Front Gate(VFG)Drain (VDD=1V)

P substrateBuried Oxide (SiO2)Front Gate Oxide(SiO2/HfO2) P channel(Si/Ge)n+(Si/Ge)n+(Si/Ge)

VSUB = 0 Figure 5.1: Silicon/Germanium on Insulator MOSFET

5.1 Parameter SetupTable 5.1: Si NMOS: Device parameters used in the verification of FD-SOI MOSFETParameterValue

Front Oxide thickness 1 nm

Back Oxide thickness 100 nm

P-channel doping concentration

Source and Drain doping Concentration

Residual Oxide charge

Metal work function 4.545 eV

Electron Affinity of Si 4.05 eV

Band gap Energy of Si 1.12 eV for 10 nm or 25 nm channel thickness1.2 eV for 5 nm channel thickness

Table 5.2: Ge -NMOS: Device parameters used in the result verification of FD-SOI MOSFETParameterValue

Front Oxide thickness 6 nm

Back Oxide thickness 100 nm

Front Oxide relative permittivity (HfO2/ZrO2)24

Back Oxide relative permittivity (SiO2)3.9

P-channel doping concentration

Source and Drain doping Concentration

Residual Oxide charge

Front Gate Metal work function 4.64 eV

Back Gate Metal work function 9.12 eV

Electron Affinity of Ge 4.13 eV

Band gap Energy of Si 0.66 eV for 25 nm channel thickness0.67 eV for 10 nm channel thickness0.76 eV for 5 nm channel thickness

5.2 Study of Threshold Voltage v/s Channel LengthFigure 5.2 (a)Figure 5.2 (b)

Figure 5.2 (c)Figure 5.2 (d)

Figure 5.2: Comparisons of threshold voltage variation with channel length for three different channel thickness (a) Si-NMOS with = 50mV (b) Si-NMOS with = 1V (c) Ge-NMOS with = 50 mV (d) Ge-NMOS with = 1VIt is evident from figure 5.1 that, as the channel length is decreased; the threshold voltage also decreases, whereas the threshold voltage increases with decrease in channel thickness. Also for thin channel, there is less variation in with channel length.With increase in drain to source voltage the threshold voltage takes a further dip. This phenomenon is called Drain Induced Barrier Lowering (DIBL), as explained in chapter 1.High S/D parasitic resistance, inversion charge loss due to trapping, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation [52]. If we compare the results in figure 5 we see that in Si the voltage roll-off essentially starts below 50nm whereas for Ge it starts below 70nm for channel thickness of 25 nm. However when the channel thickness is reduced to 10nm and further to 5nm, voltage roll-off starts below 30nm and 20nm respectively in both Si and Ge.

5.3 Study of Variation of DIBL v/s channel lengthFigure 5.3 (a)

Figure 5.3 (b)

Figure 5.3: Comparison of DIBL variation with channel length for three different values of channel thickness (a) Si-NMOS (b) Ge-NMOSDIBL increases with decrease in channel length. Also with decrease in channel thickness DIBL is reduced.5.4 Study of Variation of Sub-Threshold Voltage Slope v/s channel lengthFigure 5.4 (a)Figure 5.4 (b)

Figure 5.4 (c)Figure 5.4 (d)

Figure 5.4: Comparison of Sub-threshold slope variation along with channel length for three different channel thickness (a) Si-NMOS with = 50mV (b) Si-NMOS with = 1V (c) Ge-NMOS with = 50mV (d) Ge-NMOS with = 1V.It can be observed that when channel length decreases, S increases and moves away from the ideal value 60 mV/decade. S shifts to slightly higher values due to quantum effects. As is evident from Figure 5.3 sub-threshold slope does not depend much on drain to source voltage, therefore is almost invariant with change in.5.5 Surface Potential PlotFigure 5.5(a)

Figure 5.5 (b)

Fig. 5.5: (a) Surface potential plot in non-inversion layer (b) Surface potential plot in inversion layer in SOI MOSFETWhen the gate voltage VFG is less than threshold voltage the MOSFET is in depletion region, the surface potential plot in this region is given in figure 5.5(a) when it becomes greater than threshold voltage VTH , the MOSFET enters the inversion regime, the potential plot is given in figure 5.5(b)

CONCLUSIONContinuous down scaling of MOSFET device is required to increase the device speed and packaging density, but it degrades the device performance in terms of short channel effect and leakage current . For continuous scaling down, there is need of device structure that provides better performance in deep submicron regime. The GUI based model developed can plot surface potential and concentration in two-dimension. Using this model, threshold voltage and SCEs like DIBL and Sub-threshold is found. The effect of various MOS parameters like body doping density, applied substrate bias, the thickness of thin-film, gate oxide and buried oxide on the threshold voltage can be visualized with the help of this model.Future scope of this work can be to further improve the model to calculate drain current and leakage current. We can further see how the SCEs are changing with gate oxide thickness, channel doping and source/drain doping using our GUI Model. The model developed can be also extended to Double Metal Gate (DMG) SOI MOSFET by changing the boundary conditions. Similar kind of GUI based model can be developed for other type of MOSFETs like Junction-less MOSFET or Fin-FET etc.

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[52]D. Kuzum et. al, Experimental Demonstration of High Mobility Ge NMOS, International Electron Devices Meeting, pp. 1-4, Dec. 2009.Abbreviations useda) AMR Adaptive Mesh Refinementb) BOX Buried Oxide c) CVD Chemical Vapor Depositiond) DIBL Drain Induced Barrier Loweringe) DMG Double Metal Gatef) EOT Equivalent oxide thicknessg) FDM Finite Difference Methodh) FD-SOI Fully Depleted Silicon on Insulatori) Ge Germaniumj) GeOI Germanium on Insulatork) GUI Graphical User Interfacel) IC Integrated Circuitsm) ITRS International Technology Roadmap for Semiconductorsn) MOSFET Metal oxide Semiconductor Field Effect Transistoro) NMOS n channel MOSp) PD-SOI Partially Depleted Silicon on Insulatorq) PMOS p channel MOSr) TM Transition metals) SCE Short Channel Effectt) Si Silicon u) SOI Silicon on Insulator / Semiconductor on Insulatorv) VLSI Very Large Scale Integrated Circuit

MATLAB GUI MODEL

Figure B.1 (a)

Figure B.1 (b)

Figure B.1 (c)

Figure B.1 (d)

Figure B.1: (a) The Matlab GUI for the project, (b) Semiconductor Silicon (or similarly Germanium) is loaded with provision to change the device parameters of the NMOS, and then evaluated to get the self-consistent Poisson-Schrdinger solution. (c) Plot Potential push-button plots the potential at each point of the 2-dimensional Si-NMOS surface. (d) Plot Concentration push-button plots the concentration at each point of the 2-dimensional Si-NMOS surface.1