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Formal Specification of Software UML State Machines Bernhard Beckert U NIVERSITÄT KOBLENZ -L ANDAU B. Beckert: Formal Formal Specification of Software – p.1
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UML State Machines

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Page 1: UML State Machines

Formal Specification of Software

UML State Machines

Bernhard Beckert

UNIVERSITÄT KOBLENZ-LANDAU

B. Beckert: Formal Formal Specification of Software – p.1

Page 2: UML State Machines

UML State Machines

Important type of UML diagrams

For modelling behaviour

Lifecycle of objects

Behaviour of operations

History

Invented by D. Harel (State Charts)

Made popular by J. Rumbaugh (OMT)

B. Beckert: Formal Formal Specification of Software – p.2

Page 3: UML State Machines

Notions Related to State Machines

State

Transition

Event

Action, Activity

Guards

Sending messages

Nesting

Concurrency

History states

B. Beckert: Formal Formal Specification of Software – p.3

Page 4: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

B. Beckert: Formal Formal Specification of Software – p.4

Page 5: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

State

StateMachine

Initial State

Transition

Event

bm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 6: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

State

StateMachine

Initial State

Transition

Event

bm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 7: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

Final Statebm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 8: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

Final Statebm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 9: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

White Win

Black Win

bm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 10: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

White Win

Black Win

bm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 11: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

White Win

Black Win

bm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 12: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

White Win

Black Win

bm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 13: UML State Machines

Example: Chess

A chess game consists

of alternate moves of

Black and White. White

moves first.

The game can end both

when it is White’s and

when it is Black’s turn.

The moving player can

end the game: winning

(checkmate),

loosing (resign),

or with a draw.

Behaviour of ChessGame

White’s Move

Black’s Move

White Win

Black Win

Drawbm(p:Piece)

B. Beckert: Formal Formal Specification of Software – p.4

Page 14: UML State Machines

State Machines

State Machine

Labelled, finite graph (cycles possible)

States

Nodes of the graph

Labelled with: name, do-, entry-, exit-action, . . .

Initial and final states have special shapes

Transitions

Edges of the graph

Labelled with: event, guard, action, . . .

B. Beckert: Formal Formal Specification of Software – p.5

Page 15: UML State Machines

State Machines

State Machine

Labelled, finite graph (cycles possible)

States

Nodes of the graph

Labelled with: name, do-, entry-, exit-action, . . .

Initial and final states have special shapes

Transitions

Edges of the graph

Labelled with: event, guard, action, . . .

B. Beckert: Formal Formal Specification of Software – p.5

Page 16: UML State Machines

State Machines

State Machine

Labelled, finite graph (cycles possible)

States

Nodes of the graph

Labelled with: name, do-, entry-, exit-action, . . .

Initial and final states have special shapes

Transitions

Edges of the graph

Labelled with: event, guard, action, . . .

B. Beckert: Formal Formal Specification of Software – p.5

Page 17: UML State Machines

When to Use State Machines

Use State Machines . . .

at an early stage of software development

when behaviour of an object (lifecycle) or operationis not well understood yet

Do NOT use State Machines . . .

when several objects are involved(interaction diagrams are better)

B. Beckert: Formal Formal Specification of Software – p.6

Page 18: UML State Machines

When to Use State Machines

Use State Machines . . .

at an early stage of software development

when behaviour of an object (lifecycle) or operationis not well understood yet

Do NOT use State Machines . . .

when several objects are involved(interaction diagrams are better)

B. Beckert: Formal Formal Specification of Software – p.6

Page 19: UML State Machines

State

Abstract view

the same response to the same stimuli

the same active behaviour

Implementation view

certain attributes have certain values

B. Beckert: Formal Formal Specification of Software – p.7

Page 20: UML State Machines

State

Abstract view

the same response to the same stimuli

the same active behaviour

Implementation view

certain attributes have certain values

B. Beckert: Formal Formal Specification of Software – p.7

Page 21: UML State Machines

Event

Properties

observable in the environment of the current object

takes place at certain point in time (has no duration)

has possibly parameters

Role in diagram

triggers a transition

is “consumed” when transition is executed

can be saved under certain circumstances

B. Beckert: Formal Formal Specification of Software – p.8

Page 22: UML State Machines

Event

Properties

observable in the environment of the current object

takes place at certain point in time (has no duration)

has possibly parameters

Role in diagram

triggers a transition

is “consumed” when transition is executed

can be saved under certain circumstances

B. Beckert: Formal Formal Specification of Software – p.8

Page 23: UML State Machines

Types of Events

Signal event

An object that is dispatched (thrown) and received (caught)

Call event

Represents the dispatch of an operation

Time event

Represents the passage of a certain amount of time

Change event

Represents the fact that a Boolean expression is changed to true

The expression is checked continuously (polling)

B. Beckert: Formal Formal Specification of Software – p.9

Page 24: UML State Machines

Transition

Properties

decribes change from one state to another state

without duration when executed

Role in diagram

triggering controlled by events, guards, state exit conditions

execution can cause actions

B. Beckert: Formal Formal Specification of Software – p.10

Page 25: UML State Machines

Transition

Properties

decribes change from one state to another state

without duration when executed

Role in diagram

triggering controlled by events, guards, state exit conditions

execution can cause actions

B. Beckert: Formal Formal Specification of Software – p.10

Page 26: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

B. Beckert: Formal Formal Specification of Software – p.11

Page 27: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoney

B. Beckert: Formal Formal Specification of Software – p.11

Page 28: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoney

B. Beckert: Formal Formal Specification of Software – p.11

Page 29: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoneyCheckPIN

B. Beckert: Formal Formal Specification of Software – p.11

Page 30: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoneyCheckPIN

B. Beckert: Formal Formal Specification of Software – p.11

Page 31: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoney

Guard

CheckPIN[correct]

CheckPIN[incorrect]

B. Beckert: Formal Formal Specification of Software – p.11

Page 32: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoney

Guard

CheckPIN[correct]

CheckPIN[incorrect]

B. Beckert: Formal Formal Specification of Software – p.11

Page 33: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoney

Action

CheckPIN[correct]

CheckPIN[incorrect]/increaseErrCounter

B. Beckert: Formal Formal Specification of Software – p.11

Page 34: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoney

Action

CheckPIN[correct]

CheckPIN[incorrect]/increaseErrCounter

B. Beckert: Formal Formal Specification of Software – p.11

Page 35: UML State Machines

Example: ATM

The customer must pass

authentication before

withdrawing money.

Authentication is done by

checking a PIN.

The PIN can be correct or

not.

Unseccessful attempts are

counted,

If the counter exceeds a

limit, the customer is

rejected.

Customer at ATM

Authentication WithdrawMoney

Rejected

SendEvent

CheckPIN[correct]

CheckPIN[incorrect and ErrCnt<Limit]/increaseErrCounter

CheckPIN[incorrect and ErrCnt>=Limit]ˆAuthentication Failed

B. Beckert: Formal Formal Specification of Software – p.11

Page 36: UML State Machines

Internal Transitions

Notation

Written as

Event[Guard]/Action

within the state box

Example

Authentication

reset/clearScreen

Difference to self transition

Entry and exit actions are not dispatched

B. Beckert: Formal Formal Specification of Software – p.12

Page 37: UML State Machines

Entry and Exit Actions

Notation

Written as

entry/Action resp.exit/Action

within the state box

Semantics

Dispatched on entering resp. exiting the state

B. Beckert: Formal Formal Specification of Software – p.13

Page 38: UML State Machines

Activities

Notation

Written as

do/Action

within the state box

Semantics

have duration

can be finished by event for outgoing transitions

B. Beckert: Formal Formal Specification of Software – p.14

Page 39: UML State Machines

Example: ATM (Alternative Formalisation)

Customer at ATM

Authentication

do/CheckPINentry/maskScreenexit/unmaskScreen

WithdrawMoney

Rejected

Closed

when(correct)

when(incorrect and ErrCnt<Max)/increaseErrCounter

when(incorrect and ErrCnt>=Max)ˆAuthorization Failed

deposit(amount)/changeAccount

withdraw(amount)[amount<=balance]/changeAccount

close

B. Beckert: Formal Formal Specification of Software – p.15

Page 40: UML State Machines

Exercise

A student must complete the basic level before enteringthe advanced level.

After both levels, the student has to pass five examinations.

An examination can be retaken at most twice.After the third failed attempt the student’s registration is cancelled.

B. Beckert: Formal Formal Specification of Software – p.16

Page 41: UML State Machines

Exercise: Student

A student must complete

the basic level before

entering the advanced level.

After both levels, the

student has to pass five

examinations.

An examination can be

retaken at most twice. After

the third failed attempt the

student’s registration is

cancelled.

B. Beckert: Formal Formal Specification of Software – p.17

Page 42: UML State Machines

Exercise: Student

A student must complete

the basic level before

entering the advanced level.

After both levels, the

student has to pass five

examinations.

An examination can be

retaken at most twice. After

the third failed attempt the

student’s registration is

cancelled.

Student

Basic Level

Advanced Level

B. Beckert: Formal Formal Specification of Software – p.17

Page 43: UML State Machines

Exercise: Student

A student must complete

the basic level before

entering the advanced level.

After both levels, the

student has to pass five

examinations.

An examination can be

retaken at most twice. After

the third failed attempt the

student’s registration is

cancelled.

Student

Basic Level

Advanced Level

B. Beckert: Formal Formal Specification of Software – p.17

Page 44: UML State Machines

Exercise: Student

A student must complete

the basic level before

entering the advanced level.

After both levels, the

student has to pass five

examinations.

An examination can be

retaken at most twice. After

the third failed attempt the

student’s registration is

cancelled.

Student

Basic Level

Advanced Level

when(FExaCnt>=5)

passMExa/inc(MExaCnt)

passFExa/inc(FExaCnt)

when(MExaCnt>=5)

B. Beckert: Formal Formal Specification of Software – p.17

Page 45: UML State Machines

Exercise: Student

A student must complete

the basic level before

entering the advanced level.

After both levels, the

student has to pass five

examinations.

An examination can be

retaken at most twice. After

the third failed attempt the

student’s registration is

cancelled.

Student

Basic Level

Advanced Level

when(FExaCnt>=5)

passMExa/inc(MExaCnt)

passFExa/inc(FExaCnt)

when(MExaCnt>=5)

B. Beckert: Formal Formal Specification of Software – p.17

Page 46: UML State Machines

Exercise: Student

A student must complete

the basic level before

entering the advanced level.

After both levels, the

student has to pass five

examinations.

An examination can be

retaken at most twice. After

the third failed attempt the

student’s registration is

cancelled.

Student

Basic Level

Advanced Level

Graduated

Examination

Cancelled

when(FExaCnt>=5)

passMExa/inc(MExaCnt)

when(MExaCnt>=5)

when(FailCnt>=3)

failFExa/inc(FailCnt)

enterFExa

passFExa/inc(FExaCnt)

B. Beckert: Formal Formal Specification of Software – p.17

Page 47: UML State Machines

Criticism

Not really a good model, because . . .

the student leaves the basic level to take an exam

the student can cheat by repeating a passed exam

the student cannot enter parallel exams

the student has to complete each exam once tried

the student cannot pass exams of the advanced levelwhile in the basic level

B. Beckert: Formal Formal Specification of Software – p.18

Page 48: UML State Machines

Advanced Constructs Can Help

Deferred event

Composite state

Concurrent composite state

Join state, Fork State

Concurrent transition

Junction state

Sync state

B. Beckert: Formal Formal Specification of Software – p.19

Page 49: UML State Machines

Events: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. Event is generated: Event raised (somewhere) by some action

2. Event is conveyed: Event transported to current object(transpotation does not change event)

3. Event is received: Event placed on event queue of current object

4. Event is dispatched Event de-queued from event queue(becomes current event)

5. Event is consumed Event is processed

B. Beckert: Formal Formal Specification of Software – p.20

Page 50: UML State Machines

Events: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. Event is generated: Event raised (somewhere) by some action

2. Event is conveyed: Event transported to current object(transpotation does not change event)

3. Event is received: Event placed on event queue of current object

4. Event is dispatched Event de-queued from event queue(becomes current event)

5. Event is consumed Event is processed

B. Beckert: Formal Formal Specification of Software – p.20

Page 51: UML State Machines

Events: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. Event is generated: Event raised (somewhere) by some action

2. Event is conveyed: Event transported to current object(transpotation does not change event)

3. Event is received: Event placed on event queue of current object

4. Event is dispatched Event de-queued from event queue(becomes current event)

5. Event is consumed Event is processed

B. Beckert: Formal Formal Specification of Software – p.20

Page 52: UML State Machines

Events: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. Event is generated: Event raised (somewhere) by some action

2. Event is conveyed: Event transported to current object(transpotation does not change event)

3. Event is received: Event placed on event queue of current object

4. Event is dispatched Event de-queued from event queue(becomes current event)

5. Event is consumed Event is processed

B. Beckert: Formal Formal Specification of Software – p.20

Page 53: UML State Machines

Events: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. Event is generated: Event raised (somewhere) by some action

2. Event is conveyed: Event transported to current object(transpotation does not change event)

3. Event is received: Event placed on event queue of current object

4. Event is dispatched Event de-queued from event queue(becomes current event)

5. Event is consumed Event is processed

B. Beckert: Formal Formal Specification of Software – p.20

Page 54: UML State Machines

Events: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. Event is generated: Event raised (somewhere) by some action

2. Event is conveyed: Event transported to current object(transpotation does not change event)

3. Event is received: Event placed on event queue of current object

4. Event is dispatched Event de-queued from event queue(becomes current event)

5. Event is consumed Event is processed

B. Beckert: Formal Formal Specification of Software – p.20

Page 55: UML State Machines

Event Processing: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. check Guard – if false abort

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg,Arg1)

(syncronous processing, i.e. wait until finished)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.21

Page 56: UML State Machines

Event Processing: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. check Guard – if false abort

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg,Arg1)

(syncronous processing, i.e. wait until finished)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.21

Page 57: UML State Machines

Event Processing: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. check Guard – if false abort

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg,Arg1)

(syncronous processing, i.e. wait until finished)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.21

Page 58: UML State Machines

Event Processing: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. check Guard – if false abort

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg,Arg1)

(syncronous processing, i.e. wait until finished)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.21

Page 59: UML State Machines

Event Processing: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. check Guard – if false abort

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg,Arg1)

(syncronous processing, i.e. wait until finished)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.21

Page 60: UML State Machines

Event Processing: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. check Guard – if false abort

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg,Arg1)

(syncronous processing, i.e. wait until finished)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.21

Page 61: UML State Machines

Event Processing: The Detailed View

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev(Arg)[Guard]/ActTrans(Arg, Arg1)

1. check Guard – if false abort

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg,Arg1)

(syncronous processing, i.e. wait until finished)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.21

Page 62: UML State Machines

Event Processing: Completion Event

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

[Guard]/ActTrans(Arg1)

1. wait until ActDo1 finishes (raises completion event)

2. check Guard – if false abort

3. execute ActExit1

4. execute ActTrans(Arg1)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.22

Page 63: UML State Machines

Event Processing: Completion Event

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

[Guard]/ActTrans(Arg1)

1. wait until ActDo1 finishes (raises completion event)

2. check Guard – if false abort

3. execute ActExit1

4. execute ActTrans(Arg1)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.22

Page 64: UML State Machines

Event Processing: Completion Event

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

[Guard]/ActTrans(Arg1)

1. wait until ActDo1 finishes (raises completion event)

2. check Guard – if false abort

3. execute ActExit1

4. execute ActTrans(Arg1)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.22

Page 65: UML State Machines

Event Processing: Change Event

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

when(Guard)/ActTrans(Arg1)

1. wait until Guard switches from false to true (raises change event)

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg1)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.23

Page 66: UML State Machines

Event Processing: Change Event

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

when(Guard)/ActTrans(Arg1)

1. wait until Guard switches from false to true (raises change event)

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg1)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.23

Page 67: UML State Machines

Event Processing: Change Event

State1

entry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

when(Guard)/ActTrans(Arg1)

1. wait until Guard switches from false to true (raises change event)

2. abort ActDo1

3. execute ActExit1

4. execute ActTrans(Arg1)

5. execute ActEntry2

6. execute ActDo2

B. Beckert: Formal Formal Specification of Software – p.23

Page 68: UML State Machines

Completion Event vs. Change Event

Activity

Completion event: after activity has ActDo1 finished

Change event: activity ActDo1 is aborted

Guard

Completion event: guard checked only once (on completion of activity)

Change event: guard checked continuously

B. Beckert: Formal Formal Specification of Software – p.24

Page 69: UML State Machines

Completion Event vs. Change Event

Activity

Completion event: after activity has ActDo1 finished

Change event: activity ActDo1 is aborted

Guard

Completion event: guard checked only once (on completion of activity)

Change event: guard checked continuously

B. Beckert: Formal Formal Specification of Software – p.24

Page 70: UML State Machines

Event Processing: Deferred Events

Special action defer

Ev/defer

Puts event Ev in list of deferred events

Can only be used in a state (not to label a transition)

Triggering deferred events

A deferred event is activated as soon as a state is enteredwhere it is not deferred

Lost events

Events that are neither handled nor deferred in the current state are lost

B. Beckert: Formal Formal Specification of Software – p.25

Page 71: UML State Machines

Event Processing: Deferred Events

Special action defer

Ev/defer

Puts event Ev in list of deferred events

Can only be used in a state (not to label a transition)

Triggering deferred events

A deferred event is activated as soon as a state is enteredwhere it is not deferred

Lost events

Events that are neither handled nor deferred in the current state are lost

B. Beckert: Formal Formal Specification of Software – p.25

Page 72: UML State Machines

Event Processing: Deferred Events

Special action defer

Ev/defer

Puts event Ev in list of deferred events

Can only be used in a state (not to label a transition)

Triggering deferred events

A deferred event is activated as soon as a state is enteredwhere it is not deferred

Lost events

Events that are neither handled nor deferred in the current state are lost

B. Beckert: Formal Formal Specification of Software – p.25

Page 73: UML State Machines

Event Processing: Deferred Events – Example

State1

Ev1/deferentry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev

Ev1

Scenario

State1 is current stateEv1 dispatched first, Ev dispatched afterwards

Then . . .

1. event Ev1 is deferred

2. transition from State1 to State2, consuming event Ev

3. event Ev1 is re-activated

4. transition from State2 to State1, consuming Ev1

B. Beckert: Formal Formal Specification of Software – p.26

Page 74: UML State Machines

Event Processing: Deferred Events – Example

State1

Ev1/deferentry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev

Ev1

Scenario

State1 is current stateEv1 dispatched first, Ev dispatched afterwards

Then . . .

1. event Ev1 is deferred

2. transition from State1 to State2, consuming event Ev

3. event Ev1 is re-activated

4. transition from State2 to State1, consuming Ev1

B. Beckert: Formal Formal Specification of Software – p.26

Page 75: UML State Machines

Event Processing: Deferred Events – Example

State1

Ev1/deferentry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev

Ev1

Scenario

State1 is current stateEv1 dispatched first, Ev dispatched afterwards

Then . . .

1. event Ev1 is deferred

2. transition from State1 to State2, consuming event Ev

3. event Ev1 is re-activated

4. transition from State2 to State1, consuming Ev1

B. Beckert: Formal Formal Specification of Software – p.26

Page 76: UML State Machines

Event Processing: Deferred Events – Example

State1

Ev1/deferentry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev

Ev1

Scenario

State1 is current stateEv1 dispatched first, Ev dispatched afterwards

Then . . .

1. event Ev1 is deferred

2. transition from State1 to State2, consuming event Ev

3. event Ev1 is re-activated

4. transition from State2 to State1, consuming Ev1

B. Beckert: Formal Formal Specification of Software – p.26

Page 77: UML State Machines

Event Processing: Deferred Events – Example

State1

Ev1/deferentry/ActEntry1exit/ActExit1do/ActDo1

State2

entry/ActEntry2exit/ActExit2do/ActDo2

Ev

Ev1

Scenario

State1 is current stateEv1 dispatched first, Ev dispatched afterwards

Then . . .

1. event Ev1 is deferred

2. transition from State1 to State2, consuming event Ev

3. event Ev1 is re-activated

4. transition from State2 to State1, consuming Ev1B. Beckert: Formal Formal Specification of Software – p.26

Page 78: UML State Machines

Composite States

Purpose

Allow to model complex behaviour

Idea

Similar sub-states are grouped into a composite state(nesting hierarchy is a tree)

Composite states can havetransitions, entry/exit actions, do activities, . . .(transitions can connect states from different nesting levels)

Sub-states “inherit” from the composite state

Note

State Machines are in fact composite statesB. Beckert: Formal Formal Specification of Software – p.27

Page 79: UML State Machines

Composite States: Example

Off

On

Initial

Process

switchOn

GoswitchOff

Initial, Process are sub-states of On

Initial, Process “inherit” transition switchOff

B. Beckert: Formal Formal Specification of Software – p.28

Page 80: UML State Machines

Composite States: Three Equivalent Models

Off

On

Initial

Process

switchOn

GoswitchOff

Off

Initial

Process

switchOn

switchOff Go

switchOff

Off

On

Initial

Process

switchOn

switchOff

Go

Note

These models are equivalent ifentry/exit actions anddo activities of Onare ignored

B. Beckert: Formal Formal Specification of Software – p.29

Page 81: UML State Machines

Composite States: Three Equivalent Models

Off

On

Initial

Process

switchOn

GoswitchOff

Off

Initial

Process

switchOn

switchOff Go

switchOff

Off

On

Initial

Process

switchOn

switchOff

Go

Note

These models are equivalent ifentry/exit actions anddo activities of Onare ignored

B. Beckert: Formal Formal Specification of Software – p.29

Page 82: UML State Machines

Composite States: Three Equivalent Models

Off

On

Initial

Process

switchOn

GoswitchOff

Off

Initial

Process

switchOn

switchOff Go

switchOff

Off

On

Initial

Process

switchOn

switchOff

Go

Note

These models are equivalent ifentry/exit actions anddo activities of Onare ignored

B. Beckert: Formal Formal Specification of Software – p.29

Page 83: UML State Machines

Composite States: Active States

Off

On

Initial

Process

switchOn

GoswitchOff

Active states

Sub-state and composite state can be active simultaneously

“Active state” now denotes a pathfrom a top-level state to a leaf node in the state hierarchy

B. Beckert: Formal Formal Specification of Software – p.30

Page 84: UML State Machines

Composite States: Rules for Entering States

Off

On

Initial

Process

switchOn

GoswitchOff

Entering a composite state

There must be an initial sub-state

Entering a sub-state

Both the composite state and sub-state are activated

Order of entry actions: top-downB. Beckert: Formal Formal Specification of Software – p.31

Page 85: UML State Machines

Composite States: Rules for Exiting States

Off

On

Initial

Process

switchOn

GoswitchOff

Exiting a composite state

Exit active sub-state as well.

Exiting a sub-state

Order of exit actions: bottom-up

When final state becomes active sub-state, completion event is raisedB. Beckert: Formal Formal Specification of Software – p.32

Page 86: UML State Machines

Concurrent Composite States

Taking Class

Incomplete

Lab1 Lab2

Project

Final Test

Passed

Failed

lab done

project done

pass

lab done

fail

Regions

Concurrent parts of composite state

Are activated synchronously (when composite state is acitivated)

Separated by dashed linesB. Beckert: Formal Formal Specification of Software – p.33

Page 87: UML State Machines

Concurrent Composite States

Taking Class

Incomplete

Lab1 Lab2

Project

Final Test

Passed

Failed

lab done

project done

pass

lab done

fail

Active state

Also called state configuration

Now consists of ???

a sub-tree of the state hierarchy

B. Beckert: Formal Formal Specification of Software – p.34

Page 88: UML State Machines

Concurrent Composite States

Taking Class

Incomplete

Lab1 Lab2

Project

Final Test

Passed

Failed

lab done

project done

pass

lab done

fail

Active state

Also called state configuration

Now consists of a sub-tree of the state hierarchy

B. Beckert: Formal Formal Specification of Software – p.34

Page 89: UML State Machines

Concurrent Composite States: Rules for Entering

Taking Class

Incomplete

Lab1 Lab2

Project

Final Test

Passed

Failed

lab done

project done

pass

lab done

fail

Entering a composite state

There must be an initial sub-state in each region

Entering a sub-state

There must be an initial sub-state in all other regionsB. Beckert: Formal Formal Specification of Software – p.35

Page 90: UML State Machines

Concurrent Transitions

Taking Class

Incomplete

Lab1 Lab2

Project

Final Test

Passed

Failed

lab done

project done

pass

lab done

fail

Concurrent transition

Alternative notation for entering concurrent composite state

Uses pseude-states “fork” and “join”

B. Beckert: Formal Formal Specification of Software – p.36

Page 91: UML State Machines

History States

Taking Class

Incomplete

Lab1 Lab2

Project

Final Test

H

Passed

Failed

Army

lab done

project done

pass

lab done

fail

was killed

outbreak of war

resume

When re-entering composite state,establishes the last active configuration

Outgoing transition indicates default active configurationB. Beckert: Formal Formal Specification of Software – p.37

Page 92: UML State Machines

History States: Shallow vs. Deep

Taking Class

Incomplete

Lab1 Lab2

Project

Final Test

H

Passed

Failed

Army

lab done

project done

pass

lab done

fail

was killed

outbreak of war

resume

Shallow (H): Records history only of composite state is belongs to

Deep (H∗): Records history of sub-states as well

B. Beckert: Formal Formal Specification of Software – p.38

Page 93: UML State Machines

Synch States

Taking Class

Incomplete

Lab1 Lab2

*

Project

Final Test

Passed

Failed

lab done

project done

pass

lab done

fail

Allow to synchronise regions

Used in combination with fork and join

B. Beckert: Formal Formal Specification of Software – p.39

Page 94: UML State Machines

Junction Points

State1 State2

State3 State4 State5

e1[g1]

e2[g2]

[g3]

[g4]

[g5]

Purpose

Simplify notation, allow to “factor out” transitions

Different from fork/join

B. Beckert: Formal Formal Specification of Software – p.40

Page 95: UML State Machines

Junction Points

Example without junction point

State1 State2

State3 State4 State5

e1[g1 and g3]

e1[g1 and g4]

e1[g1 and g5]e2[g2 and g3]e2[g2 and g4] e2[g2 and g5]

B. Beckert: Formal Formal Specification of Software – p.41

Page 96: UML State Machines

Metamodel for State Machine

ModelElement(from core)

StateMachineGuard

expression:BooleanExpression

StateVertex Transition

PseudoState

kind:PseudostateKind

SynchState

bound:UnlimitedInteger

StubState

referenceState:Name

State

Action

(from CommonBehavior)

Event

CompositeState

isConcurrent:BooleanSimpleState FinalState

+context 0..1

+behavior *

source

1 +outgoing

*

target

1 +incoming

*

0..1

+top 1

0..1

+transitions*1

+guard0..1

*

+trigger 0..1

0..1

+internalTransition*

0..1

+effect0..10..1

+entry

0..1

0..1

+exit

0..1

0..1

+doActivity

0..1

0..* +deferrableEvent

0..*

0..1

container

+submachine

1

B. Beckert: Formal Formal Specification of Software – p.42

Page 97: UML State Machines

PseudoStateKind

initial

final

deepHistory

shallowHistory

join

fork

junction

B. Beckert: Formal Formal Specification of Software – p.43

Page 98: UML State Machines

A Constraint of the Meta Model

Constraint on context of StateMachine

A state machine is aggregated within either a classifier ora behavioural feature (e.g. an operation)

context StateMachine

inv self.context.notEmpty implies

self.context.oclIsKindOf(BehavioralFeature) or

self.context.oclIsKindOf(Classifier))

Note

Nothing said about what happens if self.context.isEmpty

B. Beckert: Formal Formal Specification of Software – p.44

Page 99: UML State Machines

A Constraint of the Meta Model

Constraint on context of StateMachine

A state machine is aggregated within either a classifier ora behavioural feature (e.g. an operation)

context StateMachine

inv self.context.notEmpty implies

self.context.oclIsKindOf(BehavioralFeature) or

self.context.oclIsKindOf(Classifier))

Note

Nothing said about what happens if self.context.isEmpty

B. Beckert: Formal Formal Specification of Software – p.44