UML and MDA for UML and MDA for Transactional Level Transactional Level Modeling Modeling S. Bocchio S. Bocchio , A. Rosti , A. Rosti STMicroelectronics STMicroelectronics E. E. Riccobene Riccobene , , P. P. Scandurra Scandurra University of Milan University of Milan
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UML and MDA for UML and MDA for Transactional Level Transactional Level ModelingModeling
S. BocchioS. Bocchio, A. Rosti , A. Rosti STMicroelectronicsSTMicroelectronicsE. E. RiccobeneRiccobene, , P. P. ScandurraScandurraUniversity of MilanUniversity of Milan
2UML and MDA for TLM
Introduction: motivation and objectivesBackground: the SystemC UML profile and the toolfor the UML/SystemC profileUpdate to SystemC2.1 and TLMExamples:
import existing SystemC models into UML SystemC back annotation = SystemC parser + XMI generatorEA selecting Project | Import/Export | Import package from XMI file..
SC2UML
SystemCfilesSystemCfiles
SystemCparser
XMI generator
XMIfile
JAVACC grammar 4 C++/SystemC
JDOM/JSAXAPI
15UML and MDA for TLM
SystemC 2.1: new features
Sc_exportDynamic thread
void exec(){while(true){
if(init==true)sc_spawn(&f,..);
wait();action();
}}
16UML and MDA for TLM
systemC 2.1 new features
SC_FORK, SC_JOIN
void exec(){SC_FORK
sc_spawn(&test,..);sc_spawn(&void,..);
SC_JOINwhile(true){
do_exec();}
}
17UML and MDA for TLM
What is TLM?
Modeling communication through function callsBased on the concept of interfacesBut can be accurate from the Timing perspectiveImplemented by channels exposing interfaces.Also gain simulation speed because communication is not pin accurate
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OSCI TLM 1.0 Standard
TML was possible since SystemC 2.0 Lack of standard library and methodologies can lead to incompatibilities
OSCI TLM standard set of API for communicationUnidirectional blocking and non blocking
put(.), get(.), peek(.)Implemented by tlm_fifo<T>
Bidirectional blocking interfacetransport(.)Implemented by tlm_transport_channel<REQ,RSP>
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OSCI TLM library in UML
A set of model..
20UML and MDA for TLM
OSCI TLM library in UML
A set of model..
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OSCI TLM 1.0 library
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The Simple Bus (transactional level)
M1 uses the blocking master interface (a high level software)
M2 uses the non blocking master interface (a processor executing on every clock
edge even if its bus transactions are not completed)
M3 uses the direct master interface to print debug information about memoriesS1, S2 provide the same interface
S1 is a fast memory supportingsingle-cycle read/write operationsS2 is a slow memory that takes ncycles per each read/write operation
ARB
BM MON
BUS
NBM
SLOWMEMFASTMEM
clock
S. Bocchio… “A model driven designEnvironment for Embedded System”, DAC ‘06
23UML and MDA for TLM
ST TLM_infra library
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The arbiter
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The arbiter
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The platform (class diagram)
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The platform instance (object diagram)
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Conclusion
UML profile make simpler platform building
UML is NOT just a way to have a composition tool!Code generationSystem viewModel validation…