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Page 1 Copyright © 2017 Avnet, Inc. AVNET, “Reach Further,” and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners.
LIT# UG-AES-ZU7EV-CC-G-V1
UltraZed™-EV Carrier Card Hardware User Guide Version 1.0
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Document Control Document Version: 1.0
Document Date: 12/15/2017
Document Author(s): Paul Blaschka
Document Classification: Public
Document Distribution: Public
Prior Version History Version Date Comment 1.0 12/15/2017 Initial Release
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Contents 1 Introduction ........................................................................................................... 5
1.1 UltraZed-EV Carrier Card List of Features: ................................................................ 5 1.2 Carrier Card Block Diagram ....................................................................................... 8
1.2.1 Additional Documentation ................................................................................................. 9 2 Functional Description ........................................................................................ 10
2.1 JX Micro Connectors................................................................................................ 10 2.1.1 JX1 Connector ................................................................................................................ 10 2.1.2 JX2 Connector ................................................................................................................ 10 2.1.3 JX3 Connector ................................................................................................................ 10
2.2 PS USB 2.0/3.0 Interface – J17 ............................................................................... 11 2.2.1 USB 2.0 Interface ........................................................................................................... 11 2.2.2 Device, Host or OTG mode select jumpers – JP21, JP22, JP23 ................................... 11 2.2.3 USB 3.0 Interface – J17 ................................................................................................. 13
2.3 PS RJ45 Connector – J8 ......................................................................................... 14 2.4 PS Display Port x1 interface – P1 ............................................................................ 15 2.5 PS SATA 3.0 Host Interface – J6............................................................................. 18 2.6 PS PMOD Header – JPS1 ....................................................................................... 19 2.7 PS Micro USB Connector (Dual USB-UART Ports) – J16 ....................................... 20 2.8 PS microSD Card Connector – J7 ........................................................................... 21 2.9 PS User LED – D25 ................................................................................................. 22 2.10 PL User Switches – Slide DIP & Push Buttons – SW1-SW5 ................................... 22 2.11 PL User LEDs – D17:D24 ........................................................................................ 24 2.12 PL PMOD Headers – JA1 & JA2 PL-PMODs .......................................................... 25 2.13 PCIe Gen2 x1 Root Port – J14 ................................................................................ 26 2.14 HDMI Input & Output interfaces – J9 & J10 ............................................................. 27 2.15 PL 3G-SDI Transmit & Receive Interfaces – J11-J13 .............................................. 31 2.16 PL Dual SFP+ Interfaces – P3 & P4 ........................................................................ 33 2.17 PL FMC HPC Slot Interface – JX4 ........................................................................... 36 2.18 Carrier Card I2C Interface........................................................................................ 42 2.19 Clock Generators – Clock 1 and Clock 2. ................................................................ 43 2.20 Clock Generator 1 – U3, IDT 5P49V5935B539LTGI ............................................... 44
2.20.1 Clock Configuration connectors JP1, JP16, JP17 .......................................................... 45 2.21 Clock Generator 2 – U6, IDT 8T49N241-048NLGI .................................................. 46 2.22 Clock Input – GTH REFCLKs via SMAs – J1 to J4 .................................................. 49 2.23 MAC ID Device - U7, 24AA025E48-I/OT ................................................................. 49
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2.24 SOM Reset input – SW6 .......................................................................................... 50 2.25 Carrier Card Reset input – from SOM ...................................................................... 50 2.26 JTAG Topology – SMT2, PC4, FMC ........................................................................ 51
2.26.1 USB-JTAG Module, SMT2, U14 ..................................................................................... 52 2.26.2 PC4 JTAG Header, J15 .................................................................................................. 52 2.26.3 FMC2 JTAG Interface – JX4 .......................................................................................... 52
2.27 LVDS Touch Panel Interface – P2 ........................................................................... 53 2.28 LEDs – Power Status – D14, D15, D26-D36 ........................................................... 55 2.29 Fan Header – JP14 .................................................................................................. 56 2.30 Unused PL I/O ......................................................................................................... 56
3 Carrier Card Power ............................................................................................. 57 3.1 Power In connector – J18 ........................................................................................ 57 3.2 Power Switch – SW8 ............................................................................................... 58 3.3 Power Input – dedicated rails................................................................................... 59 3.4 Power Monitor interfaces: SYSMON (J21) and VMON J19, J20 ............................. 59
3.4.1 Power Supply monitor header – J19, J20 ...................................................................... 60 3.5 PMBus Interface – J22 ............................................................................................ 60 3.6 Carrier Card Power Supplies ................................................................................... 61 3.7 Power Control .......................................................................................................... 62 3.8 Infineon IRPS38063MTRPBF PMIC – U18, 0x1B ................................................... 62 3.9 Infineon IRPS38063MTRPBF PMIC – U19, 0x1C ................................................... 64 3.10 Infineon IRPS5401MTRPBF PMIC – U21, 0x19 ...................................................... 66
3.10.1 Power supply net ties...................................................................................................... 66 3.10.2 IRPS5401 PMIC Feedback resistors – U21 ................................................................... 68 3.10.3 IRPS5401 PMIC Power Sense signals – U21 ............................................................... 69
3.11 Infineon IRPS5401MTRPBF PMIC – U22, 0x1A ..................................................... 70 3.11.1 IRPS5401 PMIC Feedback resistors – U22 ................................................................... 72 3.11.2 IRPS5401 PMIC Power Sense signals – U22 ............................................................... 73
3.12 Display Port Regulator – U1 .................................................................................... 76 3.13 PS VBATT LR44 Battery – JP13 & BTH-1 ............................................................... 77 3.14 PS VBATT placement .............................................................................................. 78 3.15 Power Supply Sequencing and Power Modes ......................................................... 80
4 PCB Information ................................................................................................. 83 4.1 PCB Characteristics ................................................................................................. 83
4.1.1 PCB Electrical Characteristics: ....................................................................................... 83 4.1.2 PCB Stack Up ................................................................................................................. 83
5 UltraZed-EV Carrier Card Mechanical ................................................................ 85
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1 Introduction The UltraZed-EV Carrier Card (CC) is a development board designed to be used by customers for rapid proof-of-concept and prototype development efforts using the Avnet UltraZed-EV System On Module (SOM) module(s). Leveraging the Carrier Card and SOM solution greatly reduces time to market and hardware risk by increasing target application development time on a proven reliable hardware platform. Further, the design files for the carrier card are made readably available to customers, allowing a direct design copy of what is proven to work.
This carrier card provides all of the necessary SOM power, clock, reset control and SoC I/O pin accessibility through the JX1, JX2, and JX3 MicroHeaders and also includes multiple industry standard interfaces.
The carrier card also provides two debug interfaces - SMT2 (Micro USB) and PC-4 JTAG header. The SMT2 interface requires a micro USB cable. The PC-4 requires a debug module such as the Digilent ® HS3 dongle. Both interfaces are provided to assist with SOM application development.
This document details the specific features, operation and configuration of the UltraZed-EV CC board. Please visit http://www.ultrazed.org/product/ultrazed-ev-carrier-card. For the latest product information. The CC board features are listed below.
1.1 UltraZed-EV Carrier Card List of Features: The UltraZed-EV Carrier card provides the following features and interfaces. Please refer to the associated section of this document for further information.
– Supports the following UltraZed-EV SOM types: – XCZU7EV-1FBVB900 – XCZU7EG-1FBVB900
– SOM Connections:
– 2 high density 200 pin JX connectors (JX1, JX2) – 1 high density 120 pin JX connector (JX3)
– Industry I/O Interfaces:
– 1 SATA 3.0 Host interface – 1 Display Port connector – 1 USB 2.0/3.0 Host & OTG micro AB connector – 1 10/100/1000 Mb/s RJ45 connector – 1 Dual USB-UART using Micro USB connector – 1 LVDS Touch Panel interface – 2 SMA User Clock inputs – 2 PL PMOD headers (single ended) – 1 PS PMOD header (single ended)1 HDMI In Interface – 1 FMC HPC connector – 1 HDMI In Interface – 1 HDMI Out Interface – 1 3G-SDI SMPTE BNC interface (3 BNC connectors) – 2 SFP+ Interfaces – 1 microSD card connector
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– User switches, pushbuttons and LEDs: – 8 position PL user DIP (slide) switches – 4 PL user push button switches – 8 PL user LEDs – 1 PS user LED – 1 PS VBATT battery socket – 1 PS VBATT header (0.1” header) – 1 SOM reset switch
– Debug & Configuration: – Digilent® SMT2 USB-JTAG module – PC-4 JTAG header – 2 PMIC Voltage Monitor headers – provide easy DMM probe access to each voltage rail – 1 PMBus header – Various interface LED indicators displaying fault, link, speed and power – PG_Module LED – PG_MODULE LED – +VIN_HDR LED – SOM Reset LED – USB OTG, Host/Device mode jumpers – 11 Power Supply LEDs – indicate if each board rail is powered up – Various interface LED indicators displaying fault, link, speed and power – Write protect jumper on microSD card interface – PS GTR clock synthesizer has jumper selectable start-up configuration – 1 Power Enable 0.1” pad set (to turn on PMIC’s without a SOM attached) – 5 Ground Test Points – 1 SOM +5V fan connector
– I2C interfaces:
– I2C programmable differential clock generator – I2C MAC address memory device – I2C PMBUS for programmable PMICs
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– Power: – +VIN 11.6V up to 12.2V via six pin power connector
– NOTE: This is a new, high power 120 Watt connection – Power slide switch – High power high side MOSFET switch with capacitor adjustable turn on time – 2 High power Infineon single channel I2C programmable IR38063 PMICs – 2 high power Infineon 5 Channel I2C programmable IRPS5401 PMICs – 2 dual row 8 pin voltage monitor header sockets for board power measurements – Remote rail sensing of SOM. PMICs voltage adjusts according to SOM loading – Isolated Vin to +3.3V regulator – +VIN connections to SOM via JX connectors – PMBus™ header accesses all PMICs on one I2C bus – PL SYSMon header – PS VBATT battery connection with diode steering protection
LR-44 Battery slot, external jack or on board 1.8V power Dual 100 mil header with over voltage protection for user voltage input
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1.2 Carrier Card Block Diagram Below is a high level block diagram of the UltraZed-EV Carrier Card.
Figure 1 – UltraZed-EV Carrier Card Block Diagram
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Glossary
Term Definition CC UltraZed-EV Carrier Card. The SOM attaches to this carrier card (board) for user evaluation. The
CC features proven high speed interfaces to the SOM as well as the necessary power, control and clocks required for the SOM to operate.
MIO Multiplexed Input Output – the dedicated I/O available on the PS PL Programmable Logic – programmable fabric of the SoC. PMIC Power Management Integrated Circuit – voltage regulator used to create required board voltages.
Pre-programmed by Avnet. The user may re-program via using the CC I2C PMBus. POR Power On Reset – reset asserted during power on event. Keeps board in reset until PMIC’s
output is stabilized. PS Processing System – the SoC’s processor cores – Application Processing Unit (Quad core ARM
Cortex-A53) and Real-Time Processing Unit (Dual core ARM Cortex-R5). SMPS Switch Mode Power Supply – switching power supply used to provide high current rails to the
board. May be separate from the PMIC or may be the PMIC, depending application needs. SOM System On Module – a SoC IC placed on a PCB allowing easy access to the SoC IC’s interface,
power and control signals. Includes the necessary memory (RAM, storage), power and connectors to operate as a pluggable processing module.
SoC System On Chip – Xilinx Zynq UltraScale+ IC. Net Ties (NTs)
Net Ties (NTs) are used throughout the Carrier Card and are placed to allow non-port naming of signals. This is done to facilitate routing or to clarify the signal function and is not required for production designs by the customer.
Table 1: Glossary
1.2.1 Additional Documentation – Additional information and documentation on Avnet’s UltraZed product line can be found
at www.ultrazed.org/product/ultrazed-EV – Additional information and documentation on Xilinx’s Zynq® UltraScale+ All
Programmable Heterogenous MPSoCs can be found at http://www.xilinx.com/products/silicon-devices/soc/zynq-ultrascale-mpsoc.html
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2 Functional Description The following chapter details all of the CC interfaces, their configuration and their functional attributes. This carrier card provides 26 PS MIO pins and 180 user PL I/O pins (72 differential pairs and 36 single-ended) organized as follows:
– 26 PS MIO bank 501, MIO[26:51] – 48 PL HD (High Density) I/O pins (2 banks) – 104 PL HP (High Performance) I/O pins (2 banks)
2.1 JX Micro Connectors The UltraZed-EV Carrier Card has 3 Samtec SEAF8 series JX connectors to gain access to the UltraZed-EV SOM I/O pins. The JX connectors provide the following signals including power/ground pins (signal directions are with respect to the UltraZed-EV SOM). Please refer to the Ultrazed-EV master JX pinout guide: http://www.ultrazed.org/product/ultrazed-ev-carrier-card.
2.1.1 JX1 Connector – High density 200-pin Socket, Samtec part number: SEAF8-50-05.0-S-04-2-K – JTAG pins (JTAG_TMS, JTAG_TCK, JTAG_TDI, and JTAG_TDO) – SYSMON pins (SYSMON_V_P, SYSMON_V_N, SYSMON_DX_P, and SYSMON_DX_N) – 48 differential HP I/O pairs (HP_DP) – 8 single ended signals (HP_SE) – SOM_RESET_IN_N input – CC_RESET_OUT_N output – SOM_PG_OUT output – PMBus signals (PMBus_DATA, PMBus_CLK, and PMBus_ALERT_N) – Power and ground pins (VCCO_HP_64, VCCO_HP_65, VCCO_HD_47, VCCO_HD_48,
VIN and GND) 2.1.2 JX2 Connector
– High density 200-pin Socket, Samtec part number: SEAF8-50-05.0-S-04-2-K – 48 single ended IO/24 differential input signals (HD_SE) – 16 GTH transceivers (GTH[0:15]) – 8 GTH reference clock inputs (GTH_REFCLK[0:7]) – Power and ground pins (MGTAVCC, MGTAVTT, MGTVCCAUX, and GND)
2.1.3 JX3 Connector – High density 120-pin Socket, Samtec part number: SEAF8-30-05.0-S-04-2-K – PS GTR[0:3], PS GTR_REFCLK[0:3] – PS MIO bank 501 pins (MIO[26:51]) – USB 2.0 connector interface (USB_OTG_P, USB_OTG_N, USB_ID, USB_OTG_VBUS,
and USB_OTG_CPEN) – Gigabit Ethernet connector interface (ETH_MD[1:4]_P, ETHMD[1:4]_N, and
ETH_PHY_LED[0:1]) – Carrier Card I2C interface (CC_SDA, CC_SCL, and CC_INT_N) – PS_VBATT input – Power and ground pins (MGTRAVCC, MGTRAVTT, VCCO_PSIO_501, and GND) – Voltage sense feedback output pins (MGTAVCC_Sense, MGTAVTT_Sense,
MGTVCCAUX_Sense, MGTRAVCC_Sense, MGTRAVTT_Sense, VCCO_HP_64_Sense, VCCO_HP_65_Sense, VCCO_HD_47_Sense, and VCCO_HD_48_Sense)
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2.2 PS USB 2.0/3.0 Interface – J17 The UltraZed-EV Carrier Card’s USB 2.0/3.0 interface is implemented with a Kycon KMMX-AB10-SMT1SB30TR Micro AB connector capable of supporting OTG, Device and Host modes. The UltraZed-EV SOM contains the USB 2.0 ULPI PHY interface (USB3320 IC) for USB 2.0. PS GTR[2] is used to implement the USB 3.0 interface to the same connector.
2.2.1 USB 2.0 Interface
a. The USB 2.0 interface is connected via the SOM’s ULPI PHY IC. b. The interface differential impedance is 90 Ω (+/- 5%), Single Ended is 45 Ω (+/- 5%) c. Power: 5V, 500mA. d. CPEN is used to enable the ACPI/USB compliant Microchip MIC2544_1YMM high side
switch IC. When CPEN is logic high, “enabled”, the +5.0V rail is passed through to the +USB_VB rail for the USB connector.
e. When CPEN is low the power switch is disabled. f. R102 is used to set the current limit of the MIC2544 part. The value of 191 ohms is used
to set the current to 1.23 Amps. g. When in Host or OTG mode, FB8 and FB9 along with two capacitors are used to provide
filtered power to the USB connector J12. h. D42 ESD suppression array protects the USB_OTG_P/N signals. i. LED D40 is used to indicate a current limit or thermal shutdown event with the MIC2544
IC. The output is open-drain and asserted low when a flag event has occurred which causes D24 to turn on. The output is not latched and therefore clears once the event ends thereby extinguishing D24.
2.2.2 Device, Host or OTG mode select jumpers – JP21, JP22, JP23
a. J22 selects how the USB_ID net is connected. Pin 1 to 2 allows the USB device to connect to the SOM, pin 2 to 3 forces the pin to +3.3V. No populate allows the pin to float. When floating the interface is set to Device mode but once connected the operation can be reversed via the Host Negotiation Protocol (HNP). By default the jumper is not populated.
Figure 2 – JP22 USB_ID select jumper
b. JP12 is used to select the power for +USB_VB. c. JP21 used to select the pullup resistor for the USB_OTG_VBUS net going to the SOM. d. JP23 used to select the appropriate +USB_VB bus capacitance for the operating mode. e. The mode jumper positions are listed below. Default positions are USB in Host Mode.
CC Signal Name: JX3 Pin #: USB_ID D17
Table 2: USB Mode Select jumpers
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Jumper Number: Jumper Position: Mode select: JP12 On Host or OTG (default) JP12 Off Device JP21 Pin 1 – 2 Device or OTG JP21 Pin 2 – 3 Host (default) JP23 Pin 1 – 2 Device or Host (default) JP23 Pin 2 – 3 OTG
Table 3: USB Mode Select jumpers
Figure 3 – USB Device, OTG and Host select, JP12 & JP23
Figure 4 – USB Device, OTG and Host select, JP21
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CC Signal Name: JX3 Pin #: USB_OTG_VBUS C17 USB_OTG_CPEN C16
Table 4: USB Mode Select jumpers
2.2.3 USB 3.0 Interface – J17 The USB 3.0 interface has the following specifications:
a) Data transfer rate up to 5 Gb/s (625 MB/s) and is referred to as USB Super Speed. This portion of the interface is directly connected to the Zynq PS via PS GTR[2] and J17, the integrated USB micro-AB connector.
b) Power capability is up to 1.23A @ 5V for non-data (charging) power delivery. c) Power capability up to 900mA during data transfer. d) Zdiff is 100Ω (+/- 5%). e) 52 MHz GTR_REFCLK2_P/N clock derived from IDT 5P49V5935LTGI programmable clock
generator. f) GTR_TX2_P/N signals have 0.1uF AC coupling capacitors. g) D41 ESD suppression array used on GTR_TX/RX_P/N signals.
Figure 5 – USB 2.0/3.0 Port Interface
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CC Signal Name: JX3 Pin #: USB_OTG_N D15 USB_OTG_P D14 GTR_TX2_N B3 GTR_TX2_P B2 GTR_RX2_N A5 GTR_RX2_P A4
Table 5: USB 3.0 connections
2.3 PS RJ45 Connector – J8 The UltraZed-EV Carrier Card utilizes an RJ45 connector with integrated magnetics. The UltraZed-EV’s RGMII SOM Gigabit Ethernet PHY interface along with the Carrier Card RJ45 connector are used to implement a single Gigabit Ethernet port as shown below. The current choice of connector is a BEL FUSE L829-1J1T-43 RJ45.
– The MDI impedance is 50 Ω single ended, +/- 5% and is referenced to the positive plane (See TI AN1263) if termination resistors are used at the SOM.
– The maximum distance of the total trace run do not exceed 6” from SOM PHY to RJ-45. – The trace lengths are matched within 10 mils pair to pair and no more than 100 mils overall between
the entire group of pairs. – Two LEDs to indicate speed and activity status:
o ETH_PHY_LED0: Green Speed o ETH_PHY_LED1: Yellow Activity
Figure 6 – Gigabit Ethernet Port
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Figure 7 – Gigabit Ethernet Port
CC Signal Name: JX3 Pin #: ETH_MD1_P B14 ETH_MD1_N B15 ETH_MD2_P A15 ETH_MD2_N A16 ETH_MD3_P B17 ETH_MD3_N B18 ETH_MD4_P A18 ETH_MD4_N A19 ETH_PHY_LED0 C20 ETH_PHY_LED1 C18
Table 6: Gigabit Ethernet Port pin mapping
2.4 PS Display Port x1 interface – P1 The UltraZed-EV Carrier Card has a single Display Port output connected to the PS GTR[3] TX port. The Display Port interface also uses an auxiliary interface (DPAUX) which is implemented on the Carrier Card using the PS MIO[27:30] signals (these are pre-defined MIO pins for the DPAUX when the display port is used).
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Figure 8 – Display Port x1 interface
Figure 9 – Display Port DPAUX Generator including Z match and AC coupling
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Figure 10 – Display Port 3.3V power supply
Figure 11 – Display Port GTR TX ESD protection
CC Signal Name: JX3 Pin #: GTR_TX3_P D2 GTR_TX3_N D3 MIO_27 C22 MIO_28 D22 MIO_29 C23 MIO_30 D23
Table 7: Display Port connections
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2.5 PS SATA 3.0 Host Interface – J6 The UltraZed-EV Carrier Card’s SATA 3 host interface uses the SoC’s PS GTR[1] transceiver. The interface includes AC coupling capacitors with appropriate PCB GSSG cut-outs and a maximum of 2 layer transitions per signal with no blind or buried vias. This topology is used to minimize impedance mismatches thereby improving signal integrity.
– Interface impedance: 100 ohms, +/- 15% – Data rates up to 6 Gb/s
Figure 12 – SATA Port interface
CC Signal Name: JX3 Pin #: GTR_TX1_P D6 GTR_TX1_N D7 GTR_RX1_P C8 GTR_RX1_N C9
Table 8: SATA Port connections
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2.6 PS PMOD Header – JPS1 The PS PMOD header is connected to the PS MIO[36:43] pins and operated at 3.3V I/O using the VCCO_PSIO_501 rail. The PS MIO[36:43] maps to SPI, however the UltraScale+ does not create a direct map to the UART(0 or 1) nor I2C MIO pins. Table 9: PS PMOD to MIO UltrZed SOM Table mapping shows the UART and I2C connections.
– Routed at 50Ω single ended. – The interface follows, as close as possible, the Digilent SPI and UART/I2C pinouts.
See page 581 – 583 for TRM pin mapping: http://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
Figure 13 – PS PMOD interface
Table 9: PS PMOD to MIO UltrZed SOM Table mapping
CC Net Name: TRM SPI0 TRM I2C0 TRM I2C1 TRM UART0 TRM UART1 JX3 Connector MIO36 SCL TXD D27 MIO37 SDA RXD C28 MIO38 SCLK SCL RXD D29 MIO39 N_SS[2] SDA TXD C30 MIO40 N_SS[1] SCL TXD B20 MIO41 N_SS[0] SDA RXD A21 MIO42 MISO SCL RXD B21 MIO43 MOSI SDA TXD A22
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2.7 PS Micro USB Connector (Dual USB-UART Ports) – J16 The dual USB UART port is via a microUSB connector. The PHY interface IC is Silicon Labs CP2105 dual USB-UART device. The port has been configured for persistence, allowing the device to remain enumerated even when the Carrier Card’s power is turned off.
– USB 2.0 compliant with royalty free drivers available for download. – VDD and VIO are attached together to provide a persistent USB connection. When a host PC
is attached, VBUS is used to generate VDD. No other board power is needed for the UART to be turned on. When the board is in the powered off state, no +3.3V is present so suspend LEDs D37 and D39 will not turn on until the board is powered on.
– Port 0 is connected to Bank 501 PS MIO[34:35], RXD, TXD and are level translated via MOSFETs. These signals are swapped on the carrier creating a null-modem connection. This allows a straight through cable connection.
– Port 1 is connected to Bank 501 PS MIO[32:33], TXD, RXD and are level translated via MOSFETs. These signals are swapped on the carrier creating a null-modem connection. This allows a straight through cable connection.
– GPIO signals or Modem control signals are not used and are brought out to a test pad for user convenience.
– LEDs: D37 and D39 indicate when the device is in suspend mode. By default the pins are active low during a suspend state. These pins are user programmable, and if desired, the polarity can be reversed allowing the LEDs to be on during normal operation and extinguish during suspend. Please refer to the Silicon Labs CP2105 datasheet for further information. https://products.avnet.com/shop/en/ema/uart/cp2105-f01-gmr-3074457345626208393
– The UART reset pin has an RC time delay from power up. This pin is also be controlled by the SOM’s CC_RESET_OUT_N signal.
– A Vendor ID (VID) is not programmed into the OTP ROM. The device uses the default VID provided by Silicon Labs.
– A unique PID (Product ID) can be programmed in via the USB interface by the user. To accomplish this, a 4.7uF cap is required between NC/DCD_ECI/VPP pin and ground as shown below. Upon completion of programming, the capacitor should be removed.
– ESD device D38 is used on the USB D+ and D- lines for ESD protection. – Impedance is 45Ω single ended control, 90Ω differential.
Figure 14 – PS PMOD interface
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CC Net Name: UART Signal Name: JX3 Pin #: MIO_32 MIO_32.UART1_TXD D25 MIO_33 MIO_33.UART1_RXD C26 MIO_34 MIO_34.UART0_RXD D26 MIO_35 MIO_35.UART0_TXD C27
Table 10: UART Table
2.8 PS microSD Card Connector – J7 The PS MIO[44:51] pins are used to interface to a micro-SD card connector. The interface operates at 3.3V. Since microSD cards do not have a Write-Protect (WP) pin, the PS SD controller SD_WP signal (MIO[44]) must be pulled up to the 3.3V rail to choose Write Protect via JP2. When JP2 is not populated, SD_WP is grounded via R40 on the UltraZed-EV Carrier Card.
– JP2 WP Jumper used to allow Write Protect emulation for microSD cards if needed. The default position for this jumper is Not Placed, thereby disabling Write Protect function.
– The interface is routed at 50 ohms single ended.
Figure 15 – SD Card interface
CC Net Name: J4 Signal Name: JX3 Pin #: MIO_44 SD_WP B22 MIO_45 SD_CD A23 MIO_46 SD_D0 B24 MIO_47 SD_D1 A25 MIO_48 SD_D2 B26 MIO_49 SD_D3 A27 MIO_50 SD_CMD B28 MIO_51 SD_CLK A29
Table 11: PS microSD card table
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2.9 PS User LED – D25 A red PS user LED is provided on the carrier. It is an active high LED and buffered with a NPN BJT. This LED is connected to the MIO[26] JX3.D21 pin and operated at 3.3V I/O.
Figure 16 – PS User LED
2.10 PL User Switches – Slide DIP & Push Buttons – SW1-SW5 The Carrier Card has 12 PL user switches. Four pushbutton switches SW1-SW4, and an 8 pin DIP slide switch, SW5.
– SW1 – SW4 pushbutton switches are normally open when not depressed and are pulled low via RP1, a 10K resistor pack. When SW1 – SW4 are depressed, they provide a 1.8V signal via 240 ohm pull-up resistors. 0.1uF capacitors are placed to minimize switch bounce noise.
– When slid to the “ON” position, SW5 outputs are pulled high to a logic level of +1.8V via a 240 ohm current limiting resistor pack. When in the OFF position (open), SW5 outputs are pulled low via a 4.7K resistor pack.
Figure 17 – PL User Push Button switches
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Figure 18 – PL User Slide switches
CC Net Name: JX1 Pin #: HP_DP_18_P B19 HP_DP_18_N B20 HP_DP_19_P A18 HP_DP_19_N A19 HP_SE_00 B45 HP_SE_01 B46 HP_SE_02 B48 HP_SE_03 B49 HP_SE_04 A44 HP_SE_05 A45 HP_SE_06 A47 HP_SE_07 A48
Table 12: PL User Switch Table
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2.11 PL User LEDs – D17:D24 The UltraZed-EV Carrier Card provides 8 PL user LEDs. These active high LEDs are connected to a HP bank via JX1 connector and operated at 1.8V I/O. These LEDs are buffered with NPN BJTs to minimize the current sourced by the FPGA.
Figure 19 – PL User LEDs
CC Net Name: JX1 Pin #:
HP_DP_20_P D22 HP_DP_20_N D23 HP_DP_21_P C21 HP_DP_21_N C22 HP_DP_22_P B22 HP_DP_22_N B23 HP_DP_47_P A41 HP_DP_47_N A42
Table 13: PL User LEDs
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2.12 PL PMOD Headers – JA1 & JA2 PL-PMODs The UltraZed-EV Carrier Card provides 2 PL PMOD headers with dual-PMOD connections. The PMOD interface operates at 3.3V. The signals reference Banks 47 and Bank 48 on the HD signals. These banks are operated at 3.3V on the carrier. These signals are routed as single-ended signals with a 50 ohms impedance. Decoupling capacitors to be placed as close as possible to the power pins.
Figure 20 – PL PMODs
CC Net Name: JX2 Pin #: PMOD PIN # HD_SE_00_P D2 1 HD_SE_00_N D3 2 HD_SE_01_P C3 3 HD_SE_01_N C4 4 HD_SE_02_P B2 7 HD_SE_02_N B3 8 HD_SE_03_P A3 9 HD_SE_03_N A4 10 HD_SE_04_GC_P D5 1 HD_SE_04_GC_N D6 2 HD_SE_05_GC_P C6 3 HD_SE_05_GC_N C7 4 HD_SE_06_GC_P B5 7 HD_SE_06_GC_N B6 8 HD_SE_07_GC_P A6 9 HD_SE_07_GC_N A7 10
Table 14: PL PMOD pin table
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2.13 PCIe Gen2 x1 Root Port – J14 The UltraZed-EV Carrier Card uses the PS GTR[0] transceiver for the PCIe x1 Root Port interface. The GTR_REFCLK[0] of the UltraZed-EV SOM is connected to the IDT clock generator on the Carrier Card as shown in the following figure. The PCIe Root Port connector reset (PERST#) will be connected to the PS MIO[31] of the UltraZed-EV SOM JX3 connector. Refer to the programmable clock section of this document for more information.
– The +12V, 500mA rail is provided by the +VIN 12V power supply input. – The +3.3V, 3.0A rail is provided by U19, IR38063 PMIC. – GTR_TX0_P/N signals have a 0.1uF AC coupling capacitors. – Clock AC coupling capacitors are placed on the SOM. – The PCIe rails require: +12V @ 500 mA and +3.3V at 3.0 Amps.
UltraZed-EV SOM Slot
JX3
PCIe x1 Root Port Connector
REFCLK_P
PET0P/NPET0P/NPERST#
GTR_TX0_P/NGTR_RX0_P/N
MIO[31]GTR_REFCLK[0]
Clock Generator(IDT 5P49V5935)
PCIe(100MHz)
33
335050
REFCLK_NClock Generator(IDT 8T49N241)
Q0
nQ0
Figure 21 – PCIe Gen2 x1 Root Port block diagram
CC Net Name: JX3 Pin #:
GTR_TX0_P B6 GTR_TX0_N B7 GTR_RX0_P A8 GTR_RX0_N A9 GTR_REFCLK0_P A12 GTR_REFCLK0_N A13 PERST_N C24 PCIe_WAKE_N D8 PCIe_PRSNT_N D9
Table 15: PCIe Gen2 x1 Root Port table
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Figure 22 – PCIe Gen2 x1 Root Port connector
2.14 HDMI Input & Output interfaces – J9 & J10 The Carrier Card features two HDMI interfaces, HDMI_IN and HDMI_OUT. Each interface uses a vertical HDMI connector, TE Part number 2007435-1. The HDMI output is provided on a TE Connectivity 1888811-1. The HDMI_OUT circuit uses a SN65DP159RGZ IC for dual mode DisplayPort to transition-minimized differential signal (TMDS) re-timer functions, supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b and 2.0 output signals. This IC also supports dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel.
– AC coupling capacitors used on each interface. – U9, a TI SN65DP159RGZR TMDS to HDMI level shifter and re-timer IC is used for adaptive and
fixed signal equalization and clock recovery. The device is configurable via the HDMI_CTL I2C bus and supports data rates up to 6 Gb/s per lane to support Ultra HD Ultra HD (4K x 2K / 60 Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 x 1080 / 60 Hz). This IC can automatically configure itself as a re-driver at all data rates.
– U8, (HDMI_OUT circuit), a TPD12S016 HDMI Companion IC is used for I2C level shifting (including internal I2C pull-up resistors), ESD protection and 55mA current limit 5V_OUT load switch.
– U10, M24C64 8KB EEPROM used for HDMI EDID. – U11, (HDMI_IN circuit), a TPD12S016 HDMI Companion IC is used for I2C level shifting
(including internal I2C pull-up resistors), and ESD protection. The 5V_OUT load switch function is not used as this is a receiver.
– The HDMI RX signals are pull-up via a +3.3V, 1.5A filter array consisting of FB7, 49.9 ohm resistor and L1-L8 prior to AC coupling to the SOM.
– ESD diode arrays D6 & D7 used to protect HDMI_OUT interface signals. – ESD diode arrays D8 & D9 used to protect HDMI_IN interface signals.
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The below figures and table detail the interfaces. For further information, please reference Xilinx’s ZCU102 User Guide, UG1182.
UltraZed-EV SOM Slot
HDMI_TX[0:2]_P/N
TMDS Driver
TMDS Termination
HDMI_IN_CLKP/N
HDMI_I2C_SRC
HDMI_I2C_SNK
HDMI_I2C_CTL
IDT Clock Generator
(IDT 8T49N241)
JX1
HDMI_TX_EN, HDMI_TX_CEC, HDMI_TX_HPD
HDMI_RX_CEC, HDMI_RX_HPD
HDMI RX Power Detect
HDMI_RX_PWR_DET
JX2
GTH[0:2]_TX_P/N
HP I/O (2)
HD I/O (2)
HD I/O (3)
HD I/O (2)
HD I/O (2)
HD I/O (2)
HD I/O
GTH[0:2]_RX_P/N HDMI_RX[0:2]_P/N
GTH_REFCLK[1]_P/NHDMI_RX_CLKP/N
GTH_REFCLK[0]_P/NHDMI_TX_CLKP/N
HDMI Out Connector
HDMI In Connector
Figure 23 – HDMI IN/OUT block diagram
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Figure 24 – HDMI OUT re-timer IC and signals
Figure 25 – HDMI OUT I2C level shifting, EDID EEPROM and interface J9
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Figure 26 – HDMI_IN I2C interface J10
SOM Net Name: CC Net Name or Function: JX2 Pin #:
HP_DP_23_P HDMI_IN_CLK_P JX1.A21 HP_DP_23_N HDMI_IN_CLK_N JX1.A22 GTH0_TX_P HDMI_TX0_P D20 GTH0_TX _N HDMI_TX0_N D21 GTH1_TX _P HDMI_TX1_P B20 GTH1_TX _N HDMI_TX1_N B21 GTH2_TX _P HDMI_TX2_P D23 GTH2_TX _N HDMI_TX2_N D24 HD_SE_17_GC_P HDMI_TX_SRC_SDA C15 HD_SE_17_GC_N HDMI_TX_SRC_SCL C16 HD_SE_13_P HDMI_TX_EN C12 HD_SE_13_N HDMI_TX_CEC C13 HD_SE_14_P HDMI_TX_HPD B11 HD_SE_18_GC_P HDMI_CTL_SDA B14 HD_SE_18_GC_N HDMI_CTL_SCL B15 HD_SE_19_GC_P HDMI_RX_SNK_SDA A15 HD_SE_19_GC_N HDMI_RX_SNK_SCL A16 HD_SE_14_N HDMI_RX_CEC_SINK B12 HD_SE_15_P HDMI_RX_HPD A12 HD_SE_15_N HDMI_PWR_DET A13 GTH0_RX _P HDMI_RX0_P C21 GTH0_RX _N HDMI_RX0_N C22 GTH1_RX _P HDMI_RX1_P A21
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GTH1_RX _N HDMI_RX1_N A22 GTH2_RX _P HDMI_RX2_P C24 GTH2_RX _N HDMI_RX2_N C25 GTH_REFCLK1_P HDMI_RXCLK_P C27 GTH_REFCLK1_N HDMI_RXCLK_N C28 GTH_REFCLK0_P HDMI_TXCLK_P D26 GTH_REFCLK0_N HDMI_TXCLK_N D27
Table 16: HDMI Input & Output pinout table
2.15 PL 3G-SDI Transmit & Receive Interfaces – J11-J13 The UltraZed-EV Carrier Card has a 3G-SDI In (receive) and Out (transmit) interface to support broadcast video as shown in the following figure. A Microchip EQCO30T5.2 is used for the cable driver (transmitter) and a Microchip EQCO30R5.D is used for the cable equalizer (receiver). Two Samtec right angle BNC connectors (Part Number BNC7T-J-P-HN-RA-BH1) are used to provide SDI video out interface. A single BNC connector is used for the SDI video input.
The 3G-SDI interface requires specific reference clock input requirements. The GTH reference clock input (250 MHz, 3.3V, LVDS) for the SDI interface is provided by channel 2 of U6, the IDT 8TN49N241-048 programmable clock generator.
SDI Out BNC
ConnectorUltraZed-EV SOM Slot JX2
GTH[3]_TX_P/NCable Driver
Microchip EQCO30T5.2
SDI In BNC
Connector
Cable EqualizerMicrochip
EQCO30R5.DGTH[3]_RX_P/N
SDI_P/N SDO_P/N
SDO_P/N SDI_P/N
Figure 27 – 3G-SDI interface block diagram
– 250 MHz, 3.3V, LVDS GTH reference clock input – 2x 75 ohm GTH[3]_TX_P/N to BNCs for SDI TX. 75 ohm to ground, not trace to trace. AC
coupled and has a 25 ohm drive resistor on each line. – 1x 75 ohm GTH[3]_RX_P/N from BNCs for SDI RX. 75 ohm to ground, not trace to trace.
AC coupled. – GTH pin routing is 100 ohm differential per the Microchip datasheets. Zynq has an internal
100 ohm termination resistor.
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Figure 28 – 3G-SDI Out (transmit) interface
Figure 29 – 3G-SDI In (receive) interface
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Figure 30 – 3G-SDI OUT mode select jumpers
Jumper Number: Jumper Position: Mode select: JP3 On - default Enable – transmit capable JP3 Off Disable – transmit disabled JP4 On SD Operation JP4 Off - default HD/3G operation
Table 17: 3G-SDI OUT Mode Select jumpers
CC Net Name: JX2 Pin #:
GTH3_TX_P B23 GTH3_TX_N B24 GTH3_RX_P A23 GTH3_RX_N A25
Table 18: 3G-SDI pinout table
2.16 PL Dual SFP+ Interfaces – P3 & P4 The UltraZed-EV Carrier Card has two small form factor pluggable (SFP+) 2x2 quad connector interfaces as shown in the following figure. These SFP+ interfaces can accept SFP and SFP+ modules and can be used to implement 1G/10G Ethernet as well as a host of other high-speed interfaces.
– Rate select jumper plugs: JP5 & JP7 for SFP+ 1 interface. – Rate select jumper plugs: JP8 & JP10 for SFP+ 2 interface. – TX Laser enable/disable jumpers: JP6 (SFP+ 1) & JP9 (SFP+ 2) – D10 & D11 provide a loss of signal (LOS) indicator. Each LED is silkscreend with “LINK” next
to it. When the LED is on, the LOS signal is low, indicating there is a valid link. When off there is not a link which indicates a received optical power below receiver sensitivity.
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SFP+ Connector
UltraZed-EV SOM Slot JX2
SFP1_TX_P/N, SFP1_RX_P/NTX_DISABLE_1
RX_LOS_1I2C1
TX_DISABLE_2RX_LOS_2
I2C2
HD I/OHD I/O
HD I/OHD I/O
GTH[4]
GTH[5]
HD I/O (2)
HD I/O (2)
SFP2_TX_P/N, SFP2_RX_P/N
SFP+ Connector
Figure 31 – Dual SFP+ block diagram
Figure 32 – SFP+ 1 interface
Figure 33 – SFP+ 2 interface
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Figure 34 – SFP+ rate select jumpers
Figure 35 – SFP+ Laser (transmit) select jumpers
Jumper Number: Signal Name: Jumper Position: Mode Selected: JP5 Rate1 Select 0 (RX) On 2.125 or 4.25 Gb/s JP5 Rate1 Select 0 (RX) Off - default 8.5 Gb/s JP7 Rate1 Select 1 (TX) On 2.125 or 4.25 Gb/s JP7 Rate1 Select 1 (TX) Off - default 8.5 Gb/s JP6 On – default TX Laser enabled (on) JP6 Off TX Laser disabled (off) JP8 Rate2 Select 0 (RX) On 2.125 or 4.25 Gb/s JP8 Rate2 Select 0 (RX) Off - default 8.5 Gb/s JP10 Rate2 Select 1 (TX) On 2.125 or 4.25 Gb/s JP10 Rate2 Select 1 (TX) Off - default 8.5 Gb/s JP9 On – default TX Laser enabled (on) JP9 Off TX Laser disabled (off)
Table 19: SFP+ Mode Select jumpers
Page 36
SOM Net Name: CC Net Name/Function: JX2 Pin #:
GTH4_TX_P GTH4_TX_P B26 GTH4_TX_N GTH4_TX_N B27 GTH4_RX_P GTH4_RX_P A27 GTH4_RX_N GTH4_RX_N A28 HD_SE_09_P SFP1_TX_DIS C9 HD_SE_09_N LOS1 C10 HD_SE_10_P SFP1_SDA B8 HD_SE_10_N SFP1_SCL B9 GTH5_TX_P GTH5_TX_P D29 GTH5_TX_N GTH5_TX_N D30 GTH5_RX_P GTH5_RX_P C30 GTH5_RX_N GTH5_RX_N C31 HD_SE_11_P SFP2_TX_DIS A9 HD_SE_11_N LOS2 A10 HD_SE_12_P SFP2_SDA D11 HD_SE_12_N SFP2_SCL D12
Table 20: SFP+ 1 & 2 pinout table
2.17 PL FMC HPC Slot Interface – JX4 The UltraZed-EV Carrier Card provides an FMC High Pin Count (HPC) slot. The FMC signals are connected to the UltraZed-EV SOM JX1/JX2 connectors as shown in the following figures. The signal grouping and bank connections are chosen to allow the most compatibility with off the shelf FMCs in the market.
– The power to the pins are as follows: 12V at 1A, 3.3V at 3A, and 1.8V (Fixed VADJ) at 4A. – JP18, JP19 Global Address Select jumpers allow the user to change the interface’s address. The
default address is 0x00. – D12 LED turns on when PG_C2M is high, indicating Power Good from Carrier to Mezzanine. – JP11 jumpers VIO_B_M2C signal, JX4I.J39 to +1.8V when connected. By default this jumper is
not placed.
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UltraZed-EV SOM Slot
JX1
FMC HPC Connector
LA[02:13]_P/N
CLK[0]_M2C_P/N
GA[0:1]
TRST_LPRSTN_M2C_L
LA00_P/N_CCLA01_P/N_CC
LA17_P/N_CCLA18_P/N_CC
VADJ
CLK[1]_M2C_P/N
LA[19:26]_P/N
HP_DP_12_GC_P/NHP_DP_13_GC_P/N
HP_DP_32_GC_P/N
HP_DP_14_GC_P/N
HP_DP_33_GC_P/N
HP_DP_[00:11]_P/N
HP_DP_[24:31]_P/N
HP_DP_34_GC_P/N
SDA, SCL
VREF_A_M2CNC
JX2 HD I/OHD I/O
1.8V
3P3V, 3P3VAUX3.3V
12P0V12V
PG_C2MPG_C2M
PG_M2C3.3V
GA[0:1]
JTAG InterfaceJTAG
RES1
LA[14:16]_P/NHP_DP_[15:17]_P/N
JX2
DP[0:7]_C2M_P/N GTH[8:15]_TX_P/NDP[0:7]_M2C_P/N GTH[8:15]_RX_P/NGBTCLK0_M2C_P/N GTH_REFCLK[4]_P/NGBTCLK1_M2C_P/N GTH_REFCLK[6]_P/N
LA[27:33]_P/NHP_DP_[35:41]_P/N
HD I/O (2)
Figure 36 – FMC HPC block diagram
Figure 37 – FMC HPC JX4A – JX4D
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Figure 38 – FMC HPC JX4E, F, I
Page 39
Figure 39 – FMC HPC JX4J, G, H
Figure 40 – FMC HPC Pullups, GA Select, LED
Page 40
SOM Net Name: CC Net Name/Function: JX2 Pin #: HP_DP_00_P FMC_LA_02_P D5 HP_DP_00_N FMC_LA_02_N D6 HP_DP_01_P FMC_LA_03_P C4 HP_DP_01_N FMC_LA_03_N C5 HP_DP_02_P FMC_LA_04_P B5 HP_DP_02_N FMC_LA_04_N B6 HP_DP_03_P FMC_LA_05_P A4 HP_DP_03_N FMC_LA_05_N A5 HP_DP_04_P FMC_LA_06_P D8 HP_DP_04_N FMC_LA_06_N D9 HP_DP_05_P FMC_LA_07_P C7 HP_DP_05_N FMC_LA_07_N C8 HP_DP_06_P FMC_LA_08_P B8 HP_DP_06_N FMC_LA_08_N B9 HP_DP_07_P FMC_LA_09_P A7 HP_DP_07_N FMC_LA_09_N A8 HP_DP_08_P FMC_LA_10_P D11 HP_DP_08_N FMC_LA_10_N D12 HP_DP_09_P FMC_LA_11_P C10 HP_DP_09_N FMC_LA_11_N C11 HP_DP_10_P FMC_LA_12_P B11 HP_DP_10_N FMC_LA_12_N B12 HP_DP_11_P FMC_LA_13_P A10 HP_DP_11_N FMC_LA_13_N A11 HP_DP_GC_15_N FMC_LA_14_N A14 HP_DP_GC_15_P FMC_LA_14_P A15 HP_DP_16_N FMC_LA_15_N D19 HP_DP_16_P FMC_LA_15_P D20 HP_DP_17_N FMC_LA_16_N C18 HP_DP_17_P FMC_LA_16_P C19 HP_DP_12_GC_P FMC_LA_00_P D15 HP_DP_12_GC_N FMC_LA_00_N D16 HP_DP_13_GC_P FMC_LA_01_P C14 HP_DP_13_GC_N FMC_LA_01_N C15 HP_DP_32_GC_P FMC_LA_17_P_CC D32 HP_DP_32_GC_N FMC_LA_17_N_CC D33 HP_DP_33_GC_P FMC_LA_18_P_CC C31 HP_DP_33_GC_N FMC_LA_18_N_CC C32 HP_DP_24_P FMC_LA_19_P D25 HP_DP_24_N FMC_LA_19_N D26 HP_DP_25_P FMC_LA_20_P C24 HP_DP_25_N FMC_LA_20_N C25
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HP_DP_26_P FMC_LA_21_P B25 HP_DP_26_N FMC_LA_21_N B26 HP_DP_27_P FMC_LA_22_P A24 HP_DP_27_N FMC_LA_22_N A25 HP_DP_28_P FMC_LA_23_P D28 HP_DP_28_N FMC_LA_23_N D29 HP_DP_29_P FMC_LA_24_P C27 HP_DP_29_N FMC_LA_24_N C28 HP_DP_30_P FMC_LA_25_P B28 HP_DP_30_N FMC_LA_25_N B29 HP_DP_31_P FMC_LA_26_P A27 HP_DP_31_N FMC_LA_26_N A28 HP_DP_35_P FMC_LA_27_P A31 HP_DP_35_N FMC_LA_27_N A32 HP_DP_36_P FMC_LA_28_P D36 HP_DP_36_N FMC_LA_28_N D37 HP_DP_37_P FMC_LA_29_P C35 HP_DP_37_N FMC_LA_29_N C36 HP_DP_38_P FMC_LA_30_P B36 HP_DP_38_N FMC_LA_30_N B37 HP_DP_39_P FMC_LA_31_P A35 HP_DP_39_N FMC_LA_31_N A36 HP_DP_40_P FMC_LA_32_P D39 HP_DP_40_N FMC_LA_32_N D40 HP_DP_41_P FMC_LA_33_P C38 HP_DP_41_N FMC_LA_33_N C39 HP_DP_14_GC_P FMC_CLK0_M2C_P B15 HP_DP_14_GC_N FMC_CLK0_M2C_N B16 HP_DP_34_GC_P FMC_CLK1_M2C_P B32 HP_DP_34_GC_N FMC_CLK1_M2C_N B33 ~ ~ ~ JX2 ~ ~ ~ JX2: GTH8_TX_P FMC_TXDP0_C2M_P D35 GTH8_TX_N FMC_TXDP0_C2M_N D36 GTH9_TX_P FMC_TXDP1_C2M_P B35 GTH9_TX_N FMC_TXDP1_C2M_N B36 GTH10_TX_P FMC_TXDP2_C2M_P D38 GTH10_TX_N FMC_TXDP2_C2M_N D39 GTH11_TX_P FMC_TXDP3_C2M_P B38 GTH11_TX_N FMC_TXDP3_C2M_N B39 GTH12_TX_P FMC_TXDP4_C2M_P B41 GTH12_TX_N FMC_TXDP4_C2M_N B41 GTH13_TX_P FMC_TXDP5_C2M_P D44 GTH13_TX_N FMC_TXDP5_C2M_N D45
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GTH14_TX_P FMC_TXDP6_C2M_P B44 GTH14_TX_N FMC_TXDP6_C2M_N B45 GTH15_TX_P FMC_TXDP7_C2M_P D47 GTH15_TX_N FMC_TXDP7_C2M_N D48 GTH8_RX_P FMC_RXDP0_M2C_P C36 GTH8_RX_N FMC_RXDP0_M2C_N C37 GTH9_RX_P FMC_RXDP1_M2C_P A36 GTH9_RX_N FMC_RXDP1_M2C_N A37 GTH10_RX_P FMC_RXDP2_M2C_P C39 GTH10_RX_N FMC_RXDP2_M2C_N C40 GTH11_RX_P FMC_RXDP3_M2C_P A39 GTH11_RX_N FMC_RXDP3_M2C_N A40 GTH12_RX_P FMC_RXDP4_M2C_P A42 GTH12_RX_N FMC_RXDP4_M2C_N A43 GTH13_RX_P FMC_RXDP5_M2C_P C45 GTH13_RX_N FMC_RXDP5_M2C_N C46 GTH14_RX_P FMC_RXDP6_M2C_P A45 GTH14_RX_N FMC_RXDP6_M2C_N A46 GTH15_RX_P FMC_RXDP7_M2C_P C48 GTH15_RX_N FMC_RXDP7_M2C_N C49 GTH_REFCLK4_P FMC_GBTCLK0_M2C_P D41 GTH_REFCLK4_N FMC_GBTCLK0_M2C_N D42 GTH_REFCLK6_P FMC_GBTCLK1_M2C_P B47 GTH_REFCLK6_N FMC_GBTCLK1_M2C_N B48 HD_SE_22_P FMC_SCL B17 HD_SE_22_N FMC_SDA B18 HD_SE_23_P FMC_PRSTN_M2C_L A18 HD_SE_23_N FMC_TRST_L A19
Table 21: FMC HPC pinout table
2.18 Carrier Card I2C Interface The UltraZed-EV SOM provides a master I2C bus (CC_SDA, CC_SCL, and CC_INT) to the Carrier Card via the JX3 connector to allow software to communicate with all I2C devices on the UltraZed-EV SOM as well as the clock and MAC I2C slave devices on the Carrier Card using a single I2C interface.
The CC_SDA, CC_SCL, and CC_INT pins are pulled up to the 1.8V rail via 1K ohm resistors R46 & R47 on the UltraZed-EV Carrier Card. The CC_INT signal is not used on the carrier and is pulled up via R49 to +1.8V and a test point (TP2) is attached to it for development purposes.
– Carrier Card Master I2C interface devices: – U3, IDT 5P49V5935 clock generator, Clock 1, address 0xD4 primary or 0xD0 (alternate). – U6, IDT 8T49N241-048 clock generator, Clock 2, address 0xD8 – U5, IDT 8T49N241-048 clock 2 configuration EEPROM (24AA025T-I/OT), address 0xA4 – U7, MAC Address device - 24AA025E48-I/OT, address 0xA2
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Figure 41 – I2C CC_INT_N signal and TP2
SOM Net Name: CC Net Name/Function: JX3 Pin #:
CC_SDA CC_SDA C1 CC_SCL CC_SCL A1 CC_INT CC_INT D19
Table 22: Carrier Card master I2C bus connections
2.19 Clock Generators – Clock 1 and Clock 2. The Carrier Card has 2 clock generators to provide the SOM with all necessary interface clocks on-board. Clock 1 is an IDT 5P49V5935B539LTGI and is an Avnet custom programmed part (available for order via the Avnet website). Clock 2 is an IDT 8T49N241-048 and is configured via the on-board EEPROM (U5). Both clocks are on the master I2C bus and can be accessed by the user for configuration purposes. The following sections provide further detail on each clock.
UltraZed-EV SOM Slot
JX2
GTH_REFCLK[3]
GTH_REFCLK[2]
GTH_REFCLK[1]
GTH_REFCLK[0]Q3 (LVDS)
Q2 (LVDS)
Q1 (LVDS)
Q0 (HCSL)
SDA/SCL
HDMI_RX_CLK (From HDMI In)
HDMI_TX_CLK
SDI_CLK
GTH_REFCLK[7]
GTH_REFCLK[6]
GTH_REFCLK[5]
GTH_REFCLK[4]FMC_GBTCLK0
FMC_GBTCLK1
JX3
User Clock SMA
Connectors
User Clock SMA
Connectors
GTR_REFCLK[0]
PCIe x1 Root Port Connector
SDA/SCL
GTR_REFCLK[1]
GTR_REFCLK[2]
GTR_REFCLK[3]
OUT1 (LVDS)
OUT2 (LVDS)
OUT3 (LVDS)
OUT4 (LVDS)
PCIe (100MHz)
SATA (125MHz)
USB3.0 (52MHz)
DisplayPort (27MHz)
CC_SDA/SCL
IDT 8T49N241
IDT 5P49V5935
100MHz
Microchip I2C EEPROM (2Kb)
(24AA025T-I/OT)
OSCI
OSCO
38.88 MHz
Figure 42 – UltraZed-EV Carrier Card clock diagram
Page 44
2.20 Clock Generator 1 – U3, IDT 5P49V5935B539LTGI The Carrier Card has a pre-programmed IDT 5P49V5935B539LTGI synthesizer on board. This clock IC generates the necessary LVDS clocks for the interfaces listed below. This part contains an internal 25 MHz crystal clock source which eliminates the need for an external clock. The part is capable of providing multiple clock frequencies, output types, spread spectrum, phase shift control and slew rate control.
The IDT 5P49V5935B539LTGI is a custom part number with the output frequencies pre-programmed into the device via an OTP register. The device runs at 1.8V. In the default configuration (Mode 0), the clock generates the following frequencies on power up.
Default U3 configuration:
Default Address: 0xD4. Alternate address: 0xD0
– Mode 0 default – 1.8V power – Spread Spectrum: off – Reference clock: 25 MHz internal – Phase Shift: 0 degrees – Output type: LVDS – Slew Rate: set to 1.0x
Default (Mode 0) output frequencies:
– Output 0 – Used for configuration only. – Output 1 – 100MHz, PCIe, JX3 GTR_REFCLK[0] – Output 2 – 125MHz, SATA, JX3 GTR_REFCLK[1] – Output 3 – 52 MHz, USB 3.0, JX3 GTR_REFCLK[2] – Output 4 – 27MHz, Display Port, JX3 GTR_REFCLK[3] – The IDT 5P49V5935B539LTGI is a custom part number with the output frequencies pre-
programmed into the device via an OTP register.
Figure 43 – U3, Clock 1, IDT 5P49V5935B539LTGI GTR Clock Synthesizer
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SOM Net Name: Interface Function: JX3 Pin #: GTR_REFCLK0_P PCIe 100 MHz A12 GTR_REFCLK0_N PCIe 100 MHz A13 GTR_REFCLK1_P SATA 125 MHz C12 GTR_REFCLK1_N SATA 125 MHz C13 GTR_REFCLK2_P USB 3.0, 52 MHz B10 GTR_REFCLK2_N USB 3.0, 52 MHz B11 GTR_REFCLK3_P DPORT, 27 MHz D10 GTR_REFCLK3_N DPORT, 27 MHz D11
Table 23: U3 Clock 1 output connections
2.20.1 Clock Configuration connectors JP1, JP16, JP17
U3 clock has two methods of configuration: hardware and software. For hardware operation it is configured via JP1, JP16, and JP17. These jumpers select one of four pre-programmed OTP configuration files during power up. See Table 24: U3 Clock 1 boot configuration table for the other jumper configurable frequencies.
To configure using software, the device must be accessed via the I2C bus and configured each time the board is powered on.
– Mode 0 is the default frequency selection when the board is manufactured. Mode 0 jumper positions are as follows: JP1, JP16 and JP17 not placed. The IDT device has weak internal pull-down resistors on these pins.
– I2C software configuration mode: the user can configure the IDT part using the I2C bus. To
configure the IDT part for different frequencies, JP16, JP17 jumpers must be placed at positions 2 – 3 and jumper JP1 removed.
Figure 44 – U3 Clock Synthesizer configuration jumpers
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Parameter: Configuration 0: Configuration 1: Configuration 2: Configuration 3: Units: Input (Default Config) 25 25 25 MHz Output 0 25 25 25 25 MHz Output 1 100 100 100 100 MHz Output 2 125 125 125 125 MHz Output 3 52 100 50 26 MHz Output 4 27 27 27 27 MHz
Table 24: U3 Clock 1 boot configuration table
NOTE: Although, the IDT 5P49V5935B539LTGI device is shipped with the above pre-programmed frequencies (in on-chip OTP Flash), jumpers JP16, JP17 and JP1 can be used to hardware configure the device as in the above table. Additionally, the Carrier Card’s master I2C interface (CC_SDA and CC_SCL) can be used to reconfigure the device with different frequencies, if needed.
2.21 Clock Generator 2 – U6, IDT 8T49N241-048NLGI The IDT 8T49N241 device is chosen for its flexibility and jitter specifications. This device meets the GTH reference clock input jitter requirements and its internal fractional dividers allow just about any frequency to be specified for a given output independent of the other outputs. This helps in meeting the clock input requirements for the HDMI, 3G-SDI, and PCIe interfaces. The reads its configuration data from an external EEPROM, U5, Microchip 24AA025T-I/OT.
Default U6 configuration:
– U6 default address is 0xD8, configurable through JT1 and JT2 – Reads configuration memory at address 0xA4 – Device’s Vccore and Vanalog at 2.5V. – VCCCS at 1.8V to allow I2C master bus compliance – Default output level set to 3.3V. – Reference clock: 25 MHz internal – Phase Shift: 0 degrees – Output type: Multiple – Slew Rate: set to 1.0x
Default output frequencies:
– Output 0 – 100 MHz, HCSL, 3.3V, PCIe_REFCLK to PCIe port connector J14 with 33 ohm series termination resistors.
– Output 1 – 148.5 MHz, LVDS, 3.3V, AUX/Loopback, JX2 GTH_REFCLK[5] – Output 2 – 250 MHz, LVDS, 3.3V, 3G-SDI, JX2 GTH_REFCLK[2] – Output 3 – 148.5 MHz, LVDS, 3.3V, HDMI, JX2 GTH_REFCLK[0]
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Figure 45 – U6 Clock 2 Synthesizer circuit
SOM Net Name: CC Net Name or Function: JX2 Pin #:
N/A PCIe 100 MHz N/A N/A PCIe 100 MHz N/A GTH_REFCLK5_P GTH_REFCLK5_P C42 GTH_REFCLK5_N GTH_REFCLK5_N C43 GTH_REFCLK2_P GTH_REFCLK2_P B32 GTH_REFCLK2_N GTH_REFCLK2_N B33 GTH_REFCLK0_P GTH_REFCLK0_P D26 GTH_REFCLK0_N GTH_REFCLK0_N D27
Table 25: U6 Clock 2 output connections
– Note: The 8T49N241 Q1 can be used for testing the FMC GTH transceivers in loopback mode. The Q1 along with the User SMA clock connections as shown provide maximum flexibility in a single clock source driving multiple GTH quads.
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Figure 46 – Clock 2 configuration EEPROM and Jumpers
– U5’s address can be user configured via JT3 and JT4 (0402 SMT resistor pads). Default resistor positions are: JT3 1-2 (EE_A1 1.8V) and JT4 to 1-2 (EE_A0 low). The default address is set to 0xA2.
– U6’s address can be user configured via JT1 and JT2 (0402 SMT resistor pads). Default resistor positions are: JT1 1-2 (CLK_A0 low) and JT2 1-2 (CLK_A1 low). The default address is set to 0xD8.
Figure 47 – Clock 2 Test Header
– Clock 2 has a non-fitted 100 mil pitch, 2x6 12 pin connector to allow user’s access to the device for development purposes.
–
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2.22 Clock Input – GTH REFCLKs via SMAs – J1 to J4 A pair of Molex SMA Connectors, Part number: 73251-1350, are placed to allow user clock inputs to the SOM. These clocks attach to the GTH_REFCLK[3] and GTH_REFCLK[7].
– SMA Pair 1: JX2, GTH_REFCLK[3] – SMA Pair 2: JX3, GTH_REFCLK[7]
Figure 48 – User SMA Clock connectors
2.23 MAC ID Device - U7, 24AA025E48-I/OT The UltraZed-EV Carrier Card has a 1.8V MicroChip 24AA025E48T-I/OT I2C MAC Address device utilizing EUI-48™. This device is connected to the master I2C bus on the Carrier Card. The address can be configured via JT5 and JT6 (0402 SMT resistor pads). The default position is 4.7K ohm resistors placed at locations 2 – 3, yielding a default address set of 0xA2.
Figure 49 – User SMA Clock connectors
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2.24 SOM Reset input – SW6 The UltraZed-EV Carrier Card has a push switch to generate the active low SOM_RESET_IN_N signal. This signal can also be driven by the PC4 JTAG Header (JTAG_INIT) pin and the GPIO2 port on the SMT2 module through zero ohm resistors. This signal can be used to reset the MPSoC device as well as all other devices on the UltraZed-EV SOM via the JX1 connector. The SOM_RESET_IN_N is an active low signal and when not active is pulled up to +1.8V on the SOM.
Figure 50 – SOM Reset Push button, SW6
SOM Net Name: CC Net Name: JX1 Pin #:
SOM_RESET_IN_N SOM_RESET_IN_N A2
Table 26: SOM Reset pin connection
2.25 Carrier Card Reset input – from SOM The UltraZed-EV SOM provides an active low reset signal to the Carrier Card (CC_RESET_OUT_N) via JX1 connector. The signal is driven from an open drain circuit on the SOM and therefore does not require voltage isolation. This signal resets U6, the IDT GTH Clock and also turns on a red LED indicator. This signal is pulled up to the carrier’s VCCCS 1.8V rail using a 10K value resistor.
Figure 51 – D16, SOM RESET input LED indicator
SOM Net Name: CC Net Name: JX1 Pin #:
CC_RESET_OUT_N CC_RESET_OUT_N C46
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Table 27: Carrier Card reset input connection
2.26 JTAG Topology – SMT2, PC4, FMC The UltraZed-EV Carrier Card has a multi-point JTAG bus. The board has a SMT2 USB module, a PC4 header and the FMC interface that are all chained together on the carrier card. Further, a jumper and translator is designed in to allow JTAG FMC access. The FMC JTAG is operated at +3.3V, while the Carrier Card’s JTAG is at 1.8V, thereby the FMC JTAG connection has a signal level translator.
– When using the SMT2 module, the interface only requires a micro USB cable. No other dongles or adapters are needed. However, to support all development environments, including those with debuggers and dongles, a PC4 2x7 header has also been provided.
PC4 Header
Digilent JTAG-SMT2
Module
FMC HPC SlotUltraZed-EV
SOM Slot
TDO
TDI TDI TDOTDI TDO
12
3
TMSTCK
TMS
TCK
TMSTCK
Vdd
Vref
3.3V
1.8V
864
102Vref
1.8V
8
342
9
11
TMSTCK
1.8V
4.7K
1.8V to 3.3VVoltage
Translators
mU
SB
Con
nect
or
14
SOM_RESET_IN_N7
0
Figure 52 – Carrier Card JTAG Topology
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2.26.1 USB-JTAG Module, SMT2, U14
The UltraZed-EV Carrier Card has Digilent USB-JTAG module placed for the UltraZed-EV SOM PL configuration, QSPI Flash and eMMC Flash programming as well as PS software debugging. The UltraZed-EV SOM will have access to the JTAG pins via the UltraZed-EV Carrier Card JX1 connector.
Figure 53 – SMT2 USB-JTAG interface
2.26.2 PC4 JTAG Header, J15 The UltraZed-EV Carrier Card will provide a PC4 JTAG header on the board so that legacy JTAG cables can be connected to the board. The PC4 header VREF pin must be connected to the 1.8V rail on the UltraZed-EV Carrier Card.
Figure 54 – PC4 JTAG interface
2.26.3 FMC2 JTAG Interface – JX4 The UltraZed-EV Carrier Card also contains a FMC JTAG interface. This interface is connected as shown below. Please refer to Figure 52 – Carrier Card JTAG Topology. The below is the 3.3V to 1.8V level translator placed on the data lines.
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Figure 55 – FMC JTAG interface translator
SOM Net Name: CC Net Name: JX1 Pin #:
JTAG_TCK JTAG_TCK D1 JTAG_TMS JTAG_TMS C1 JTAG_TDO JTAG_TDO D2 JTAT_TDI JTAG_TDI C2
Table 28: Carrier Card reset input connection
2.27 LVDS Touch Panel Interface – P2 The UltraZed-EV Carrier Card will provide Avnet LVDS Touch Panel interface. For ease of use, software references and rapid development time, Avnet recommends the following 10 inch touch panel kit: http://picozed.org/product/10-inch-touch-display-kit
– Routed at 100Ω differential. – Routed 50Ω single ended on control/status signals. – Diode D5 is not populated by default. If the target interface’s logic is 1.8V, R15 may be
removed and D5 or a resistor may be placed, as necessary, to allow 1.8V reference to +VCCO_HP_65.
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Figure 56 – LVDS Touch Panel connector, P2
CC Net Name: P2 LVDS signal name: JX1
Pin #: HP_DP_42_P TP_D0_P B39 HP_DP_42_N TP_D0_N B40 HP_DP_43_P TP_D1_P A38 HP_DP_43_N TP_D1_N A39 HP_DP_44_P TP_D2_P D42 HP_DP_44_N TP_D2_N D43 HP_DP_45_P TP_D3_P C41 HP_DP_45_N TP_D3_N C42 HP_DP_46_P TP_CLK_P B42 HP_DP_46_N TP_CLK_N B43 HD_SE_21_P TP_SDA A41 HD_SE_21_N TP_SCL A42 HD_SE_20_N TP_IRQ_N A18
Table 29: LVDS Touch Panel pinout
•
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2.28 LEDs – Power Status – D14, D15, D26-D36 Additional LEDs representing power supply status, reset status, etc…will be added to the board:
– D15, VIN, green – indicates the carrier power supply is on and within 10% nominal output. – D14, PG Module, green – indicates the SOM power supply is on and within 10% nominal output. – 11 LEDs, green, BJT buffered, indicating each voltage rail.
Figure 57 – PG Module and VIN LEDs
Figure 58 – Power Rail LEDs
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2.29 Fan Header – JP14 The carrier card provides a dual position fan header for the SOM’s cooling fan. The default configuration sources +5.0V to the SOM fan. If a 12V fan is used, FB10 and C215 need to be placed and FB11 removed. A ferrite bead and capacitor are used to minimize fan motor noise coupling to the carrier card’s rails. The maximum current for the fan should not exceed 200mA.
Figure 59 – JP14 Fan Header
2.30 Unused PL I/O All unused PL I/O pins will be looped back on the UltraZed-EV Carrier Card PCB design using 0 Ohms resistors for testing.
The UltraZed-EV Carrier Card has access to 16 GTH transceivers (GTH[0:15]) via UltraZed-EV SOM JX2 connector. All but GTH[6:7] are used on the UltraZed-EV Carrier Card. The GTH[6:7] TX pins are looped back to the GTH[6:7] RX pins on the Carrier Card using 0 Ohms resistors for testing.
– GTR_RX3_P and GTR_RX3_N are grounded. – GTH6_RX_P/N tied via 0 ohm resistors to GTH6_TX_P/N – GTH7_RX_P/N tied via 0 ohm resistors to GTH7_TX_P/N
Figure 60 – Loopback resistors
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3 Carrier Card Power The Carrier Card’s power solution is designed to provide power to all of the interfaces/peripherals on the Carrier Card as well as provide power to the appropriate interfaces on the SOM. This section is broken up to define each subsection of power for clarity and ease of design. See the specific interface sections for more detail.
3.1 Power In connector – J18 Due to the number and types of interfaces the UltraZed-EV SOM and Carrier are capable of supporting, the worst case power supply need is approximately ~102 Watts. This exceeds the standard Avnet 60 Watt power supply and therefore necessitated a new power solution to be used.
– The new power supply is capable of sourcing 12V at 10 Amps and has been designed for the Carrier Card and SOM combination. The standard 60W power supply pinout is not compatible with this Carrier Card and will not allow the board to power on.
– The six pin ATX-style connector remains, but the pinout has changed to prevent the 60W power supply from being able to power the system. Pins 2 & 5 are connected instead of pins 1 & 4.
– Removed L1 choke (on prior boards) due to new power supply chosen.
Figure 61 – New power jack pinout
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3.2 Power Switch – SW8 Power Switch SW8 is a CK 1101 slide switch with a contact rating of 6 Amps. While the contact rating is not sufficient for the potential 10 Amps of current, it has been kept in the design due to it’s low cost and availability. In lieu of placing a higher current switch, and to control the in-rush current and voltage ramp on the power supply, a high power Infineon BSC030P03NS3 50 Amp P-Channel MOSFET has been designed in.
– New high power Infineon BSC030P03NS3 50 Amp P-MOSFET as high side switch.
– New low cost in-rush current and voltage ramp control using the P-MOSFET and Low Pass filter consisting of R204 and C174. By default, using the shipped Avnet 120W power supply, C174 is not required to be placed.
Figure 62 – Prior Low Pass Filter used on UZ-EG to control power-on ramp time
Figure 63 – NEW UZ-EV solution to control power-on ramp time, if needed
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3.3 Power Input – dedicated rails The below rails are listed as dedicated because they are independent of the power sequencing required for the SOM. These rails provide power once the board is turned on.
– +VIN 12V using a new pinout method to J18. – U20, +3.3V Primary regulator – powers the LDO regulators on the Infineon PMICs. – U1, +3.3VDP – Display Port regulator, Maxim Semiconductor Max8902. – U17, +USB_VB - +5.0V USB switch, Microchip MIC2544-1YMM.
Figure 64 – U20, +3.3V Primary regulator for PMICs
3.4 Power Monitor interfaces: SYSMON (J21) and VMON J19, J20 The UltraZed-EV SOM SYSMON interface is available on the carrier card. The pins are routed to a 0.1” SIP header for access to the SYSMON interface pins.
– Signals are routed differentially at 100 ohms. – Termination resistors R206 and R207 are placed within 100 mils of J21. – The signals are routed to within 10 mils across both pairs.
Figure 65 – J21, SYSMON Header
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SOM/CC Net Name: JX1 Pin #: SYSMON J21 Pin #:
SYSMON_DX_N C48 1 SYSMON_DX_P C49 2 SYSMON_V_P D50 4 SYSMON_V_N D49 5
Table 30: SYSMON connection table
3.4.1 Power Supply monitor header – J19, J20
Two non-populated dual row 100 mil pitch 8 pin headers are used for measuring the carrier card’s voltage rails. The below figure shows the available voltage monitor points.
Figure 66 – J19, J20 Voltage Monitor Headers
3.5 PMBus Interface – J22 The UltraZed-EV CC and SOM’s Power Management ICs can be accessed by attaching to the PMBus header, J22. This header can be used for monitoring and programming all PMBus voltage regulators on the Carrier Card and SOM. To attach to this interface the customer may use a generic I2C dongle or an Infinion USB005 dongle.
NOTE: After the initial programming of all PMBus voltage regulators, the UltraZed-EV SOM can drive the PMBus in order to control/monitor the PMBus voltage regulators on the UltraZed-EV SOM as well as the Carrier Card for the purpose of power management and/or measurements. The PMBus signals are pulled up to 3.3V on the SOM.
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SOM/CC Net Name: JX1 Pin #: PMBus_SDA B1 PMBus_SCL B2 PMBus_ALERT_N A1
Table 31: PMBUS connection table
Figure 67 – J22 PMIC PMBUS Header
Figure 68 – J22 PMBUS Offpage connections
3.6 Carrier Card Power Supplies The carrier provides power rails for the UltraZed-EV CC interfaces as well as the SOM. 4 Infineon PMICs are used to generate the required power rails. 2 Infineon IRPS5401MTRPBFs for lower current rails and and 2 Infineon IRP38063MTRPBFs for high current >4A rails. These parts are programmed with the necessary files by the Avnet programming center and are orderable.
– All parts are PMBus accessible and therefore user configurable.
– All of the IRPS5401MTRPBF’s used on the CC and SOM use a single programming file and the parts are orderable under a single part number. Please discuss with your Avnet account representative to get the part number.
– Each of the IRPS38063 PMICs have a unique part number assigned to them based on the programming file. Please discuss with your Avnet account representative to get the specific part number.
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– The UltraZed-EV SOM provides voltage sense feedbacks for each rail supplied by the carrier card. Please refer to Xilinx’s ds925 for percent variation on the following power rails when designing the power system for a custom Carrier Card.
3.7 Power Control The UltraZed-EV SOM provides a signal named SOM_PG_OUT signal (3.3V level) that is used by the Carrier Card for PMIC power sequencing. The Carrier Card voltage regulators are not turned ON until the SOM_PG_OUT signal is asserted.
SOM/CC Net Name: JX1 Pin #: SOM_PG_OUT D47
Table 32: SOM_PG_OUT input to Carrier Card
NOTE: In normal operation, the SOM_PG_OUT signal controls the CC’s PMIC enable pins. For this reason a SOM must be placed for the carrier to power up in normal operation. In test mode, the CC board can be powered up by modifying the circuits as described below.
– To power up the board without a SOM, the user can populate JP15 and then place a jumper on the pins. In addition to placing the jumper, the user will have to populate the not-fitted components on each regulator output to provide feedback to the PMICs. See each PMIC section. The CC has a 49.9K weak pull up which turns on the carrier card’s PMICs. While it is recommended a SOM not be placed when this modification is made, the resistor value is high enough to allow the SOM to maintain control of the CC’s SOM_PG_OUT signal.
Figure 69 – JP15 PMIC ON test header
3.8 Infineon IRPS38063MTRPBF PMIC – U18, 0x1B U18 provides a 1.8V high current rail (20 amps max) for the Carrier Card’s main 1.8V power supply. The Infineon IRPS38063MTRPBF PMIC was chosen due to it’s small size, high efficiency, high power and PMBus programmable features. A remote feedback sense line is used at the highest current interface on the board. This technique increases the voltage accuracy over high load conditions. The part has been Avnet programmed for this application.
The IRPS38063 PMIC has been programmed as follows:
– Vout_command: 1.80V – Vout_max: 1.949V – Iout fault: 33 amps max – Frequency: 607 KHz – Transition rate: 0.125mV/us
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– Point of load sense via R288 – Feedback Vout scale: 1.0 – Turn off outputs if PMIC input voltage is less than 9.0V – Turn on outputs if PMIC input voltage is equal or greater than 11.0V – R215 provided for Bode plot measurements if needed. – The address offset, +11, is set by R227, a 7.87K ohm resistor. – The carrier card PMIC I2C address is: 0x1B – The carrier card PMBus address is: 0x4B
Figure 70 – U18, 1.8V High Power PMIC
Figure 71 – U18, 1.8V High Power PMIC load sense
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3.9 Infineon IRPS38063MTRPBF PMIC – U19, 0x1C U19 provides a 3.3V high current rail (20 amps max) for the Carrier Card’s main 3.3V power supply. The Infineon IRPS38063MTRPBF PMIC was chosen due to it’s small size, high efficiency, high power and PMBus programmable features. A remote feedback sense line is used at the highest current interface on the board. This technique increases the voltage accuracy over high load conditions. The part has been Avnet programmed for this application. Note: the feedback scale is set to 0.5 due to the output voltage being greater than 2.5V. This is per Infineon’s recommendations.
The IRPS38063 PMIC has been programmed as follows:
– Vout_command: 3.30V – Vout_max: 3.500V – Iout fault: 33 amps max – Frequency: 607 KHz – Transition rate: 0.125mV/us – Point of load sense via R288 – Feedback Vout scale: 0.5 – Turn off outputs if PMIC input voltage is less than 9.0V – Turn on outputs if PMIC input voltage is equal or greater than 11.0V – R217 provided for Bode plot measurements if needed. – The address offset, +12, is set by R228, a 8.87K ohm resistor. – The carrier card PMIC I2C address is: 0x1C – The carrier card PMBus address is: 0x4C
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Figure 72 – U19, 3.3V High Power PMIC
Figure 73 – U19, 3.3V High Power PMIC load sense
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3.10 Infineon IRPS5401MTRPBF PMIC – U21, 0x19 A five channel, high current programmable PMIC is required to source the SOM with high accuracy rails. The Infineon IRPS5401MTRPBF PMIC was chosen due to it’s small size, high efficiency, and programmable features. This part is on the PMBUS and is accessible via J10, the PMBus header. The part has been factory programmed with 3 selectable output profiles. One profile is used for the carrier card, while the remaining two are used for the SOM.
The IRPS IRPS5401MTRPBF PMIC has been programmed as follows:
– Transition rate: 0.500mV/us – Turn off outputs if PMIC input voltage is less than 9.0V – Turn on outputs if PMIC input voltage is equal or greater than 11.0V – The address offset, +9, is set by R248, a 6.19K ohm resistor. – The carrier card PMIC I2C address is: 0x19 – The carrier card PMBus address is: 0x49
The below table shows device “19’s” IRPS IRPS5401MTRPBF rail programming:
Channel Number:
Programmed Voltage & Current:
Iout_fault limit:
Feedback Scale:
Switching Frequency:
SOM &/or Carrier Card Rail name(s):
CHA 0.85V, 2.0A 3.313A 1.00 1 MHz +MGTRAVCC CHB 1.80V, 2.0A 2.75A 1.00 1 MHz +VCCO_1V8
+VCCO_HP_64 +VCCO_HP_65
CHC 3.30V, 3.0A 4.50A 0.50 1 MHz +3.3V_HD +VCCO_HD_47 +VCCO_HD_48 +VCCO_PSIO_501
CHD 5.0V, 3.0A 4.50A 0.50 1 MHz +5.0V LDO 1.0V, 0.3A 0.652A N/A N/A +MGTRAVTT
Table 33: U21 PMIC Output rails
3.10.1 Power supply net ties There are several rails that are tied together on the carrier card through the use of PCB net ties. PCB net ties are two separate signal planes tied to each through a piece of PCB copper. This technique is used to illustrate schematic/electrical connectivity
– +VCCO_1V8 VCCO_HP_64/65 – +3.3V_HD VCCO_HD_47/48 & VCCO_PSIO_501
NOTE: These rails are not tied together on the SOM. They are not tied together at the SOM because a user may want different I/O voltages on each bank. They are tied together on the carrier card because these are the voltages required for our specific application.
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Figure 74 – Net Ties to attach PMIC rails to VCCO rails.
Figure 75 – U21, 0x19 high power PMIC
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3.10.2 IRPS5401 PMIC Feedback resistors – U21 Feedback resistors are placed on each PMIC output channel. However, these resistors may not be placed, are labeled as “DNP” and are grayed out in the schematic. These parts are removed to allow SOM remote sensing to occur. If the user desires, these components can be placed for power supply evaluation, but should NOT be placed when a SOM is used.
– Resistors listed as DNP can be populated when testing the Carrier Card in stand alone mode. DO NOT CONNECT A SOM TO THE CARRIER when this is implemented!
Figure 76 – PMIC power outputs with DNP feedback components
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3.10.3 IRPS5401 PMIC Power Sense signals – U21 The UltraZed-EV SOM provides low current power sense signals for the below carrier rails. These feedback signals are used to adjust the output voltage for each rail. This method of feedback ensures the load (SOM) is provided stable power during dynamic power loading conditions. This method of sensing also nulls out all current and resistance drops across both boards and connectors.
SOM/CC Net Name: JX3 Pin #: MGTRAVCC_SENSE D20 VCCO_HP_64_SENSE D30 VCCO_HP_65_SENSE C29 VCCO_HD_47 D24 VCCO_HD_48 D28 MGTRAVTT_SENSE C25
Table 34: SOM to U21, 0x19 power rail sense connections
Figure 77 – U21, 0x19 PMIC Power supply sense rail filters
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3.11 Infineon IRPS5401MTRPBF PMIC – U22, 0x1A A five channel, high current programmable PMIC is required to source the SOM with high accuracy rails. The Infineon IRPS5401MTRPBF PMIC was chosen due to it’s small size, high efficiency, and programmable features. This part is on the PMBUS and is accessible via J10, the PMBus header. The part has been factory programmed with 3 selectable output profiles. One profile is used for the carrier card, while the remaining two are used for the SOM.
The IRPS IRPS5401MTRPBF PMIC has been programmed as follows:
– Transition rate: 0.500mV/us – Turn off outputs if PMIC input voltage is less than 9.0V – Turn on outputs if PMIC input voltage is equal or greater than 11.0V – Channel D is not used and therefore turned off. – The address offset, +10, is set by R271, a 6.98K ohm resistor. – The carrier card PMIC I2C address is: 0x1A – The carrier card PMBus address is: 0x4A
The below table shows device “1A’s” IRPS IRPS5401MTRPBF rail programming:
Channel Number:
Programmed Voltage & Current:
Iout_fault limit:
Feedback Scale:
Switching Frequency:
SOM &/or Carrier Card Rail name(s):
CHA 0.90V, 2.0A 3.00A 1.00 1 MHz +MGTAVCC CHB 1.20V, 2.5A 3.75A 1.00 1 MHz +MGTAVTT CHC 1.10V, 2.0A 3.75A 0.50 1 MHz +1.1V CHD N/A N/A N/A N/A N/A LDO 1.8V, 0.5A 0.720A N/A N/A +MGTVCCAUX
Table 35: U22 PMIC Output rails
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Figure 78 – U22, 0x1A high power PMIC
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3.11.1 IRPS5401 PMIC Feedback resistors – U22 Feedback resistors are placed on each PMIC output channel. However, these resistors may not be placed, are labeled as “DNP” and are grayed out in the schematic. These parts are removed to allow SOM remote sensing to occur. If the user desires, these components can be placed for power supply evaluation, but should NOT be placed when a SOM is used.
– Resistors listed as DNP can be populated when testing the Carrier Card in stand-alone mode. DO NOT CONNECT A SOM TO THE CARRIER when this is implemented!
Figure 79 – U22, 0x1A PMIC power outputs with DNP feedback components
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3.11.2 IRPS5401 PMIC Power Sense signals – U22 The UltraZed-EV SOM provides low current power sense signals for the below carrier rails. These feedback signals are used to adjust the output voltage for each rail. This method of feedback ensures the load (SOM) is provided stable power during dynamic power loading conditions. This method of sensing also nulls out all current and resistance drops across both boards and connectors.
SOM/CC Net Name: JX3 Pin #: MGTAVCC_SENSE A24 MGTAVTT_SENSE A28 1V1_SENSE N/A MGTVCCAUX_SENSE B23
Table 36: SOM to U22, 0x1A power rail sense connections
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Figure 80 – Power supply sense rail filters
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Figure 81 – PMIC Interface window via IR PowIRCenter
Power Rail Name: Source, Channel: Volts, Amps: Purpose: JX Pins: +VIN Wall adapter, N/A +12V, 10.0 A Main board power All +VIN pins +3.3VDP U1 LDO, N/A +3.3V, 500 mA Display Port power N/A +3.3V PRIMARY U20 LDO, N/A +3.3V, 1.5 A PMIC core power N/A +5.0V PMIC 0x19, CHD +5.0V, 3.0 A DP LDO, HDMI IC’s N/A +MGTRAVCC PMIC 0x19, CHA +0.85V, 2.0 A SOM VCCIO power JX3: A30, B29, B30 +3.3V_HD, +VCCO_HD47/48, +VCCO_PSIO_501
PMIC 0x19, CHC +3.3V, 3.0 A Main board power, LVDS Touch Panel, Micro SD Card, SOM VCCIO power
JX1: C43, C44, C45, D44, D45, D46 JX3.D18
+VCCO_1V8, +VCCO_HP_64/65
PMIC 0x19, CHB +1.8V, 2.0 A Clocks, MAC ID EEPROM, PBs, JTAGs, SOM VCCIO power
JX1: A3, B3, B4, C3, D3, D4,
+MGTRAVTT PMIC 0x19 LDO +1.8V, 0.3 A SOM VCCIO power JX3 B25, B27 +USB_VB U17, Switch +5.0V, 1.5 A USB interface N/A +PS_VBATT JP3, LR44,
+VCCO_1V8 + <2.0V, < 10mA FPGA key memory JX3.C21
+MGTAVCC PMIC 0x1A, CHA +0.9V, 2.0A SOM VCCIO power JX2: C1, C2, D4, D7, D10, D13
+MGTAVTT PMIC 0x1A, CHB +1.2V, 2.5A SOM VCCIO power JX2: A1, A2, B4, B7, B13
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+1.1V PMIC 0x1A, CHC +1.1V, 2.0A HDMI IC’s N/A
+MGTVCCAUX PMIC 0x1A LDO +1.8V, 0.5A SOM VCCIO power JX2: A5, A8,
+1.8V PMIC 0x1B +1.8V, 20A CC interfaces N/A
+3.3V PMIC 0x1C +3.3V, 20A CC interfaces N/A
GND on JX1 System GND GND CC and SOM A6, A9, A12, A13, A16, A17, A20, A23, A26, A29, A30, A33, A34, A37, A40, B7, B10, B13, B14, B17, B18, B21, B24, C6, C9, C12, C13, C16, C17, C20, C23, C26, C29, C30, C33, C34, C37, C40, C47
GND on JX2 System GND GND CC and SOM A11, A14, A17, A20, A23, A26, A29, A32, A35, A38, A41, A44, A47, A50, B1, B16, B19, B22, B25, B28, B31, B34, B37, B40, B43, B46, B49, B50, C5, C8, C11, C14, C17, C20, C23, C26, C29, C32, C35, C38, C41, C44, C47, C50, D1, D16, D19, D22, D25, D28, D31, D34, D37, D40, D43, D46, D49, D50
GND on JX3 System GND GND CC and SOM A2, A3, A6, A7, A10, A11, A14, A17, A20, A26, B1, B4, B5, B8, B9, B12, B13, B16, B19, C2, C3, C4, C5, C6, C7, C10, C11, C14, C15, C19, D1, D4, D5, D8, D9, D12, D13, D16
Table 37 – Carrier Card power rails
3.12 Display Port Regulator – U1 The Display Port requires a high precision power supply, +3.3VDP. The Maxim Part MAX8902BATA+T creates this rail. Features include:
– Vout is high precision, (<1.5% Vout) & low noise (16uVRMS) – 500mA source in normal operation – 700mA source in short mode – Auto thermal shutdown and protect – POK output – 2mm X 2mm package
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LED D3 is used to indicate the regulator is on. It illuminates when the regulator is within 88% of nominal output voltage.
Figure 82 – U1, +3.3V Display Port regulator
3.13 PS VBATT LR44 Battery – JP13 & BTH-1 The Carrier Card provides two methods of maintaining the SOM’s Zynq device volatile AES decryptor keys when the carrier is turned off. A 1.5V LR44 battery or a customer connection through JP13. Either connection provides power to the SOM’s +PS_VBATT signal via the JX3 pin C21 connector. When the carrier card is turned on, neither method is required as +VCCO_1V8 is diode OR’d with +PS_VBATT signal.
– The +PS_VBATT pin is pulled up via +VCCO_1V8 & D43 when the board is powered on, no battery or external power source needed to maintain decryptor keys.
– Place a LR44 battery to maintain the AES decryption keys on the SOM when board is power off. – Diode D43 and D45 provide back source isolation for +VCCO_1V8 & LR44 battery. – In lieu of placing a LR44 battery, the user may decide to use an external power supply or
battery connected via JP13. In doing so, the input voltage on JP13 MUST NOT EXCEED 2.0 volts otherwise the SOM’s FPGA may be damaged. Diode D44 and resistor R205 are placed to help prevent this, but this is by no means intended to encourage a voltage higher than 2.0V to be applied!
Figure 83 – +PS_VBATT circuit
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3.14 PS VBATT placement LR44 Battery installation instructions: The LR44 battery is required to be installed in a sleeve, part number BHX1-LR44 and firmly inserted into the carrier’s socket. The coin cell’s positive terminal is placed into the opening of the sleeve facing UP.
Figure 84 – Battery & sleeve orientation prior to insertion
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Figure 85 – Final battery placement. Push battery and sleeve back until it clicks.
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3.15 Power Supply Sequencing and Power Modes Sequencing for the power supplies follows the datasheet recommendations for the Zynq UltraScale+ device. The power configuration programmed into the International Rectifier IRPS5401MTRPBF and IR3806MTRPBF devices controls the power supply sequencing. An end-user may utilize the PMBUS on the carrier-card or utilize the Zynq UltraScale+ MPSoC interface to the PMBUS to power down individual rails to implement the different power modes supported by the MPSoC.
Sequencing is needed for board power up, as well as entering and exiting different power modes. There are 3 power domains, PS LP (Processing Subsystem Low Power), PS FP (Processing Subsystem Full Power) and PL (Programmable Logic Power). The PS LP domain shall come up first followed by the PS FP and PL power domains.
PS LP Power Domain Sequence: DS925 (V1.8) Recommended:
VCC_PSINTLP → VCC_PSAUX / VCC_PSADC / VCC_PSPLL → VCCO_PSIO
UltraZed-EV SOM Implementation: VCC_PSINTLP → VCCO_PSIO / VCC_PSPLL → VCCO_PSIO_501 (From Carrier Card)
PS FP Power Domain Sequence: DS925 (V1.8) Recommended:
VCC_PSINTFP / VCC_PSINTFP_DDR → PS_MGTRAVCC / VCC_PSDDR_PLL → PS_MGTRAVTT / VCCO_PSDDR
UltraZed-EV SOM Implementation: VCC_PSINTFP → MGTRAVCC (From Carrier Card) / VCC_PSDDR_PLL (Generated from +3.3V on SOM) → MGTAVTT (From Carrier Card) / VCCO_PSDDR4_504
PL Power Domain Sequence: DS925 (V1.8) Recommended:
VCCINT → VCCINT_IO / VCCBRAM / VCCINT_VCU → VCCAUX / VCCAUX_IO → VCCO_HD_47 / VCCO_HD_48 / VCCO_HP_64 / VCCO_HP_65 / VCCO_HP_66 / MGTAVCC / MGTAVTT / MGTVCCAUX
UltraZed-EV SOM Implementation: VCCINT → VCU_INT → VCCAUX → VCCO_HD_47 (From Carrier Card) / VCCO_HD_48 (From Carrier Card) / VCCO_HP_64 (From Carrier Card) / VCCO_HP_65 (From Carrier Card) / VCCO_HP_66 / MGTAVCC (From Carrier Card) / MGTAVTT (From Carrier Card) / MGTVCCAUX (From Carrier Card)
Entering / Exiting Power Domains: To enter power down modes, the reverse order of start-up should be followed (last supply to come up should be the first to be shut down, etc.). The PL and PS FP domains can be powered down independently and either can be powered down before or after the other. When shutting down power to a domain however, sequencing must be followed in relation to the specific power domain group. Upon repowering these domains, proper sequencing should again be followed.
The following diagrams are indicative of the pre-programmed power-on and power-off sequences that exist on the UltraZed-EV SOM and the UltraZed-EV Carrier Card.
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Figure 86 – UltraZed-EV Carrier Card Power ON sequence diagram example
Figure 87 – UltraZed-EV Carrier Card Power OFF sequence diagram example
0ms 6ms 12ms 18ms 24ms 30ms 36ms 42ms 48ms 54ms 60ms 66ms 72ms 75ms
SOM_PG_OUT
CARRIER GENERATES RAILS
MGTRAVCC
MGTRAVTT
MGTAVCC
MGTAVTT
MGTVCCAUX
VCCO_1V8 (Carrier Card Name)
VCCO_HP_64 (SOM Name)
VCCO_HP_65 (SOM Name)
3.3V_HD (Carrier Card Name)
VCCO_HD_47 (SOM Name)
VCCO_HD_48 (SOM Name)
VCCO_PSIO_501 (SOM Name)
1.1V (Carrier Card Only)
5.0V (Carrier Card Only)
1.8V (Carrier Card Only)
3.3V (Carrier Card Only)
0ms 6ms 12ms 18ms 24ms 30ms 36ms 42ms 48ms 54ms 60ms 66ms 72ms 75ms
SOM_PG_OUT
CARRIER GENERATES RAILS
MGTVCCAUX
MGTRAVTT
5.0V (Carrier Card Only)
1.1V (Carrier Card Only)
3.3V_HD (Carrier Card Name)
VCCO_HD_47 (SOM Name)
VCCO_HD_48 (SOM Name)
VCCO_PSIO_501 (SOM Name)
VCCO_1V8 (Carrier Card Name)
VCCO_HP_64 (SOM Name)
VCCO_HP_65 (SOM Name)
1.8V (Carrier Card Only)
3.3V (Carrier Card Only)
MGTAVTT
MGTAVCC
MGTRAVCC
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Figure 88 – UltraZed-EV Carrier Card actual PMIC timing windows
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4 PCB Information 4.1 PCB Characteristics
The following PCB characteristics define the electrical and physical requirements for the UltraZed-EV SOM.
4.1.1 PCB Electrical Characteristics: The following trace, bus, copper weight and board characteristic impedances must be met. A detailed board stack up will be required prior to board layout to provide trace dimension and separation guidance.
– Material: FR-4 – Thickness: .062” +/- 8% – 12 layers – Copper weight, Nominal: 0.5 oz. on signal layers and 1.0 oz. on Power/GND layers. – Nominal board impedance is 50Ω for single ended signals. – Differential signals 100Ω +/- 5% unless otherwise noted. – Differential 75Ω +/-5% for 3G-SDI signals – USB signals 45Ω single ended, 90Ω differential to the connector, with a 10% tolerance. – Gigabit Ethernet signals 50 Ω single ended, 100Ω differential to the connector, with a 10%
tolerance. – USB 3.0 differential signals 100 Ω. – Board temperature rise not to exceed 20C due to power – No blind or buried VIAs were used to meet interface performance requirements.
4.1.2 PCB Stack Up The following layer stack up will be required to meet the performance objectives:
1 – Signal + Primary Component Side (Top) 2 - GND 3 - Signal 4 - Signal 5 - GND 6 - PWR 7 - PWR 8 - GND 9 - Signal 10 - Signal 11 - GND 12 – Signal + Secondary Component Side (Bottom)
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Figure 89 – UltraZed-EV Carrier Card fabrication layer stackup
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5 UltraZed-EV Carrier Card Mechanical The following figure shows the UltraZed-EV Carrier Card mechanical dimensions. The Carrier Card is in a 7.0” x 8.0” form factor.
Figure 90 – UltraZed-EV Carrier Card Mechanical
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