Ultra Thin HDI Multi-purpose Test Vehicle Definition Stage Project C.B. Katzko, TTM Technologies HDPUG Member Meeting, 2014 June 04 Düren, Germany Hosted.

Ultra Thin HDI Multi-purpose Test Vehicle

Definition Stage ProjectC.B. Katzko, TTM Technologies

HDPUG Member Meeting, 2014 June 04Düren, Germany

Hosted by Isola

© High Density Packaging Users Group, Inc.

Background - IT Market Disruption

• Our “Post PC Era” :• Sales of desktop & laptops declining

• Smartphones & tablets becoming dominant internet user devices

• Cloud Computing and SAAS eroding the packaged software model

• Ultrabooks, hybrids and “modular” PCs replacing traditional PCs

• Commodity servers rivaling OEM brand systems for internet enterprises

• “Internets of Things” = explosion of embedded system modules


Source : Gartner Research 1995 - 2013

1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013

Unit Sales

70.9 80.6 92.9 113.5

134.7

128.1

132.4

168.9

189 218.5

239.4

271.2

302.2

305.9

351 352.8

352.7

316

Growth %

17.8 13.7 15.3 21.7 14.5 -4.6 2.7 10.9 11.8 15.3 9.5 13.4 10.9 1.2 13.8 0.5 -3.5 -10

25

75

125

175

225

275

325

375

-12.5

-7.5

-2.5

2.5

7.5

12.5

17.5

22.5

Worldwide PC Sales

un

its

x m

illio

ns

% c

ha

ng

e -

Yo

Y

Background - User Device Trends

Source : Internet Trends 2014 – Code Conference, Mary Meeker, KPCBPDF Link : http://kpcb.com/InternetTrends

Wealthy nations near saturation, global market lead by emerging nations has room for growth

Tablets on a high growth curve as lower cost “minis” & “phablets” surpass notebook PCs

Background – End Use Trends

Source : Internet Trends 2014 – Code Conference, Mary Meeker, KPCBPDF Link : http://kpcb.com/InternetTrends

Outrank USA on total time, Smartphone & Tablet usage

USA

“Café” not “Internet Café”?

Highest smartphone internet use, e-banking/e-commerce leader in Africa

Age demographics – JP is a poster child of the global trend

Background - Modular Computing

Intel ® NUC Next Unit of Computing

Intel ® NUC Next Unit of ComputingArs Technica – 2014 Jan 06

Remaking the desktop:DIY - add your own DDR3, wireless, SSD or HDD

Open Compute Project“vanity-free” processor sled –OEM/ODMs joining these projects

PCBs - conventional MLB & HDItrending to stacked via BGA

Background – Handhelds


ALV-HDI logic boardpopulated 2 sides

Li-ion Battery

flex PCB camera

flex PCB camera/sensors

flex PCB home button

rigid-flex PCB audio jack, lighting port

integrated display

panel

flex PCBs switches

& sensors

flex PCB video driver

shield

HDI PCB audio/speaker

PoP SoC

PCBs – leading edgeHDI/ALV Flex & Rigid Flex

Source : iFixit http://www.ifixit.com/Teardown/iPhone+5s+Teardown/17383

Background – HDI/ALV Design

• Handheld/wearable electronic packaging:• Design envelope dominated by batteries & displays

• Miniaturized & modularized PCBA design with high flex content

• Extensive use of SoC & MEMs, with SiP, PoP & WCSP packaging

• Low profile CSP, WCSP & microQFN devices, 0.40~0.30mm pitch

• Ultra-thin 8-14 Layer HDI PCB design, current and near term:

• Via in Pad/stacked via ICT with decreasing pad diameter

• Conductor line/space design rules approaching 40/60um

• 2 track routing in 0.40umm pitch devices up to 36x36 BGA

• 25~40um dielectrics

• 250~800um thickness

• Flex & coreless HDI


How does the performance & reliability stack-up?

Background – HDI/ALV Roadmap

BGA Design Rules (microns)

BGA PitchSignal

RoutingInner Line Inner Space Laser Via Inner Pad Outer Pad SM Opening Remarks

0.40mm 1 Track 0.7 - 100 200 225 300 JISSO Roadmap

0.40mm 1 Track 60 65 75 200 200 275 Current Practice

0.40mm 2 Track 40 45 75 180 180 255Next Gen High I/O SoC, requires mSAP

0.30mm 1 Track 50 - 75 150 240 175 JISSO Roadmap

0.30mm 1 Track 50 50 75 200 240 175 Current Practice

0.30mm 2 Track 30 30 75 150 240 175 Forecast, requires mSAP

0.25mm 1 Track 50 50 50 100 - -JISSO Roadmap, requires mSAP

0.15mm 1 Track 25 25 30 75 - -JISSO Roadmap, requires coreless & SAP

Dielectric Thickness (microns)

Min BGASignal

RoutingCore Layer

Build-up Layer

Total Layers Remarks

0.40mm 1 Track 60 60 10 Current Practice STD HDI

0.30mm 1 Track 50 45 10 ~ 12 Current Practice ADV HDI

0.30mm 2 Track 40 40 10 ~ 12 Next Generation ADV HDI

0.25mm 1 Track 40 30 ~ 35 10 ~ 12 Forecast 2015-2016

At limit or beyond subtractive process

Project – Purpose & Objectives

Problem

• Test vehicles for BGA & HDI technology lag by a decade• Do not reflect current design practice & materials

• Falling into dis-use by practitioners in favor of EOL product testing

• Creating a void in up-stream device and materials development

Objective

• Create/validate an open source ALV-HDI test vehicle based on current & near term Smartphone design practice• General purpose test patterns for ALV PCB and assembly level tests

• Reference drop test vehicle for JESD-B22-111 (existing design)

• Smartphone forma factor for JESD-B22-111 validation (new design)

• Run validation tests for proof or concept/design & standardization


Project – Goals & Deliverables

Goals

• Build a collaborative working group handheld product technology within HDP for this and future projects

• Stakeholders from Materials, PCB, Packaging and Assembly

• Establish a suite of basic methods and tools suitable for the general assessment of the technology

• Build & test first generation TV designs for validation

• Deliverables:• Generic, modular, Test Vehicle form factor spec & DFM

guidelines

• General purpose test vehicle & drop test vehicle designs in Gerber

• Demonstrator samples for future reference

• Test data and reports for proof of concept build

Project – TV Design Goals

The TV form factor should have the capability to:

• Scale to smartphone or handheld device form factors, materials sets and production formats typical of the art

• Include as a design technology baseline:• Modularized, based on 50mm x 50mm increments for various

mixes of bare board & assembly TVs

• 0.40mm pitch BGA & 0.30mm pitch WCSP test devices

• 01005 chip passives (low value or zero ohm resistors)

• 40/60um nominal line/space design rules

• All Layer Via interconnect with stacked vias, Via in Pad

• 12 layer build-up in plane/signal pattern configuration and pattern density typical of the art for Smartphone logic boards

• PCB materials typical of the art with FR4.1 with 1037 & 1067 reinforcement incorporated in the design


General Project Work Flow

PCBA TV Drop TV

Data Analysis &

Failure Analysis

PCBA Assembly &

ICT

PCB Fabrication& SOT

PCB TV PoCBuild & Test

( reflow, MSA )

PCB TV Redesign

( if required)

PCBA Assembly

Tooling Design & Preparation

PCB Materials

Components & Assembly

Materials

AATSDrop Tests

Test Report Paper & Poster

PCBA TV PCB TV PCB TV

Short Term Tests

Long Term Tests

End

Start

PCB TV Design& Tooling

Idea Stage

Implementation Stage

current

status

Test Work Flow PCB & AATS TV

8 sets

Start

8 sets

8 sets

Start

8 sets

PCB TV Test Kit

Without Conditioning

Reflow Simulation

6x, 12x

0.40mm BGA

0.25mm BGA01005 passive

PCBA TV Assembly & Kit

- Mechanical- Thermal- IST

IST Pass triggers ASSY

- CAF 1000 hrs

- AATS 2000 x

Data Analysis, Failure Analysis

& Reporting

EndAATS 2000x or beyond (to fail)

Test Work Flow Drop Test Vehicles

8 sets of coupons

Start

8 sets of coupons

8 test boards

Start

8 test boards

Drop Test TV PCB couppns

Without Conditioning

Reflow Simulation

6x, 12x

0.40mm BGA

0.30mm WCSP

PCBA TV Assembly & Kit

- 4 Point Bend- JEDEC Drop

IST Pass triggers ASSY

Data Analysis, Failure Analysis

& Reporting

End

- Mechanical- Thermal- IST

Project Task List

Work Progress – PCB TV Prototype

peel strength strips

thermal analysis

(w/ copper)

thermal analysis

(w/o copper)

High-Potlayer/layer

line/line

4 pointbend

BGA ballshear/pull

multi-pattern delamination

stacked via hole/hole

CAF 0.30/0.40m

mlayer/layer

CAF

PTH hole/hole CAF 0.60/0.50mm pitch

PTH daisy-chain 0.60/0.50mm pitch

stacked via daisy-chain 0.30/0.40mm

stacked viaIST coupons

0.30/0.40mm

line/line CAF75/50um spacing

Active Participants

Engent Fei Xie

Kyzen Mike Bixenmann

Panasonic Tony Senese

TTM Tommy Huang

Angela Lee

Summer Xiao

C.B. Katzko Project Leader

HDPUG Ruben Bergman

Robert Smith Project Facilitator

Supporters & Friends

Alcatel-Lucent Joseph Smetana ITEQ Robert Hung

Boeing Kenneth C. Noddings

Kyzen Mike Bixenmann

Curtiss-Wright Ivan Straznicky Nihon Superior Keith Howell

Engent Dan Baldwin Panasonic Abe Tomoyuki

Paul Houston Park Electro Silvio Bertling

Flextronics Jennifer Nguyen Poltronic Paul Collander

HDPUG Jack Fisher Sekisui Hiroya Ishida

Lawrence Schultz Shengyi Sytech Kevin Zhang

Marshall Andrews TTM Technologies Zaron Huang

Hitachi Chemical Ken Hikida Marika Immonen

Takahiro Tanabe Tarja Rapala

Isola Fred Hickman Texas Instruments Luu Nguyen

TUC Alan Cochrane

Thank You

Q&A© High Density Packaging Users Group,

Inc.

Ultra Thin HDI Multi-purpose Test Vehicle Definition Stage Project C.B. Katzko, TTM Technologies HDPUG Member Meeting, 2014 June 04 Düren, Germany Hosted.

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