“Ultra-Thin Embedded Capacitance Laminates and how they improve the PDN and can Impact EMC”
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“Ultra-Thin Embedded Capacitance
Laminates and how they improve
the PDN and can Impact EMC”
Agenda1. Typical/ Traditional PDN2. The PDN using embedded capacitance3. Some Causes of Resonance and EMC in PCB’s4. Ultra-Thin Laminates for Embedded Capacitance and the reducing impact on EMC5. Some practical results/ case studies6. What’s Next
TYPICAL/ TRADITIONAL POWER DISTRIBUTION NETWORK
TYPICAL/ TRADITIONAL POWER DISTRIBUTION NETWORK
Courtesy of Dr. Jun Fan
Current Drawn from Power
Courtesy of Dr. Jun Fan
High capacitance and capacitance uniformity is the key to embed
Source: Richard Ulrich University of Arkansas
Component density is reaching its limit
Passive components
Trends in PCB DevelopmentUltra-thin Laminate Approach to Embedded Capacitance Technology-BENEFITS • Reduction and/or elimination of surface CAPACITORS and resistors
increases reliability of the device• ELECTROMAGNETIC INTERFERENCE (EMI) from the PCB is reduced or
eliminated using some ultra thin film based laminates• IMPEDA NCE is greatly reduced!!! • RoHS compliant• Provides more efficient/ excellent POWER DELIVERY (charge comes
directly underneath the device, 1 mil up)• SIMPLIFY CIRCUIT ROUTING and eliminates 2 vias, traces, and pads for
every capacitor eliminated. • Allows for a smaller PWB DESIGN- FORM FACTOR if needed.
Background / Motivation
Trends in PCB DevelopmentBackground / Motivation
Ultra thin Laminate Approach to Embedded Capacitance Technology-BENEFITS (continued)
• BETTER ELECTRICAL PERFORMANCE and HIGHER RELIABILITYdemonstrate the benefit of this ultra thin film based embedded capacitance approach
• ASSEMBLY COST is reduced by minimizing passives used • Eliminates or minimizes issues with POOR SURFACE MOUNT
CONNECTIONS or poor joints since the shared capacitor layer is embedded • This technology is NOT NEW and has been used for many years although there
is now more need for it due to densities of the newest designs • PCB and assembly will be LIGHTER
Background / MotivationTrends in PCB Development
Embedded Capacitance Technology
“Thin” power ground plane is the key parameter to improve electrical performance at high frequency!
⊿V=I*R+L*di/dt
V
Voltage Regulator
PowerGround
ICEmbedded
capacitance layer
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Itanium
ITRS 2010
AthalonPentium 1
486386
Voltage
Pow
er (W
)
Voltage is decreasing
TimeAllowable ⊿V is ±5% of Voltage
⊿V
Will increase as Power increase
Will increase as clock speed increase
50
100
150
ITRS, Swaminathan etal.
⊿V<50mV
⊿V<250mV
L∝Loop area ∝Power ground thickness
⊿V<500mV
Background of demand for PCB with Embedded Capacitor
Solution
Ultra-Thin substrate for use as power distribution layer
Copper Foil
Copper Foil
Construction of ultra-thin substrate
Dielectric layer8 to 24 um
TYPICAL PCB DESIGN AND STACK UP
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
Layer 9
Layer 10
Layer 1
Layer 2
Layer 3
Layer 4
Layer 5
Layer 6
Layer 7
Layer 8
Layer 9
Layer 10
FR4 Laminate
FR4 Laminate
FR4 Laminate
FR4 Laminate
FR4 Laminate
FR4 Laminate
Buried Capacitance
Buried Capacitance
PREPREG
PREPREG
PREPREG
PREPREG
PREPREG
PREPREG
PREPREG
PREPREG
PREPREG
PREPREG
10 LAYER PCB STACK-UPWith 2 Power-Ground layers at L2/L3 and L8/L9
(using 24 micron laminate in the Power-Ground allows for buried capacitance)
With 50 micron FR4 Power-Ground
With 24 micron Power-Ground
Power
Ground
Power
Ground
Ground
Power
Ground
Power
24 Layer Board12 µm
Capacitor Core
Capacitor Core
PCB Example Sun Microsystems PCB
High Volume Server
IMPROVED IMPEDENCE/ INDUCTANCE
PCB Electrical Performance
0.001
0.01
0.1
1
10
1E+06 1E+07 1E+08 1E+09 1E+10
Frequency (Hz)
Self
Impe
danc
e (o
hms)
ZBC-2000 -50 micron FR4
BC1000 -25 micron FR4BC24 micron
BC16 micron
BC8 micron
BC12TM micron Filled
BC16T micron Filled
Significant Reduction of Impedance
Panel Size= 50 in2
80% Retained Cu
nFProduct
124BC8
76BC12
180BC12TM
64BC16
440BC16T
40BC24
32ZBC1000
16ZBC2000
PCB Electrical Performance
Dk Effect
Discrete capacitors of 0.1µF have a resonance frequency of about 15 MHzDiscrete capacitors of 0.01µF have a resonance frequency of about 40 MHz.
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
1E+07 1E+08 2E+08 3E+08 4E+08 5E+08 6E+08 7E+08 8E+08 9E+08Frequency (Hz)
Self
Impe
danc
e (o
hms)
ZBC-2000ZBC-1000FaradFlex BC24FaradFlex BC16FaradFlex BC12TMFaradFlex BC8FaradFlex BC16T
(Up to 1 GHz)
Panel Size= 50 in2
80% Retained Cu
nFProduct
124BC8
76BC12
180BC12TM
64BC16
440BC16T
40BC24
32ZBC1000
16ZBC2000
PCB Electrical Performance
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.0.E+07 5.1.E+08 1.0.E+09 1.5.E+09 2.0.E+09 2.5.E+09Frequency (Hz)
Self
Impe
danc
e (o
hms)
ZBC-2000ZBC-1000FaradFlex BC24FaradFlex BC16FaradFlex BC12TMFaradFlex BC8FaradFlex BC16T
(Up to 3 GHz)
nFProduct
124BC8
76BC12
180BC12TM
64BC16
440BC16T
40BC24
32ZBC1000
16ZBC2000
Panel Size= 50 in2
80% Retained Cu
PCB Electrical Performance
BC8TM
RELIABILITY
PASSFinished Circuit Level Hi-Pot
50 circuits (100V/sec; 500Vmax)
PASSCore Level Hi-Pot Testing 100Cores(100V/sec; 500Vmax)
PASSIST Testing (500 cycles)
PASST-288(>20min)
PASSDielectric Thickness per Cross Section within +/-10%
PASS6x Blind Via Solder Shock
PASS6x Through Hole Solder Shock
Description
Courtesy of Sanmina-SCI
Reliability Tests
PCB FABRICATION/ PROCESSING
Pre-clean- Standard processDry Film lamination- Standard process Expose Image- Standard process
Pattern etching - Thin core compatible line recommended Ex) Thin core Schmid etching line
- Use leader board if not confident - Careful Handling required
Black oxidizing or alternative oxides- Thin core compatible line recommended- Use leader board if not confident- Horizontal line preferred- Careful Handling required
Processing guideline
Patterning
B/O or Alternative process
Dielectric (8,12,16,24μm)
Cu(18,35,70μm)
Important
8 μm to 24 μm Film based laminate and partially filled1. Pre-Clean2. Dry Film lamination3. Expose Image 4. Pattern etching (Both sides)5. Black Oxide or Alternative
16μm (Highly Filled with High DkParticles)1. Pre-Clean2. Dry Film lamination3. Expose Image (Pattern/Blanket)4. Pattern etching (One side)5. Black Oxide or Alternative6. Laminate Prepreg/Cu to Imaged Side7. Pre-Clean8. Dry Film Laminate9. Expose Image (Both Sides)10. Pattern Etching (Both Sides)11. Black Oxide or Alternative
CuPrepregPatterned LayerDielectric (Cap)
Cu
Subassembly
Comparison of Inner layer Processes
Second Lamination/ Laminate Subassembly
Second Imaging Step
POWER DISTRIBUTIONS NETWORK SIMULATIONSRESONANCE/ NOISE/ EMI
Why Buried Capacitance Designs Using Buried Capacitance Can Reduce EMI
2 mil FR4 VERSUS 1 mil Laminate
24 micron polymer film type laminate
Resonance Distribution
35- 0.1μF capsfor power supply
+44-0.1 μF capsfor resonances
0.4mm (16 mil P/G)
35- 0.1μF capsfor power supply
Can not place caps!
24 μm P/GDk 4.4No additional caps
26dB
26dB
Resonance Distribution- Lower Noise Threshold
400 μm (16 mil P/G)79 caps
24 μm P/GDk 4.435 caps
12 μm P/GDk 1035 caps
Standard core(400umFR-4) with no caps Standard core(400umFR-4) with caps
Test Board –Simulation #2
P/G Plane16 micron
Dk 30
P/G Plane 1 mil
P/G Plane ½ mil
P/G Plane FR-4 400umWith Caps
Test Board- Simulation #2
CASE STUDY 1
PCB
(by courtesy of NEC System Technology, Inc. & NEC Information Technology, Inc.)
Ultrathin Core ½ mil high Dkand 1 mil
Total 2.368 ±0.2mm
resistInclude Plating0.057Signal14
0.11prepreg0.032Gnd(Plane)130.15core
0.032Signal120.17prepreg
0.032Gnd(Plane)110.14prepreg
0.032Vdd(Plane)100.15core
0.032Signal90.14prepreg
0.032Signal80.15core
0.032Gnd(Plane)70.14prepreg
0.032Signal60.15core
0.032Vdd(Plane)50.14prepreg
0.032Gnd(Plane)40.17prepreg
0.032Signal30.15core
0.032Gnd(Plane)20.11prepreg
Include Plating0.057Signal1resist
Thickness[mm]LayerNo.Construction of Reference Board
Ultrathin Core½ mil high Dkand 1 mil
・PCB Vertical
・PCB Horizontal
・Antenna direction is Vertical (Vertical Polarized Wave Measurement)・Antenna direction is Horizontal (Horizontal Polarized Wave Measurement)
Preamp Spectrum Analyzer
Controller
Control Terminal PC
Turn Table Antenna
A Conception Diagram of The Distant Place Magnetic Field Measurement
（Source; Noise Laboratory)
0 200 400 600 800 100010
20
30
40
リファレンス基板BC24基板
Cap取り外し、PCB水平置き
周波数（MHz)
電界
強度
（dB/
uV）
0 200 400 600 800 100010
20
30
40
リファレンス基板BC24基板
Cap取り外し、PCB垂直置き
周波数（MHz)
電界
強度
（dB/
uV）
Fiel
d S
treng
thFi
eld
Stre
ngth
Frequency, MHz
Frequency, MHz
BC24 Horizontalw/o caps
Reference Board
1 mil core Horizontal
1 mil core Verticalw/o caps
1 mil Laminate
1/2 mil Laminate
CASE STUDY 2
3.3V
1.5V
1.5V
3.3V
1.5V
1.5V
781 0.1μF decoupling capacitors
Capacitance Measurements(courtesy of Univ. of Missouri at Rolla)
Note: 1.5V plane is split resulting in smaller capacitor area
Replaces 78.1 μF of capacitance on standard board (781 capacitors of 0.1 μF )
24 μm 12 μm 12 μm DK10
Board Impedance Measurements (S21, Z11)
Time Domain Power Bus Noise Measurement
24 μm 12 μm 12 μm Dk 10
12 μm Dk 1012 μm24 μm50 μm
50 μm
Frequency Domain Power Bus Noise Measurement
Tested to 1 GHz
50 μm
50 μm
24 μm
24 μm
12 μm
12 μm
12 μm Dk 10
12 μm Dk 10
CASE STUDY 3
The Embedded Passives Journey
IPC/APEX – April 2, 2008Authors:
Bill Devenish – Harris Corp., Mechanical Advanced Development (MAD)Andrew Palczewski – Harris Corp., PCB Technologist
Used with the permission of Harris Corporation
Used with the permission of Harris Corporation
Used with the permission of Harris Corporation
Courtesy of Harris Corp. and CALCE
Other Benefits
Capacitor Material vs. FR4
Sheet Resistivities (ohm/square) 25 25 Nominal Material Tolerance +/-5% +/-5 %
MIL-STD-202-108I Load Life Cycling Test Ambient Temp: 70C Resistor Size: 0.500" X 0.050" On Cycle: 1.5 hrs Loaded: (Δ R%) @ 150mW <0.9 after 3200 hrs.) <5 Off Cycle: 1.5 hrs Unloaded: (Δ R%) <0.74 after 3200 hrs.) Length Of Test: 10000 hrs
MIL-STD-202-308 Current Noise Index in dB <-23 <-15 Voltage Applied: 5.6 Volts
MIL-STD-202-103A Temp: 40 °C
Humidity Test (Δ R%) 0.5 0.5 Relative Humidity: 95% Time: 240 hrs MIL-STD-202-304
Characteristic (RTC) PPM/°C -6.0 50 Hot Cycle: 25°, 50°,75° 125°C Cold Cycle: 25°, 0°,-25°, -55°C MIL-STD-202-107B
Thermal Shock (Δ R%) 0.2 -0.5 No of Cycles: 25 Hot Cycle Temp: 125 °C Cold Cycle Temp: -65 °C
Solder Float (Δ R%) MIL-STD-202-210D After 1 Cycle -0.4 0.5 Temp: 260°C After 5 cycles -0.6 Immersion: 20 Second Power Density (mW/mil 2) 0.45 0.15 Step-up Power Test derated at 50% Resistor size 0.020" x 0.030"
Properties NiP/CapacitorCore
NiP CoreFR-4 (control)
Remarks and Conditions
Synergistic Effect !
3X better power density through resistor due to better heat conductivity of the buried capacitor laminate
Buried Capacitance™ Core Standard Core
Thinner dielectric provides better heat transfer
Some ultra thin laminates have 3 to 5 times better heat transfer
• Embedded Capacitor and can Improve System Price/Performanceby
– Reducing Discrete Caps– Reducing PWB size– Increasing Functionality – Improving power distribution– Improving Signal integrity
• Thinner Power Distribution Planes are required for improved Impedance Performance at high frequency
• New Substrates have demonstrated excellent electrical performance and physical properties.
• They are compatible with PCB processing; a truly “drop in”material.
• Materials are commercially available from many Fabricators• Substrates Filled with Ferroelectric Particles have better
performance, but result in higher cost PCBs• GREEN and Lead Free Solution
Thank You
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