General Description The MAX9867 is an ultra-low power stereo audio codec designed for portable consumer devices such as mobile phones and portable gaming consoles. The device features stereo differential microphone inputs that can be connected to either analog or digital micro- phones. The single-ended line inputs, with configurable preamplifier, can be sent to the ADC for record or routed directly to the headphone amplifier for playback. An aux- iliary ADC path can be used to track any DC voltage. The stereo headphone amplifiers support differential, single-ended, and capacitorless output configurations. Using the capacitorless output configuration, the device can output 10mW into 32 Ω headphones. Comprehensive click-and-pop circuitry suppresses audible clicks and pops during volume changes and startup or shutdown. Utilizing Maxim’s proprietary digital circuitry, the device can accept any available 10MHz to 60MHz system clock. This architecture eliminates the need for an external PLL and multiple crystal oscillators. The stereo ADC and DAC paths provide user-configurable voice- band or audioband digital filters. Voiceband filters pro- vide extra attenuation at the GSM packet frequency and greater than 70dB stopband attenuation at f S /2. The MAX9867 operates from a single 1.8V supply, and supports a 1.65V to 3.6V logic level. An I 2 C 2-wire seri- al interface provides control for volume levels, signal mixing, and general operating modes. The MAX9867 is available in a tiny 2.2mm x 2.7mm, 0.4mm-ball-pitch, WLP package. A 32-pin 5mm x 5mm TQFN package is also available. Features ♦ 1.8V Single-Supply Operation ♦ 6.7mW Playback Power Consumption ♦ 90dB Stereo DAC, 8kHz ≤ f S ≤ 48kHz ♦ 85dB Stereo ADC, 8kHz ≤ f S ≤ 48kHz ♦ Battery-Measurement Auxiliary ADC ♦ Support for Any Master Clock Between 10MHz to 60MHz ♦ Stereo Digital Microphone Input Support ♦ Stereo Analog Differential Microphone Inputs ♦ Stereo Headphone Amplifiers: Differential, Single-Ended, or Capacitorless ♦ Stereo Line Inputs ♦ Voiceband Filter with a Stopband Attenuation Greater than 70dB ♦ 1.65V to 3.6V Digital Interface Supply Voltage ♦ I 2 S/TDM-Compatible Digital Audio Bus ♦ 30-Bump, 2.2mm x 2.7mm 0.4mm-Pitch WLP MAX9867 Ultra-Low Power Stereo Audio Codec ________________________________________________________________ Maxim Integrated Products 1 19-4573; Rev 2; 6/10 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9867EWV+ -40°C to +85°C 30 WLP MAX9867ETJ+ -40°C to +85°C 32 TQFN-EP* +Denotes lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Applications Cell Phones Portable Gaming Devices Portable Navigation Devices Portable Multimedia Players Wireless Headsets MAX9867 ADC AUDIO DIGITAL FILTERS DAC DAC MIX MIX DIGITAL AUDIO INTERFACE DIGITAL MICROPHONE INTERFACE CONTROL INTERFACE HEADPHONE AMP RIGHT MIC AMP LEFT MIC AMP LEFT PREAMP RIGHT PREAMP LINEIN 1 LINEIN 2 HEADPHONE AMP I 2 C I 2 S/PCM ADC Simplified Block Diagram
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Ultra-Low Power Stereo Audio Codec - Maxim IntegratedGeneral Description The MAX9867 is an ultra-low power stereo audio codec designed for portable consumer devices such as mobile
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General DescriptionThe MAX9867 is an ultra-low power stereo audio codecdesigned for portable consumer devices such asmobile phones and portable gaming consoles.
The device features stereo differential microphone inputsthat can be connected to either analog or digital micro-phones. The single-ended line inputs, with configurablepreamplifier, can be sent to the ADC for record or routeddirectly to the headphone amplifier for playback. An aux-iliary ADC path can be used to track any DC voltage.
The stereo headphone amplifiers support differential,single-ended, and capacitorless output configurations.Using the capacitorless output configuration, thedevice can output 10mW into 32Ω headphones.Comprehensive click-and-pop circuitry suppressesaudible clicks and pops during volume changes andstartup or shutdown.
Utilizing Maxim’s proprietary digital circuitry, the devicecan accept any available 10MHz to 60MHz systemclock. This architecture eliminates the need for anexternal PLL and multiple crystal oscillators. The stereoADC and DAC paths provide user-configurable voice-band or audioband digital filters. Voiceband filters pro-vide extra attenuation at the GSM packet frequencyand greater than 70dB stopband attenuation at fS/2.
The MAX9867 operates from a single 1.8V supply, andsupports a 1.65V to 3.6V logic level. An I2C 2-wire seri-al interface provides control for volume levels, signalmixing, and general operating modes.
The MAX9867 is available in a tiny 2.2mm x 2.7mm,0.4mm-ball-pitch, WLP package. A 32-pin 5mm x 5mmTQFN package is also available.
Features 1.8V Single-Supply Operation
6.7mW Playback Power Consumption
90dB Stereo DAC, 8kHz ≤ fS ≤ 48kHz
85dB Stereo ADC, 8kHz ≤ fS ≤ 48kHz
Battery-Measurement Auxiliary ADC
Support for Any Master Clock Between 10MHz to60MHz
Stereo Digital Microphone Input Support
Stereo Analog Differential Microphone Inputs
Stereo Headphone Amplifiers: Differential,Single-Ended, or Capacitorless
Stereo Line Inputs
Voiceband Filter with a Stopband AttenuationGreater than 70dB
ELECTRICAL CHARACTERISTICS(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN in differentialmode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =0dB, MCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.
(Voltages with respect to AGND.)DVDD, AVDD, and PVDD.........................................-0.3V to +2VDVDDIO.................................................................-0.3V to +3.6VDGND and PGND..................................................-0.1V to +0.1VPREG, REF, REG, MICBIAS ....................-0.3V to (AVDD + 0.3V)MCLK, LRCLK, BCLK
SDOUT, SDIN .................................-0.3V to (DVDDIO + 0.3V)SDA, SCL, IRQ ......................................................-0.3V to +3.6VLOUTP, LOUTN, ROUTP,
ROUTN.................................(PGND - 0.3V) to (PVDD + 0.3V)LINL, LINR, JACKSNS/AUX, MICLP/DIGMICDATA,
MICLN/DIGMICCLK, MICRP, MICRN..-0.3V to (AVDD + 0.3V)
Operating Temp Range.......................................-40°C to +85°CStorage Temp Range ........................................-65°C to +150°CLead Temperature (TQFN only, 10s) ...............................+300°CSoldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PVDD, DVDD, AVDD 1.65 1.8 1.95Supply Voltage Range
DVDDIO 1.65 1.8 3.6V
Analog (AVDD +PVDD)
4.65 7Full-duplex 8kHzmono (voice mode)(Note 3) Digital (DVDD +
DVDDIO)0.96 1.5
Analog (AVDD +PVDD)
3.28 5DAC playback 48kHzstereo (audio mode)(Note 3) Digital (DVDD +
DVDDIO)1.40 2
Analog (AVDD +PVDD)
8.0 12Full-duplex 48kHzstereo (audio mode)(Note 3) Digital (DVDD +
DVDDIO)2.0 3
Analog (AVDD +PVDD)
3.8 6
Total Supply Current IVDD
Stereo line-in onlyDigital (DVDD +DVDDIO)
0.004 0.05
mA
Analog (AVDD +PVDD)
1 5
Shutdown Supply Current TA = +25°CDigital (DVDD +DVDDIO)
1 5
µA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Minimum BCLK High Time tBCLKH Slave operation 30 ns
Minimum BCLK Low Time tBCLKL Slave operation 30 nsBCLK or LRCLK Rise and Fall tR, tF Master operation, CL = 15pF 7 ns
SDIN or LRCLK to BCLK SetupTime
tSU 20 ns
SDIN or LRCLK to BCLK HoldTime
tHD 0 ns
SDOUT Delay Time from BCLKRising Edge
tDLY CL = 30pF 0 40 ns
I2C TIMING CHARACTERISTICS (VDVDD = 1.65V)
Serial-Clock Frequency fSCL 0 400 kHz
Bus Free Time Between STOPand START Conditions
tBUF 1.3 µs
Hold Time (REPEATED) STARTCondition
tHD, STA 0.6 µs
SCL Pulse-Width Low tLOW 1.3 µs
SCL Pulse-Width High tHIGH 0.6 µs
Setup Time for a REPEATEDSTART Condition
tSU, STA 0.6 µs
Data Hold Time tHD, DAT RPU, SDA = 475Ω 0 900 ns
Data Setup Time tSU, DAT 100 ns
SDA and SCL Receiving RiseTime
tR (Note 10)20 +
0.1CB300 ns
SDA and SCL Receiving FallTime
tF (Note 10)20 +
0.1CB300 ns
SDA Transmitting Fall Time tFRPU, SDA = 475Ω(Note 10)
20 +0.1CB
250 ns
Setup Time for STOP Condition tSU, STO 0.6 µs
Bus Capacitance CB 400 pF
Pulse Width of Suppressed Spike tSP 0 50 ns
Note 2: The MAX9867 is 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design.Note 3: Clocking all zeros into the DAC, master mode, and differential headphone mode.Note 4: DAC performance measured at the headphone outputs.Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.Note 6: Performance measured using microphone inputs, unless otherwise stated.Note 7: Performance measured using line inputs.Note 8: Performance measured using DAC, unless otherwise stated. LRCLK = 8kHz, unless otherwise stated.Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.Note 10: CB is in pF.
ELECTRICAL CHARACTERISTICS (continued)(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN in differentialmode, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =0dB, MCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
2 B3 SCL I2C Serial-Clock Input. Connect a pullup resistor to a 1.7V to 3.3V supply.
3 A3 SDA I2C Serial-Data Input/Output. Connect a pullup resistor to a 1.7V to 3.3V supply.
4 C3 IRQ
Hardware Interrupt Output. IRQ can be programmed to pull low when bits instatus register 0x00 are set. Read status register 0x00 to clear IRQ once set.Repeat faults have no effect on IRQ until it is cleared by reading register 0x00.Connect a 10kΩ pullup resistor to a 1.7V to 3.3V supply.
5 A4 AVDD Analog Power Supply. Bypass to AGND with a 1µF capacitor.
6 B4 REF Converter Reference. Bypass to AGND with a 2.2µF capacitor (1.23V nominal).
7 A5 PREGPositive Internal Regulated Supply. Bypass to AGND with a 1µF capacitor (1.6Vnominal).
8 B5 REG PREG/2 Voltage Reference. Bypass to AGND with a 1µF capacitor (0.8V nominal).
9 A6 AGND Analog Ground
10 B6 MICBIASLow-Noise Microphone Bias. Connect a 2.2kΩ to 470Ω resistor to the positiveoutput of a microphone (1.525V nominal). Bypass to AGND with a 1µF capacitor.
11 C5MICLN/
DIGMICCLK
Left Negative Differential Microphone Input or Digital Microphone Clock Output.For analog microphones, AC-couple to the negative output of a microphone with a1µF capacitor. For digital microphones, connect to the clock input of themicrophone.
12 C6MICLP/
DIGMICDATA
Left Positive Differential Microphone Input or Digital Microphone Data Input. Foranalog microphones, AC-couple to the positive output of a microphone with a 1µFcapacitor. For digital microphones, connect to the data output of themicrophone(s). Up to two digital microphones can be connected.
13 C4 MICRPRight Positive Differential Microphone Input. AC-couple to the positive output of amicrophone with a 1µF capacitor.
14 D6 MICRNRight Negative Differential Microphone Input. AC-couple to the negative output ofa microphone with a 1µF capacitor.
15 D5 LINL Left-Line Input. AC-couple analog audio signal to LINL with a 1µF capacitor.
16 E6 LINR Right-Line Input. AC-couple analog audio signal to LINR with a 1µF capacitor.
17 D4 JACKSNS/AUX
Jack Sense or Auxiliary ADC Input. When configured for jack detection, JACKSNSdetects the presence or absence of a jack. See the Mode Configuration sectionfor details. When configured as an auxiliary ADC input, AUX is used to measureDC voltages.
18 E5 PGND Headphone Power Ground
19 D3 ROUTPPositive Right-Channel Headphone Output. Connect directly to the load indifferential and capacitorless mode. AC-couple to the load in single-ended mode.
20 E4 ROUTNNegative Right-Channel Headphone Output. Inverting output in differential mode.Leave unconnected in capacitorless and fast turn-on single-ended mode. Bypasswith a 1µF capacitor to AGND in clickless, single-ended mode.
21 D2 LOUTN
Negative Left-Channel Headphone Output. Noninverting output in differentialmode. Common headphone return in capacitorless mode. Leave unconnected infast turn-on single-ended mode. Bypass with a 1µF capacitor to AGND in clicklesssingle-ended mode.
Detailed DescriptionThe MAX9867 is a low-power stereo audio codecdesigned for portable applications requiring minimumpower consumption.
The stereo playback path accepts digital audio througha flexible interface compatible with I2S, TDM, and left-justified signals. An oversampling sigma-delta DACconverts the incoming digital data stream to analogaudio and outputs the audio through the stereo head-phone amplifier. The headphone amplifier can be con-figured in differential, single-ended, and capacitorlessoutput modes.
The stereo record path has two analog microphoneinputs with selectable gain. An integrated microphonebias can be used to power the microphones. The leftanalog microphone inputs can also accept data fromup to two digital microphones. An oversampling sigma-delta ADC converts the microphone signals and out-puts the digital bit stream over the digital audiointerface.
Integrated digital filtering provides a range of notch andhighpass filters for both the playback and record pathsto limit undesirable low-frequency signals and GSM
transmission noise. The digital filtering provides attenuationof out-of-band energy by over 70dB, eliminating audi-ble aliasing. A digital sidetone function allows audiofrom the record path to be summed into the playbackpath after digital filtering.
The MAX9867 also includes two stereo, single-endedline inputs with gain adjustment, which can be record-ed by the ADCs and/or output by the headphone ampli-fiers. An auxiliary ADC accurately measures a DCvoltage by utilizing the right audio ADC and reportingthe DC voltage through the I2C interface. A jack detec-tion function allows the detection of headphone, micro-phone, and headset jacks. Insertion and removalevents can be programmed to trigger a hardware inter-rupt and flag an I2C register bit.
The MAX9867’s flexible clock circuitry utilizes a program-mable clock divider and a digital PLL, allowing the DACand ADC to operate at maximum dynamic range for allcombinations of master clock (MCLK) and sample rate(LRCLK) without consuming extra supply current. Anymaster clock between 10MHz and 60MHz is supportedas are all sample rates from 8kHz to 48kHz. Master andslave modes are supported for maximum flexibility.
22 E3 LOUTPPositive Left-Channel Headphone Output. Connect directly to the load indifferential and capacitorless mode. AC-couple to the load in single-ended mode.
23 E2 PVDD Headphone Power Supply. Bypass to PGND with a 1µF capacitor.
24, 25 — N.C. No Connection
26 E1 DVDDIO Digital Audio Interface Power Supply. Bypass to DGND with a 1µF capacitor.
27 D1 SDOUT Digital Audio Serial-Data ADC Output
28 C2 SDIN Digital Audio Serial-Data DAC Input
29 C1 LRCLK
Digital Audio Left-Right Clock Input/Output. LRCLK is the audio sample rate clockand determines whether the audio data on SDIN is routed to the left or rightchannel. In TDM mode, LRCLK is a frame synchronization pulse. LRCLK is aninput when the MAX9867 is in slave mode and an output when in master mode.
30 B1 BCLKDigital Audio Bit Clock Input/Output. BCLK is an input when the MAX9867 is inslave mode and an output when in master mode.
31 B2 MCLK Master Clock Input. Acceptable input frequency range: 10MHz to 60MHz.
32 A1 DVDDDigital Power Supply. Supply for the digital circuitry and I2C interface. Bypass toDGND with a 1µF capacitor.
— — EP Exposed Pad. Connect the exposed thermal pad to AGND.
MA
X9
86
7 I2C RegistersThe MAX9867 audio codec is completely controlledthrough software using an I2C interface. The power-ondefault setting is complete shutdown, requiring that theinternal registers be programmed to activate the device.See Table 1 for the device’s complete register map.
I2C Slave AddressThe MAX9867 responds to the slave address 0x30 forall write commands and 0x31 for all read operations.
Device StatusStatus registers 0x00 and 0x01 are read-only registersthat report the status of various device functions. Thestatus register bits are cleared upon reading the status
register and are set the next time the event occurs.Registers 0x02 and 0x03 report the DC level applied toAUX. See the ADC section for more details and Table 2.
Jack S ense ( Read O nl y) LSNS JKSNS JKMIC 0 0 0 0 0 0x01
AUX High (Read Only) AUX[15:8] 0x02
AUX Low (Read Only) AUX[7:0] 0x03
BITS FUNCTION
CLDClip Detect FlagIndicates that a signal has reached or exceeded full scale in the ADC or DAC.
SLD
Slew Level Detect FlagWhen volume or gain changes are made, the slewing circuitry smoothly steps through all intermediatesettings. When SLD is set high, all slewing has completed and the volume or gain is at its final value. SLDis also set when soft-start or stop is complete.
ULKDigital PLL Unlock FlagIndicates that the digital audio PLL has become unlocked and digital signal data is not reliable.
JDETHeadset Configuration Change FlagJDET is set whenever there is a change in register 0x01, indicating that the headset configuration haschanged.
LSNS
LOUTP State (Valid if SHDN = 0, JDETEN = 1)LSNS is set when the voltage at LOUTP exceeds AVDD - 0.4V. An internal pullup from AVDD to LOUTPcauses this condition whenever there is no load on LOUTP. LSNS is only valid in differential andcapacitorless output modes.
JKSNSJACKSNS State (Valid if JDETEN = 1)JKSNS is set when the voltage at JACKSNS exceeds AVDD - 0.4V. An internal pullup from AVDD toJACKSNS causes this condition whenever there is no load on JACKSNS.
JKMICMicrophone Detection (Valid if PALEN or PAREN ≠ 00 and JDETEN = 1)JKMIC is set when JACKSNS exceeds 0.95 x VMICBIAS.
AUX
Auxiliary Input MeasurementAUX is a 16-bit signed two’s complement number representing the voltage measured at JACKSNS/AUX.Before reading a value from AUX, set AUXCAP to 1 to ensure a stable reading. After reading the value,set AUXCAP to 0.Use the following formula to convert the AUX value into an equivalent JACKSNS/AUX voltage:
k = AUX value when AUXGAIN = 1. See the ADC section for complete details.
Table 2. Status Registers
Voltage VAUX
k= × ⎛
⎝⎜⎞⎠⎟
0 738.
MA
X9
86
7 Hardware InterruptsHardware interrupts are reported on the open-drain IRQpin. When an interrupt occurs, IRQ remains low until theinterrupt is serviced by reading the status register 0x00.If a flag is set, it is reported as a hardware interrupt onlyif the corresponding interrupt enable is set. Each bitenables interrupts for the status flag in the respectivebit location in register 0x00. See Table 3.
SDODLY is used to control the SDOUT timing. See theDigital Audio Interface section for a detailed description.
Clock Control The MAX9867 can work with a master clock (MCLK)supplied from any system clock within the 10MHz-to-60MHz range. Internally, the MAX9867 requires a10MHz-to-20MHz clock. A prescaler divides MCLK by1, 2, or 4 to create the internal clock (PCLK). PCLK isused to clock all portions of the MAX9867. See Table 4.
The MAX9867 is capable of supporting any sample ratefrom 8kHz to 48kHz, including all common sample rates(8kHz, 16kHz, 24kHz, 32kHz, 44.1kHz, and 48kHz). To
accommodate a wide range of system architectures,the MAX9867 supports three main clocking modes:
• Normal: This mode uses a 15-bit clock divider coeffi-cient to set the sample rate relative to the prescaledMCLK input (PCLK). This allows high flexibility in boththe MCLK and LRCLK frequencies and can be usedin either master or slave mode.
• Exact Integer: In both master and slave mode, com-mon MCLK frequencies (12MHz, 13MHz, 16MHz,and 19.2MHz) can be programmed to operate inexact integer mode for both 8kHz and 16kHz samplerates. In these modes, the MCLK and LRCLK ratesare selected by using the FREQ bits instead of the NIand PLL control bits.
• PLL: When operating in slave mode, a PLL can beenabled to lock onto externally generated LRCLKsignals that are not integer related to PCLK. Prior toenabling the interface, program NI to the nearestdesired ratio and set the NI[0] = 1 to enable thePLL’s rapid lock mode. If NI[0] = 0, then NI is ignoredand PLL lock time is slower.
MCLK PrescalerDivides MCLK to generate a PCLK between 10MHz and 20MHz.00 = Disable clock for low-power shutdown.01 = Select if MCLK is between 10MHz and 20MHz.10 = Select if MCLK is between 20MHz and 40MHz.11 = Select if MCLK is between 40MHz and 60MHz.
Exact Integer ModesAllows integer sampling for specific PCLK (prescaled MCLK) frequencies and 8kHz or 16kHz sample rates.
FREQ[3:0] PCLK (MHz) LRCLK (kHz) PCLK/LRCLK
0x00 Normal or PLL mode
0x1–0x7 Reserved Reserved Reserved
0x80x9
1212
816
1500750
0xA0xB
1313
816
1625812.5
0xC0xD
1616
816
20001000
0xE0xF
19.219.2
816
24001200
FREQ
Modes 0x8–0xF are available in either master or slave mode. In slave mode, if the indicated PCLK/LRCLK ratiocannot be guaranteed, use PLL mode instead.
PLL
PLL Mode Enable0 = Valid for slave and master mode. The frequency of LRCLK is set by the NI divider bits. In master mode, the MAX9867 generates LRCLK using the specified divide ratio. In slave mode, the MAX9867 expects an LRCLK as specified by the divide ratio.1 = Valid for slave mode only. A digital PLL locks on to any externally supplied LRCLK signal.
Rapid Lock ModeTo enable rapid lock mode, set NI to the nearest desired ratio and set NI[0] = 1 before enabling the interface.
NI
Normal Mode LRCLK DividerWhen PLL = 0, the frequency of LRCLK is determined by NI. See Table 5 for common NI values.
MASMaster Mode0 = The MAX9867 operates in slave mode with LRCLK and BCLK configured as inputs.1 = The MAX9867 operates in master mode with LRCLK and BCLK configured as outputs.
WCI
LRCLK Invert0 = Left-channel data is input and output while LRCLK is low.1 = Right-channel data is input and output while LRCLK is low.Note: WCI is ignored when TDM = 1.
BCI
BCLK InvertIn master and slave modes:0 = SDIN is latched into the part on the rising edge of BCLK.SDOUT transitions after the rising edge of BCLK as determined by SDODLY.1 = SDIN is latched into the part on the falling edge of BCLK.SDOUT transitions after the falling edge of BCLK as determined by SDODLY.In master mode:0 = LRCLK changes state immediately after the rising edge of BCLK.1 = LRCLK changes state immediately after the falling edge of BCLK.
SDODLY
SDOUT Delay0 = SDOUT transitions one half BCLK cycle after SDIN is latched into the part.1 = SDOUT transitions on the same BCLK edge as SDIN is latched into the part.See Figures 1–4 for complete details. See Register 0x04 (interrupt registers).
DLY
Delay Mode0 = SDIN/SDOUT data is latched on the first BCLK edge following an LRCLK edge.1 = SDIN/SDOUT data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge following an LRCLK edge (I2S-compatible mode).Note: DLY is ignored when TDM = 1.
HIZOFF
SDOUT High-Impedance Mode0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9867, allowing SDOUT to be shared by other devices.1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9867.Note: High-impedance mode is intended for use when TDM = 1.
LVOLFIX See the Line Inputs section.
Table 6. Digital Audio Interface Registers
Digital Audio InterfaceThe MAX9867’s digital audio interface supports a widerange of operating modes to ensure maximum compati-bility. See Figures 1–4 for timing diagrams. In mastermode, the MAX9867 outputs LRCLK and BCLK, while inslave mode they are inputs. When operating in master
mode, BCLK can be configured in a number of ways toensure compatiblity with other audio devices.
LVOLFIX is used to fix the line input playback volume to0dB regardless of VOLL and VOLR. See the Line Inputssection for complete details and Table 6.
TDM Mode Select0 = LRCLK signal polarity indicates left and right audio.1 = LRCLK is a framing pulse that transitions polarity to indicate the start of a frame of audio data consisting of multiple channels.When operating in TDM mode, the left channel is output immediately following the frame sync pulse. If right-channel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data.
DMONOMono Playback Mode0 = Stereo data input on SDIN is processed separately.1 = Stereo data input on SDIN is mixed to a single channel and routed to both the left and right DAC.
BSEL
BCLK SelectConfigures BCLK when operating in master mode. BSEL has no effect in slave mode. Set BSEL = 010, unlesssharing the bus with multiple devices:000 = Off001 = 64x LRCLK (192x internal clock divided by 3)010 = 48x LRCLK (192x internal clock divided by 4)011 = Reserved for future use.100 = PCLK/2101 = PCLK/4110 = PCLK/8111 = PCLK/16
Table 6. Digital Audio Interface Registers (continued)
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
LEFT
1/fS
7ns (typ)7ns (typ)
RIGHTLEFT
RIGHTLEFT
Figure 1. Digital Audio Interface Audio Master Mode Example (Sheet 1 of 2)
NOTE: THE DELAY FROM A BCLK EDGE AND AN LRCLK EDGE IS DETERMINED BY LENGTH OF TIME THAT PCLK (THE INTERNALLY DIVIDED DOWN VERSION OF MCLK AS DEFINED BY THE PSCLK BITS) IS HIGH DURING ONE PERIOD OF MCLK PLUS THE INTERNAL DELAY. FOR EXAMPLE: IF PCLK = 12.288MHZ, THEN THE DELAY BETWEEN BCLK AND LRCLK IS TYPICALLY 45ns.
Digital FilteringThe MAX9867 incorporates both IIR (voice) and FIR(audio) digital filters to accomodate a wide range ofaudio sources. The IIR fiilters provide over 70dB of
stopband attenuation as well as selectable highpass fil-ters. The FIR filters provide low-power consumption andare linear phase to maintain stereo imaging. Table 7 isthe digital filtering register.
ADC Digital Audio FilterMODE = 0Select the desired digital filter response from Table 8. See the Frequency Response graph in the TypicalOperating Characteristics section for details on each filter.MODE = 10x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.
DVFLT
DAC Digital Audio FilterMODE = 0Select the desired digital filter response from Table 8. See the Frequency Response graph in the TypicalOperating Characteristics section for details on each filter.MODE = 10x0 = DC-blocking filter is disabled. Any other setting = DC-blocking filter is enabled.
Digital Gain ControlThe MAX9867 includes digital gain adjustment for theplayback and record paths. Independent gain adjust-ment is provided for the two record channels. Sidetone
gain adjustment is also provided to set the sidetonelevel relative to the playback level. Table 9 is the digitalgain registers.
REGISTER B7 B6 B5 B4 B3 B2 B1 B0REGISTERADDRESS
Sidetone DSTS 0 DVST 0x0B
DAC Level 0 DACM DACG DACA 0x0C
ADC Level AVL AVR 0x0D
BITS FUNCTION
DSTS
Digital Sidetone Source Mixer00 = No sidetone is selected.01 = Left ADC10 = Right ADC11 = Left + right ADCDigital Sidetone Level ControlAll gain settings are relative to the ADC input voltage.
Differential Headphone Output ModeSETTING GAIN (dB) SETTING GAIN (dB) SETTING GAIN (dB)
LILM/LIRMLine-Input Left/Right Playback Mute0 = Line input is connected to the headphone amplifiers.1 = Line input is disconnected from the headphone amplifiers.
Line-Input Left/Right Gain
SETTING GAIN (dB) SETTING GAIN (dB)
0x0 +24 0x8 +8
0x1 +22 0x9 +6
0x2 +20 0xA +4
0x3 +18 0xB +2
0x4 +16 0xC 0
0x5 +14 0xD -2
0x6 +12 0xE -4
LIGL/LIGR
0x7 +10 0xF -6
LVOLFIX
Fix Line Input Volume0 = Line input to headphone output volume tracks VOLL and VOLR bits.1 = Line input to headphone output volume fixed at VOLL and VOLR bits.
See the Digital Audio Interface section.
Table 10. Line Input Registers (continued)
Playback Volume The MAX9867 incorporates volume and mute control toallow level control for the playback audio path. Program
registers 0x10 and 0x11 to set the desired volume. SeeTable 11.
Microphone InputsTwo differential microphone inputs and a low-noise micro-phone bias for powering the microphones are providedby the MAX9867. In typical applications, the left micro-phone records a voice signal and the right microphonerecords a background noise signal. In applications thatrequire only one microphone, use the left microphoneinput and disable the right ADC. The microphone signalsare amplified by two stages of gain and then routed to
the ADCs. The first stage offers selectable 0dB, 20dB,or 30dB settings. The second stage is a programmablegain amplifier (PGA) adjustable from 0dB to 20dB in1dB steps. Zero-crossing detection is included on thePGA to minimize zipper noise while making gainchanges. See Figure 5 for a detailed diagram of themicrophone input structure. Table 12 is the microphoneinput register.
Table 12. Microphone Input Registers
REGISTER B7 B6 B5 B4 B3 B2 B1 B0REGISTERADDRESS
Left Microphone Gain 0 PALEN PGAML 0x12
Right Microphone Gain 0 PAREN PGAMR 0x13
BITS FUNCTION
VOLLM/VOLRM
Left/Right Playback MuteVOLLM and VOLRM mute both the DAC and line input audio signals.0 = Audio playback is unmuted.1 = Audio playback is mutedNote: VSEN has no effect on the mute function. When VOLLM or VOLRM is set, the output is mutedimmediately (ZDEN = 1) or at the next zero-crossing (ZDEN = 0).
Left/Right Playback VolumeVOLL and VOLR control the playback volume for both the DAC and line input audio signals.
Note: Gain settings apply when the headphone amplifier is configured in differential mode. In the single-ended and capacitorless modes, the actual gain is 5dB lower for each setting.
ADCThe MAX9867 includes two 16-bit ADCs. The first ADCis used to record left-channel microphone and line-inputaudio signals. The second ADC can be used to recordright-channel microphone and line-input signals, or itcan be configured to accurately measure DC voltages.
When measuring DC voltages, both the left and rightADCs must be enabled by setting ADLEN and ADRENin register 0x17. The input to the second ADC is JACK-SNS/AUX and the output is reported in AUX (registers0x02 and 0x03). Since the audio ADC is used to per-form the measurement, the digital audio interface mustbe properly configured. If the left ADC is being used toconvert audio, the DC measurement is performed at thesame sample rate. When not using the left ADC, config-ure the digital interface for a 48kHz sample rate toensure the fastest possible settling time.
To ensure accurate results, the MAX9867 includes twocalibration routines. Calibrate the ADC each time theMAX9867 is powered on. Calibration settings are notlost if the MAX9867 is placed in shutdown. When mak-ing a measurement, set AUXCAP to 1 to prevent AUXfrom changing while reading the registers.
Setup Procedure1) Ensure a valid MCLK signal is provided and config-
ure PSCLK appropriately.
2) Choose a clocking mode. The following options arepossible:
• Slave mode with LRCLK and BCLK signals pro-vided. The measurement sample rate is deter-mined by the external clocks.
• Slave mode with no LRCLK and BCLK signalsprovided. Configure the device for normal clockmode using the NI ratio. Select fS = 48kHz to allowfor the fastest settling times.
• Master mode with audio. Configure the device innormal mode using the NI ratio or exact integermode using FREQ as required by the audio signal.
• Master mode without audio. Configure thedevice in normal mode using the NI ratio. Select fS= 48kHz to allow for the fastest settling times.
3) Ensure JACKSNS is disabled.
4) Enable the left and right ADC; take the MAX9867 outof shutdown.
Offset Calibration Procedure Perform the following steps before the first DC mea-surement is taken after applying power to theMAX9867:
1) Enable the AUX input (AUXEN = 1).
2) Enable the offset calibration (AUXCAL = 1).
3) Wait the appropriate time (see Table 13).
4) Complete calibration (AUXCAL = 0).
Gain Calibration ProcedurePerform the following steps the first time a DC measure-ment is taken after applying power to the MAX9867 or ifthe temperature changes significantly:
1) Enable the AUX input (AUXEN = 1).
2) Start gain calibration (AUXGAIN = 1).
3) Wait the appropriate time (see Table 13).
4) Freeze the measurement results (AUXCAP = 1).
5) Read AUX and store the value in memory to correctall future measurements (k = AUX[15:0], k is typical-ly 19500).
6) Complete calibration (AUXGAIN = AUXCAP = 0).
DC Measurement ProcedurePerform the following steps after offset and gain cali-bration are complete:
1) Enable the AUX input (AUXEN = 1).
2) Wait the appropriate time (see Table 13).
3) Freeze the measurement results (AUXCAP = 1).
4) Read AUX and correct with the gain calibrationvalue:
Complete DC Measurement ExampleMCLK = 13MHz, slave mode, BCLK and LRCLK notexternally supplied:
1) Configure the digital audio interface for fS = 48kHz(PSCLK = 01, FREQ = 0x0, PLL = 0, NI = 0x5ABE,MAS = 0).
2) Disable JACKSNS (JDETEN = 0).
3) Enable the left and right ADC; take the MAX9867 outof shutdown (ADLEN = ADREN = SHDN = 1).
4) Calibrate the offset:
a. Enable the AUX input (AUXEN = 1).
b. Enable the offset calibration (AUXCAL = 1).
c. Wait 40ms.
d. Complete calibration (AUXCAL = 0).
5) Calibrate the gain:
a. Start gain calibration (AUXGAIN = 1).
b. Wait 40ms.
c. Freeze the measurement results (AUXCAP = 1).
d. Read AUX and store the value in memory to cor-rect all future measurements (k = AUX[15:0]).
e. Complete calibration (AUXGAIN = AUXCAP =AUXEN = 0).
6) Measure the voltage on JACKSNS/AUX:
a. Enable the AUX input (AUXEN = 1).
b. Wait 40ms.
c. Freeze the measurement results (AUXCAP = 1).
d. Read AUX and correct with the gain calibrationvalue.
e. Complete measurement (AUXCAP = 0).
7) DC measurement complete.
Table 14. ADC Input Register
REGISTER B7 B6 B5 B4 B3 B2 B1 B0REGISTERADDRESS
ADC Input MXINL MXINR AUXCAP AU X GAIN AUXCAL AUXEN 0x14
BITS FUNCTION
MXINL/MXINR
Left/Right ADC Audio Input Mixer00 = No input is selected.01 = Left/right analog microphone10 = Left/right line input11 = Left/right analog microphone + line inputNote: If the right-line input is disabled, then the left-line input is connected to both mixers. Enabling theleft and right digital microphones disables the left and right audio mixers, respectively. See DIGMICL/DIGMICR in Table 15 for more details.
AUXCAPAuxiliary Input Capture0 = Update AUX with the voltage at JACKSNS/AUX.1 = Hold AUX for reading.
AUXGAIN
Auxiliary Input Gain Calibration0 = Normal operation1 = The input buffer is disconnected from JACKSNS/AUX and connected to an internal voltage reference. While in this mode, read the AUX register and store the value. Use the stored value as a gain calibration factor, K, on subsequent readings.
AUXCAL
Auxiliary Input Offset Calibration0 = Normal operation1 = JACKSNS/AUX is disconnected from the input and the ADC automatically calibrates out any internal offsets.
AUXEN
Auxiliary Input Enable0 = Use JACKSNS/AUX for jack detection.1 = Use JACKSNS/AUX for DC measurements.Note: For AUXEN = 1, set MXINR = 00, ADLEN = 1, and ADREN = 1.
Digital Microphone InputThe MAX9867 can accept audio from up to two digitalmicrophones. When using digital microphones, the leftanalog microphone input is retasked as a digital micro-
phone input. The right analog microphone input is stillavailable to allow a combination of analog and digitalmicrophones to be used. Figure 6 shows the digitalmicrophone interface timing diagram. See Table 15.
Mode ConfigurationThe MAX9867 includes circuitry to minimize click-and-pop during volume changes, detect headsets, and con-figure the headphone amplifier mode. Both volumeslewing and zero-crossing detection are included toensure click-and-pop free volume transitions. Table 16is the mode configuration register.
Headset Detection OverviewThe MAX9867 features headset detection that can detectthe insertion and removal of a jack as well as the loadtype. When a jack is detected, an interrupt on IRQ can betriggered to alert the microcontroller of the event. Figure 7shows the typical configuration for jack detection.
Sleep-Mode Headset DetectionWhen the MAX9867 is in shutdown and the power supplyis available, sleep-mode headset detection can beenabled to detect jack insertion. Sleep mode applies a4µA pullup current to JACKSNS/AUX and LOUTP thatforces the voltage on JACKSNS/AUX and LOUTP toAVDD when no load is applied. When a jack is inserted,either JACKSNS, LOUTP (assuming the headphoneamplifier is not configured in single-ended mode), or bothare loaded sufficiently to reduce the output voltage tonearly 0V and clear the JKSNS or LSNS bits, respectively.The change in the LSNS and JKSNS bits sets JDET andtriggers an interrupt on IRQ if IJDET is set. The interruptsignals the microcontroller that a jack has been inserted,allowing the microcontroller to respond as desired.
Powered-On Headset DetectionWhen the MAX9867 is in normal operation and the micro-phone interface is enabled, jack insertion and removal canbe detected through the JACKSNS/AUX pin. As shown inFigure 7, VMIC is pulled up by MICBIAS. When a micro-phone is connected, VMIC is assumed to be between 0Vand 95% of VMICBIAS. If the jack is removed, VMIC increas-es to VMICBIAS. This event causes JKMIC to be set, alert-ing the system that the headset has been removed.Alternatively, if the jack is inserted, VMIC decreases tobelow 95% of VMICBIAS and JKMIC is cleared, alerting thesystem that a jack has been inserted. The JKMIC bit canbe configured to create a hardware interrupt that alerts themicrocontroller of jack removal and insertion events.
Headphone ModesThe headphone amplifier supports differential, single-ended, and capacitorless output modes, as shown inFigure 8. In each mode, the amplifier can be configuredfor stereo or mono operation. The differential andcapacitorless modes are inherently click and pop free.The single-ended mode optionally includes click-and-pop reduction to eliminate the click and pop that wouldnormally be caused by the output coupling capacitor.When click-and-pop reduction is not required in the sin-gle-ended configuration, leave LOUTN and ROUTNunconnected.
GND MIC HPR HPL
LOUTP
ROUTP
MICBIAS
JACKSNS/AUX
MICLPLOUTN
Figure 7. Typical Configuration for Headset Detection
LOUTP
LOUTN
ROUTP
ROUTN
DIFFERENTIAL
LOUTP
LOUTN
ROUTP
ROUTN
CAPACITORLESS
1µF
LOUTP
220µF
LOUTN
SINGLE ENDED
1µF
ROUTP
220µF
ROUTN
OPTIONAL COMPONENTS REQUIRED FOR CLICK AND POP SUPPRESSION ONLY
Jack Detection EnableSHDN = 0: Sleep ModeEnables pullups on LOUTP and JACKSNS/AUX to detect jack insertion. LSNS and JKSNS are valid.LOUTP detection is only valid in differential and capacitorless output modes.SHDN = 1: Normal ModeEnables the comparator circuitry on JACKSNS/AUX to detect voltage changes. JKMIC is valid if themicrophone circuitry is enabled.Note: AUXEN must be set to 0 for jack detection to function.Headphone Amplifier Mode
HPMODE Mode
000 Stereo differential (clickless)
001 Mono (left) differential (clickless)
010 Stereo capacitorless (clickless)
011 Mono (left) capacitorless (clickless)
100 Stereo single-ended (clickless)
101 Mono (left) single-ended (clickless)
110 Stereo single-ended (fast turn-on)
111 Mono (left) single-ended (fast turn-on)
HPMODE
Note: In mono operation, the right amplifier is disabled.
Power ManagementThe MAX9867 includes complete power managementcontrol to minimize power usage. The DAC and bothADC can be independently enabled so that only the
required circuitry is active. Toggle the SHDN bit when-ever a configuration change is made. Table 17 is thepower-management register.
SHDNShutdownPlaces the device in low-power shutdown mode.
LNLEN
Left-Line Input EnableEnables the left-line input preamp and automatically enables the left and right headphone amplifiers.If LNREN = 0, the left-line input signal is also routed to the right ADC input mixer and right headphoneamplifier.Note: Control of the right headphone amplifier can be overridden by HPMODE.
LNRENRight-Line Input EnableEnables the right-line input preamp and automatically enables the right headphone amplifier.Note: Control of the right headphone amplifier can be overridden by HPMODE.
DALEN
Left DAC EnableE nab l es the l eft D AC and autom ati cal l y enab l es the l eft and r i g ht head p hone am p l i fi er s. If D ARE N = 0, thel eft D AC si g nal i s al so r outed to the r i g ht head p hone am p l i fi er .Note: Control of the right headphone amplifier can be overridden by HPMODE.
DARENRight DAC EnableEnabling the right DAC must be done in the same I2C write operation that enables the left DAC. RightDAC operation requires DALEN = 1.
ADLEN Left ADC Enable
ADREN
Right ADC EnableEnabling the right ADC must be done in the same I2C write operation that enables the left ADC. The rightADC can be enabled while the left ADC is running if used for DC measurements. SHDN must be toggledto disable the right ADC in this case. Right ADC operation requires ADLEN = 1.
Revision CodeThe MAX9867 includes a revision code to allow easyidentification of the device revision. The revision code is0x42. See Table 18 for the revision code register.
I2C Serial InterfaceThe MAX9867 features an I2C/SMBus-compatible,2-wire serial interface consisting of a serial-data line(SDA) and a serial-clock line (SCL). SDA and SCL facili-tate communication between the MAX9867 and the mas-ter at clock rates up to 400kHz. Figure 9 shows the2-wire interface timing diagram. The master generatesSCL and initiates data transfer on the bus. The masterdevice writes data to the MAX9867 by transmitting theproper slave address followed by the register addressand then the data word. Each transmit sequence isframed by a START (S) or REPEATED START (Sr) condi-tion and a STOP (P) condition. Each word transmitted tothe MAX9867 is 8 bits long and is followed by anacknowledge clock pulse. A master reading data fromthe MAX9867 transmits the proper slave addressfollowed by a series of nine SCL pulses. The MAX9867transmits data on SDA in sync with the master-generatedSCL pulses. The master acknowledges receipt of eachbyte of data. Each read sequence is framed by a STARTor REPEATED START condition, a not acknowledge, anda STOP condition. SDA operates as both an input and anopen-drain output. A pullup resistor, typically greaterthan 500Ω is required on SDA. SCL operates only as aninput. A pullup resistor, typically greater than 500Ω, is
required on SCL if there are multiple masters on the bus,or if the single master has an open-drain SCL output.Series resistors in line with SDA and SCL are optional.Series resistors protect the digital inputs of theMAX9867 from high-voltage spikes on the bus lines, andminimize crosstalk, and undershoot of the bus signals.
Bit TransferOne data bit is transferred during each SCL cycle. Thedata on SDA must remain stable during the high periodof the SCL pulse. Changes in SDA while SCL is highare control signals. See the START and STOPConditions section.
START and STOP ConditionsSDA and SCL idle high when the bus is not in use. Amaster initiates communication by issuing a START con-dition. A START condition is a high-to-low transition onSDA with SCL high. A STOP condition is a low-to-hightransition on SDA while SCL is high (Figure 10). A STARTcondition from the master signals the beginning of atransmission to the MAX9867. The master terminatestransmission, and frees the bus, by issuing a STOP con-dition. The bus remains active if a REPEATED STARTcondition is generated instead of a STOP condition.
SCL
SDA
tR tF
tBUF
STARTCONDITION
STOPCONDITION
REPEATED START CONDITION START CONDITION
tSU, STO
tHD, STAtSU, STA
tHD, DAT
tSU, DAT tLOW
tHIGH
tHD, STA
tSP
Figure 9. 2-Wire Interface Timing Diagram
SCL
SDA
S Sr P
Figure 10. START, STOP, and REPEATED START Conditions
Early STOP ConditionsThe MAX9867 recognizes a STOP condition at anypoint during data transmission except if the STOP con-dition occurs in the same high pulse as a START condi-tion. For proper operation, do not send a STOPcondition during the same SCL high pulse as theSTART condition.
Slave AddressThe slave address is defined as the 7 most significantbits (MSBs) followed by the read/write bit. For theMAX9867, the 7 most significant bits are 0011000.Setting the read/write bit to 1 (slave address = 0x31)configures the MAX9867 for read mode. Setting theread/write bit to 0 (slave address = 0x30) configuresthe MAX9867 for write mode. The address is the firstbyte of information sent to the MAX9867 after theSTART condition.
AcknowledgeThe acknowledge bit (ACK) is a clocked 9th bit that theMAX9867 uses to handshake receipt each byte of datawhen in write mode (see Figure 11). The MAX9867 pulls
down SDA during the entire master-generated 9th clockpulse if the previous byte is successfully received.Monitoring ACK allows for detection of unsuccessfuldata transfers. An unsuccessful data transfer occurs ifa receiving device is busy or if a system fault hasoccurred. In the event of an unsuccessful data transfer,the bus master retries communication. The master pullsdown SDA during the 9th clock cycle to acknowledgereceipt of data when the MAX9867 is in read mode. Anacknowledge is sent by the master after each read byteto allow data transfer to continue. A not acknowledge issent when the master reads the final byte of data fromthe MAX9867, followed by a STOP condition.
Write Data FormatA write to the MAX9867 includes transmission of aSTART condition, the slave address with the R/W bit setto 0, 1 byte of data to configure the internal registeraddress pointer, 1 or more bytes of data, and a STOPcondition. Figure 12 illustrates the proper frame formatfor writing 1 byte of data to the MAX9867. Figure 13illustrates the frame format for writing n bytes of data tothe MAX9867.
The slave address with the R/W bit set to 0 indicatesthat the master intends to write data to the MAX9867.The MAX9867 acknowledges receipt of the addressbyte during the master-generated 9th SCL pulse.
The second byte transmitted from the master config-ures the MAX9867’s internal register address pointer.The pointer tells the MAX9867 where to write the nextbyte of data. An acknowledge pulse is sent by theMAX9867 upon receipt of the address pointer data.
The third byte sent to the MAX9867 contains the datathat is written to the chosen register. An acknowledgepulse from the MAX9867 signals receipt of the data byte.The address pointer autoincrements to the next registeraddress after each received data byte. This autoincre-ment feature allows a master to write to sequential regis-ters within one continuous frame. Figure 13 illustrateshow to write to multiple registers with one frame. Themaster signals the end of transmission by issuing aSTOP condition. Register addresses greater than 0x17are reserved. Do not write to these addresses.
Read Data FormatSend the slave address with the R/W bit set to 1 to initi-ate a read operation. The MAX9867 acknowledgesreceipt of its slave address by pulling SDA low duringthe 9th SCL clock pulse. A START command followedby a read command resets the address pointer to reg-ister 0x00.
The first byte transmitted from the MAX9867 is the con-tent of register 0x00. Transmitted data is valid on therising edge of SCL. The address pointer autoincre-ments after each read data byte. This autoincrementfeature allows all registers to be read sequentially withinone continuous frame. A STOP condition can be issuedafter any number of read data bytes. If a STOP condi-tion is issued followed by another read operation, thefirst data byte to be read is from register 0x00.
The address pointer can be preset to a specific registerbefore a read command is issued. The master presetsthe address pointer by first sending the MAX9867’sslave address with the R/W bit set to 0 followed by theregister address. A REPEATED START condition is thensent followed by the slave address with the R/W bit setto 1. The MAX9867 then transmits the contents of thespecified register. The address pointer autoincrementsafter transmitting the first byte.
The master acknowledges receipt of each read byteduring the acknowledge clock pulse. The master mustacknowledge all correctly received bytes except thelast byte. The final byte must be followed by a notacknowledge from the master and then a STOP condi-tion. Figure 14 illustrates the frame format for reading 1byte from the MAX9867. Figure 15 illustrates the frameformat for reading multiple bytes from the MAX9867.
1 BYTE
AUTOINCREMENT INTERNALREGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9867
ACKNOWLEDGE FROM MAX9867
B1 B0B3 B2B5 B4B7 B6
A A0
ACKNOWLEDGE FROM MAX9867
R/W
S A
1 BYTE
ACKNOWLEDGE FROM MAX9867
B1 B0B3 B2B5 B4B7 B6
PASLAVE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n
Figure 13. Writing n Bytes of Data to the MAX9867
ACKNOWLEDGE FROM MAX9867
1 BYTE
AUTOINCREMENT INTERNALREGISTER ADDRESS POINTER
ACKNOWLEDGE FROM MAX9867NOT ACKNOWLEDGE FROM MASTER
AAA PA0
ACKNOWLEDGE FROM MAX9867
R/W
S
R/WREPEATED START
Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
Figure 14. Reading 1 Byte of Data from the MAX9867
Sr 1SLAVE ADDRESS REGISTER ADDRESS SLAVE ADDRESS DATA BYTE
Figure 15. Reading n Bytes of Data from the MAX9867
Applications InformationProper layout and grounding are essential for optimumperformance. When designing a PCB for the MAX9867,partition the circuitry so that the analog sections of theMAX9867 are separated from the digital sections. Thisensures that the analog audio traces are not routednear digital traces.
Use a large continuous ground plane on a dedicatedlayer of the PCB to minimize loop areas. ConnectAGND and DGND directly to the ground plane usingthe shortest trace length possible. Proper groundingimproves audio performance, minimizes crosstalkbetween channels, and prevents any digital noise fromcoupling into the analog audio signals.
Ground the bypass capacitors on MICBIAS, REG,PREG, and REF directly to the ground plane with mini-mum trace length. Also be sure to minimize the pathlength to AGND. Bypass AVDD directly to AGND.
Connect all digital I/O termination to the ground planewith minimum path length to DGND. Bypass DVDD andDVDDIO directly to DGND.
Route microphone signals from the microphone to theMAX9867 as a differential pair, ensuring that the posi-tive and negative signals follow the same path as close-ly as possible with equal trace length. When usingsingle-ended microphones or other single-ended audiosources, ground the negative microphone input as nearas possible to the audio source and then treat the posi-tive and negative traces as differential pairs.
The MAX9867 TQFN package features an exposedthermal pad on its underside. Connect the exposedthermal pad to AGND.
An evaluation kit (EV Kit) is available to provide anexample layout for the MAX9867. The EV kit allowsquick setup of the MAX9867 and includes easy-to-usesoftware, allowing all internal registers to be controlled.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
30 WLP W302A2+3 21-0211 —
32 TQFN-EP T3255+4 21-0140 90-0121
Package InformationFor the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in thepackage code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to thepackage regardless of RoHS status.
Package Information (continued)For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in thepackage code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to thepackage regardless of RoHS status.
Package Information (continued)For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in thepackage code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to thepackage regardless of RoHS status.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 55