The LTC6950 improves SNR performance and solves clocking problems in high end data converter applications. The LTC6950 integrates a low phase noise integer-N synthesizer along with an ultralow jitter clock distribution output section to produce the low jitter signals essential to clocking data converters with high SNR levels. Besides minimizing jitter, the LTC6950 introduces EZSync TM synchronization, a simple synchronization method that guarantees repeatable edge-synchronized outputs from one chip or multiple chips. Features n Additive Jitter: 18fs RMS (12kHz to 20MHz) n EZSync Multichip Clock Edge Synchronization n Full PLL Core with Lock Indicator n –226dBc/Hz Normalized In-Band Phase Noise Floor n –274dBc/Hz Normalized 1/f Phase Noise n 1.4GHz Maximum VCO Input Frequency n Four Independent, Low Noise 1.4GHz LVPECL Outputs n One LVDS/CMOS Configurable Output n Five Independently Programmable Dividers n Five Independently Programmable VCO Clock Cycle Delays 1.4GHz Clean Clocking Solution with 18fs RMS Jitter (12kHz to 20MHz Bandwidth) Offset Frequency (Hz) 10M 100 100k 1M 10k 1k Absolute Phase Noise (dBc/Hz) –90 –100 –110 –120 –140 –160 –130 –150 –170 –180 DIV = 4, f OUT = 250MHz DIV = 16, f OUT = 62.5MHz DIV = 40, f OUT = 25MHz DIV = 1, f OUT = 1GHz f PFD = 10MHz, f VCO = 1GHz LTC6950 Closed-Loop Phase Noise Ultralow Jitter Clock Generation and Distribution L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and EZSync and ClockWizard are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.