UIS - Failure of DMOS Power Transistors · UIS - Failure of DMOS Power Transistors A. Icaza Deckelmann 1, Gerhard Wachutka , F. Hirler2, J. Krumrey2 1Institute for Physics of Electrotechnology

UIS - Failure of

DMOS Power Transistors

A. Icaza Deckelmann1, Gerhard Wachutka1, F. Hirler2, J. Krumrey2

1Institute for Physics of Electrotechnology, Munich University of Technology, Germany2Infineon Technologies, Munich, Germany

A. Icaza Deckelmann et al. -ESSDERC ‘02

Outline

• Unclamped Inductive Switching (UIS)- some facts

• Analytical Modelling Approach

• Numerical Device Simulation

• Conclusions & Outlook


UIS - Failure of DMOS Power Transistors

Unclamped Inductive Switching (UIS): typical example

i

t

I0

T on: current i flows in channel of TT off: avalanche heat is dissipated in T at rate VBR*i

tLVIti BR ⋅−= 0)(

T

L



Unclamped Inductive Switching: measuring the failure level

UIS- failure measurement

-20.000

0

20.000

40.000

60.000

80.000

100.000

120.000

140.000

time [us]

Vd

s,

Vg

s

Drain VoltageGate VoltageCurrent

• Sudden drop in VDrainindicates device failure

• Current continues to flow

• Gate is turned off



Unclamped Inductive Switching: measuring the failure level

Only a limited amount of heat can be dissipated without device damageThe maximum tolerable UIS- current is determined

by the value of inductance L

Measurement Setup Limiting curve for safe UIS

log(I0Max

)

log(L)

+



Analytical Modelling Approach: From cell array to single cell

• Device consists of integrated cell array

• Experiment shows:failure occurs randomlysomewhere inside the array

• Cells at the border areimmune to UIS failure

Cells may be consideredas equivalent

UIS-failure analysis restricted to one single cellin parallel with the rest of the array



operation stable⇒

<∂∂ 0TI

Analytical Modelling Approach: Collective behavior of cell array

operation unstable⇒

>∂∂ 0TI

ETM

TI∂

∂

1cellI

1cellI1P

ETM

TI∂

∂

2cellI

2cellI2P

T

T

ETM

TI∂

∂

I∆+ncellI _

ncellI _nP T

I

nI /

nI /

nI /

V

V

V

n-1 equivalent cells

1 different cell

ETM: electrothermal model of device cellA. Icaza Deckelmann et al. -ESSDERC ‘02


Analytical Modelling Approach:• Single Cell Model n+

n-

p+

-jnDiff

n+

jpav

p-

Body

Epi

Source Gate

Drain

Emitter

• Electrothermal transport equations• Reflecting boundary conditions at the side borders

• For downward heat transport,the cell is a semi-infinite, 1D solid

• Heat transport equation is linear• Carrier recombination + generation are instantaneous compared totemperature evolution

• In the stable regime, only the avalanchecurrent jpav is taken into account

• Electrical and thermal currents are 1D

UIS - Failure of DMOS Power Transistors A. Icaza Deckelmann et al. -ESSDERC ‘02

Analytical Modelling Approach:• UIS stress without failure n+

n-

p+

-jnDiff

n+

jpav

p-

Body

Epi

Source Gate

Drain

Emitter

UIS stress below instability limit:• Body diode is reverse biased• Avalanche breakdown occurs• Cells in parallel: V1=V2=....=Vn• For perfectly equivalent cells,also I1=I2=....=In

• Actually, cells differ slightlyfrom each other

0<∂∂

TIav

•But, avalanche- induced currentis temperature- stablein each individual cell:

total current uniformly distributed among all cells



failuredevice filamentcurrent

behavior, unstable

⇒

⇒>∂∂ 0TI

Analytical Modelling Approach:• UIS stress causing failure (qualitative)

UIS stress reaches instability limit:• Heat is generated at spot A• Temperature rises at A• Device voltage rises• Thermal diffusion

temperature also rises at BjnDiff is enhanced

• Multiplication rate MnBat spot B increases

further rise of jnDiff*MnBIf jnDiff is the dominant contribution to I:

n+

n-

p+

-jnDiff

n+

jpav

p-

Body

Epi

Source Gate

Drain

Emitter

B

A



[ ])exp(/)( )(2)(kT

qbaseiW

TkTnDiff

nBEpBE

Base

n NTnj ΦΦµ −−⋅ ⋅⋅=

avpavSCRBnBDiffnDiff

BRcell

AjVTMAj

tLVII

⋅+⋅⋅≈

⋅−=

),(0

),( SCRApApDrainpav VTMjj ⋅=

0;)( =≈⋅≈ −⋅ SourcenBENTqW

pavpBE VjBodyp

av ΦΦ µ

fDiffnDiffDSVB TtAjVcT +⋅⋅⋅⋅= −12

solution unstable

0TI

⇒

>∂∂⇒>>>

⋅⋅⋅⋅=⋅=

∂∂

−∂

∂∂

∂∂

∂

}0,{

1

Tj

pavnDiff

DiffnDiffDSVTj

tT

Tj

dtdj

nDiff

nDiffnDiffnDiff

jj

AjVc

n+

n-

p+

A

B

-jnDiff

n+

jpav

p-

Body

Epi

Source Gate

Drain

WBase

Wav

Emitter

C

C'

Analytical Modelling Approach• UIS stress causing failure (quantitative)

After heat at B hasbecome significant:

since



Numerical Device Simulation: constant current pulsesMotivation: Validation of the analytical model

Only one cell is simulated

time [s]

Tem

pera

ture

time [s]

Volta

ge

Kink in temperaturerelocation of the hot spot!



Numerical Device Simulation: constant current pulses

electron current density -formation of filament

temperature levels -relocation of the ‘hot spot’



• Electron current from source- contact rises rapidly after relocation of hot spottemperature ‘kink’ indicates onset of current instability

Numerical Device Simulation: constant current pulses

n+

n-

p+

A

B

-jnDiff

n+

jpav

p-

Body

Epi

Source Gate

Drain

WBase

Wav

Emitter

C

C'

Maximum device temperature,currents at source- contact vs. time

(I=1mA)



• Hole quasiFermi potential biasing emitter-base junction reaches only 0.2 VNumerical Device Simulation: constant current pulses

n+

n-

p+

A

B

-jnDiff

n+

jpav

p-

Body

Epi

Source Gate

Drain

WBase

Wav

Emitter

C

C'

temperature and quasiFermi potentials at emitter- base junction vs. time

(I=1mA)



Numerical Device Simulation: constant current pulses - discussion

Analysis of electron diffusion current:

[ ])exp(/)()( )(2kT

qbasei

Basen

nDiffnBEpBENTnW

TDj ΦΦ −− ⋅⋅=

•Emitter- base junction is forward-biased with 0.2 V [ Φ pBE ] only

5.0)()( −∝⋅= TTkTTD nn µ•Diffusion coefficient decreases with temperature:

)exp()( 32kT

Ei

gTTn −⋅∝•But: Intrinsic density rises:

ni(T) is dominating factor for the increase of jnDiff



Numerical Device Simulation: UIS stress

current + voltage transientswith and without UIS-failure

electron, hole current + voltage transientswith and without UIS - failure



Conclusions

• Analytical modelling approach for the failure of DMOS PowerTransistors under UIS stress conditions has been proposed

• Electrothermal device simulation of a single transistor celldemonstrates the appearance of a current filament due to UIS stress

• From the analytical model it can be deduced that filamentformation implies unstable current crowding in one cell,leading eventually to device failure and damage

• ni(T) is the decisive factor for filament formation

A. Icaza Deckelmann et al. - ESSDERC ‘02


Outlook

• Experimental corroboration of the model is still missing

• Accurate high-temperature physical models are still to be implementedin the simulation in order to quantitatively predict UIS-failure levels

A. Icaza Deckelmann et al. - ESSDERC ‘02


Failure Current square Pulse

Measurementy = 30,535x-0,4528

R2 = 0,9976

Simulationy = 60,792x-0,584

R2 = 0,9993

1

10

100

10 100 1000Time to Failure[us]

Cur

rent

per

Dev

ice

Are

a [A

/mm

2 ]

Meas@300K

Sim@300K

Potentiell (Meas@300K)

Potentiell (Sim@300K)

UIS - Failure of DMOS Power Transistors A. Icaza Deckelmann et al. -ESSDERC ‘02

UIS - Failure of DMOS Power Transistors · UIS - Failure of DMOS Power Transistors A. Icaza Deckelmann 1, Gerhard Wachutka , F. Hirler2, J. Krumrey2 1Institute for Physics of Electrotechnology

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