UCC28722/UCC28720 5W USB BJT Flyback Design Example · Application Report SLUA700 –January 2014 1 UCC28722/UCC28720 5W USB BJT Flyback Design Example Michael O’Loughlin Senior

Application Report

SLUA700 –January 2014

1

UCC28722/UCC28720 5W USB BJT Flyback Design Example

Michael O’Loughlin Senior System Solutions Engineer

Introduction:

In USB and isolated low power converter designs-quasi resonant and discontinuous conduction mode

flyback converter topologies are a popular choice, due to their low parts count and relatively low cost.

To reduce the cost even further, TI has developed a quasi-resonant/discontinuous current mode flyback

controller with primary-side control. This removes the need for optocoupler and TL431 feedback

circuitry reducing the cost of these low power designs even more. The control methodology uses a

combination of primary peak current amplitude modulation (AM) and frequency modulation (FM) to

regulate the output current and voltage please refer to data sheet [1] for controller details. This design

example is a theoretical design that shows how to use the UCC28722 in a 5W USB application. The

calculations were used to design the UCC28720EVM-212 reference design [2]. Note the UCC28722 is

cost reduced version of the UC28720. To reduce the cost of the UCC28722 the internal startup circuit

was removed. This device requires a trickle charge resistor from the bulk input voltage during power

up.

Design Specifications:

Description Minimum Typical Maximum Units

RMS Input Voltage 90 (VINMIN) 115/230 265 (VINMAX) V

No Load Input Power 50 (PINL) mW

Output Voltage 4.75 5 (VOUT) 5.25 V

Output Voltage Ripple 100 (VRIPPLE) mVpp

Output Load Step (0.1 to 0.6A), (0.6 to 0.1A)

4.1 (VOTRM) 6.0 V

Output Current 1(IOUT) A

Switching Frequency 74 kHz (fMAX) kHz

Full Load Efficiency 73(η) 74 %

Table 1, Design Specifications

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2 UCC28722/UCC28720 5W USB BJT Flyback Design Example

Functional Schematic:

VIN

DA

DB

DC

DD

2

6

5

3

4

1

UCC28722

CS

VDD DRV

GND CBC

T1

T1

VS

VOUT+

VOUT-

CA CB

RS1

RS2

RCBC

RLC

RF1

CDD

DZ RS

CS

COUT

RCSRG2

RG1

RZ

RT

10.0k

DE

DF

DG

10

10k

4.7uF

22.5

NP NS

NA

470uH

QA1nF

RL

DF

30V

Note RT is not required on UCC28720

Figure 1, UCC28722 5W Offline Flyback Functional Schematic

Selecting RCBC Resistor:

In this design cable compensation was not used and resistor R8 was not populated.

Please refer to the data sheet on how to setup cable compensation [1].

Initial Power Budget:

To meet the efficiency (η) goal an initial power loss budget (PBUDGET) needs to be set.

WAVIVP OUTOUTOUT 515

WPP

P OUTOUT

BUDGET 849.1

Bridge Rectifier Selection (DA ..DD):

For this design a 600V, 0.8A, bridge rectifier from Diodes Incorporated was chosen for the bridge

rectifier diode (DA.. DD), part number HD06.

VVFDA 1 , forward voltage drop of bridge rectifier diode (VFDA)

SLUA700

UCC28722/UCC28720 5W USB BJT Flyback Design Example 3

mA

V

W

V

P

I

INMIN

OUT

DA 85

22

90

75.0

5

22

, bridge rectifier average diode current (IDA)

mWIVP DAFDADA 85 , estimate power dissipated in bridge rectifier diode (PDA)

Estimate remaining power budget based on bridge rectifier loss.

WPPP DABUDGETBUDGET 68.12

Transformer Calculations (T1):

Transformer demagnetizing duty cycle (DMAG) is fixed to 42.5% based on the UCC28720/2 control law

methodology [1].

425.0MAGD

TR is the estimated period of the LC resonant frequency at the switch node.

usTR 2

Calculate maximum duty cycle (DMAX):

501.02

274425.01

21

skHz

TfDD R

MAXMAGMAX

Calculate transformer primary peak current (IPPK) based on a minimum flyback input voltage. This

calculation includes a factor of 0.6 to account for the reduction in flyback input voltage caused by the

ripple voltage across the input capacitors (CA and CB).

mAV

W

DV

PI

MAXINMIN

OUTPPK 358

47.06.029075.0

52

6.02

2

Selected primary magnetizing inductance (LPM) based on minimum flyback input voltage, transformer,

primary peak current, efficiency and maximum switching frequency (fMAX).

mH

kHzmA

W

fI

P

LMAXPPK

OUT

PM 44.174350

75.0

522

22

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4 UCC28722/UCC28720 5W USB BJT Flyback Design Example

VV SATCEQA 1)(_ , estimated voltage drop across transistor during conduction

VVRCS 78.0 , voltage drop across current sense resistor

VVDG 6.0 , estimated forward voltage drop across output diode

Calculate transformer turns ratio primary to secondary (a1) based on volt-second balance.

Note in the following equation LSM is secondary magnetizing inductance.

7.156.02 )(_

1

DGOUTMAG

RCSSATCEQAINMINMAX

SM

PM

S

P

VVD

VVVD

L

L

N

Na

VV onDDMIN 15.8)( , UCC28722 minimum VDD voltage before UVLO turnoff.

VVDE 6.0 , estimated auxiliary diode forward voltage drop

VV INITOUT 2_ , Minimum voltage on the output when adapter is connected to a device

with a depleted battery.

Calculate transformer auxiliary to secondary turns ratio (a2)

37.3_

2

DGINITOUT

DEDDMIN

S

A

VV

VV

N

Na

Transformer primary RMS current (IPRMS)

mAD

II MAXPPKPRMS 146

3

Transformer secondary peak current RMS current (ISPK)

ADV

PI

MAGOUT

OUTSPK 71.4

2

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UCC28722/UCC28720 5W USB BJT Flyback Design Example 5

Transformer secondary RMS current (ISRMS)

AD

II MAGSPKSRMS 77.1

3 , transformer secondary RMS current

Estimate power dissipated by the UCC28722 IC (PIC)

VaVV OUTDD 83.162 , Estimated VDD

mAIRUN 2 , Typical IC run current

mAI MAXDRS 37)( , Average Maximum Drive Current

mAI MINDRS 19)( , Average Minimum Drive Current

mADII

I MAX

MINDRSMAXDRS

AVGDRS 142

)()(

)(

, Average Base Drive Current

mWIIVP AVGDRSRUNDDIC 270)(

Calculate auxiliary winding peak current (IAPK)

mADaVV

PI

MAGDEOUT

ICAPK 67

)(

2

2

Calculate auxiliary winding RMS current (IARMS)

mAD

II MAGAPKARMS 25

3

For this transformer we allow for 3% efficiency loss from the transformer (PT1)

mWPP OUTT 15003.01

Recalculate remaining power budget

WPPP TBUDGETBUDGET 26.11

A Wurth Electronik transformer was designed for this application, part number 7508110151, which has

the following specifications:

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6 UCC28722/UCC28720 5W USB BJT Flyback Design Example

a1 = 15.42

a2 = 3.2

mHLPM 5.1

uHLLK 20 , primary leakage inductance

Input Capacitor Selection (CIN = CA + CB):

Calculate input capacitor charge time (tCH) based on 40% input capacitor ripple voltage.

msHz

V

VV

tINMIN

INMININMIN

CH 4.3474

2

6.022sin1 1

Calculate flyback average primary current (IPT1) during input capacitor discharge.

mAV

P

V

P

I INMIN

OUT

INMIN

OUT

PT 722

6.0221

Calculate total input capacitance (CIN) based on minimum flyback input voltage and 40% ripple voltage

across the input capacitor.

msHz

TRL 11472

1

, longest period of the rectified line voltage

VVV INMININRIPPLE 9.504.02 , input ripple to the flyback converter

uF

V

tTIC

INRIPPLE

CHRLPT

IN 101

uFC

CC INBA 5

2

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UCC28722/UCC28720 5W USB BJT Flyback Design Example 7

Calculate input capacitor (CA) RMS current (IC_ARMS) based on 40% input capacitor ripple voltage.

mAt

VCCI

CH

INMINBACINP 311

4.02)(2

, peak input capacitor charge current (ICINP)

mAI

T

tTI

T

tII PT

RL

CHRLCINP

RL

CHCINPRMSCA 82

23232

2

1

22

_

Estimate of capacitor CB‘s low frequency (1/TRL) RMS current ( LFRMSCBI _ )

RMSCALFRMSCB II __

Estimate of CB‘s high frequency RMS current (ICB_HFRMS)

mAD

ID

II MAXPPK

MAXPPKHFRMSCB 116

23

22

_

Estimate of CB’s total RMS current (ICB_RMS)

mAIII HFRMSCBLFRMSCBRMSCB 1422

_

2

__

For this design 4.7uF, 400V electrolytic capacitors, from Nichicon part number UVR2G4R7MPD were

chosen for the design.

uFCC BA 7.4

These capacitors had a measured ESR of 5 ohms at 74 kHz

ESRCA = ESRCB = 5Ω

Recalculate remaining power budget based on power dissipation by the ESRs in the input capacitors.

WESRIESRIPP CBRMSCBCARMSCABUDGETBUDGET 126.12

_

2

_

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8 UCC28722/UCC28720 5W USB BJT Flyback Design Example

Filter Inductor (LA):

Filter inductor (LA) is used for EMI filtering. In this design it is just a place holder and the design has

not been optimized for EMI. 470uH inductor from Bourns was chosen, part number RLB0608-471KL.

This inductor has a DCR of 6.5 ohms.

5.6DCR

Recalculate power budget based on DCR losses

WDCRIPP PRMSBUDGETBUDGET 987.02

Fusible Resistor (RL):

To limit the inrush current during power and for safety a 10 ohm, 3W fusible resistor from Bourn, part

number PWR4522AS10R0JA was placed at the input of this design.

10LR

Recalculate power budget based on estimated RL losses

WRV

PPP L

INMIN

OUTBUDGETBUDGET 929.0

2

Current Sense Resistor (RCS):

For this design 2.15 ohm resistor was selected based on a nominal maximum current sense signal of

0.78V.

ohmI

VR

PPK

CS 15.22.278.0

mWRIP CSPRMSRCS 462

, nominal current sense resistor power dissipation

Recalculate power budget

WPPP RCSBUDGETBUDGET 883.0

Select Output Diode (DG):

Calculate diode reverse voltage (VRDG)

Va

VVV INMAXOUTRDG 3.291

21

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UCC28722/UCC28720 5W USB BJT Flyback Design Example 9

Calculate peak output diode (IDGPK)

AII SPKDGPK 7.4

For this design we selected a 3A, 40V schottky rectifier with a forward voltage drop (VFDG) of 0.31V.

VVFDG 31.0

Estimated diode power loss (PDG)

OUT

FDGOUTDG

V

VPP 310mW

Recalculate power budget

mWPPP DGBUDGETBUDGET 573

Select Output Capacitors (COUT):

Select output ESR based on 90% of the allowable output ripple voltage

mA

mV

I

VESR

SPK

RIPPLECOUT 19

7.4

9.01009.0

For this design the output capacitor (COUT) was selected to prevent VOUT from dropping below the

minimum output voltage during transients (VOTRM).

VVOTRM 1.4

mFVV

V

Pms

COTRMOUT

OUT

OUT

OUT 1.12

2

For this design example two 680uF capacitors were selected in parallel on the output, with an ESR of 7

mΩ each.

mFuFCOUT 36.16802

mm

ESRCOUT 5.32

7

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10 UCC28722/UCC28720 5W USB BJT Flyback Design Example

Estimate total output capacitor RMS current (ICOUT_RMS)

AV

PDII

OUT

OUTMAGSPK

RMSCOUT 46.13

22

_

Estimate total output capacitor loss (PCOUT)

mWESRIP COUTRMSCOUTCOUT 5.72

_

Recalculate power budget

mWPPP COUTBUDGETBUDGET 565

Select BJT QA:

For this design we had chosen 800V 1A transistor with the following characteristics:

VV satCE 6.0)( , Transistor Collector Emitter Saturation

VV satBE 6.0)( , Base Emitter Saturation

nstr 140 , Estimated collector rise time

Estimate transistor losses (PQA):

VVV

VV FDAINRIPPLE

INMINFLY 8.9922

2 , Average Minimum Input Voltage

mAIID

IMAXDRSMINDRSMAX

AVGDRS 142

)( )()(

)(

, Average Base Drive Current

mADI

I MAXPPKAVGCE 90

2)(

, Average Collector Emitter Current

mWftaVVV

IVIVIP MAXrDGOUTFLY

PPKSATCEAVGCESATBEAVGDRSQA 3732

1)()()()()(

Recalculate the power budget

mWPPP QABUDGETBUDGET 192

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UCC28722/UCC28720 5W USB BJT Flyback Design Example 11

Setup Zener Clamp to Protect FET QA:

VVZ 82 , Zener Clamp Voltage (DZ)

VV MAXCE 800_ , FET maximum drain to source voltage

VVVV INMAXMAXCECLAMP 2.34529.0_ , Available Clamp Voltage to Protect FET QA

7346.0

PPK

ZCLAMPS

I

VVR

Select a standard resistor for the design.

750SR

Estimate Zener Clamp/LLK power dissipation (PLK)

mW

fILP MAXPPKLPK

LLK 952

2

Recalculate power budget

mWPPP LLKBUDGETBUDGET 97

Trickle Charge Resistor (RT):

To reduce no load power losses RT and to keep no load power to a minimum, three 1.47MΩ are used in

series for RT

MMRT 41.4347.1

mW

R

VP

T

INMAXRT 32

22

, Total trickle charge resistor power dissipation

Recalculate power budget

mWPPP RTBUDGETBUDGET 65

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12 UCC28722/UCC28720 5W USB BJT Flyback Design Example

VDD Capacitor Selection (CDD):

VV ONVDD 21)( , Typical VDD turn-on threshold

VV OFFVDD 7.7)( , Typical VDD turnoff threshold

uF

IVV

VCIIC

OUTOFFVDDONVDD

INITOUTOUTRUNAVGDRS

DD 3.3)( )()(

_)(

Select standard capacitor value for the design

uFCDD 7.4

Note after CDD has been charged up to the device turn on threshold (VVDD(on)), the UCC28722 will

initiate three small gate drive pulses (DRV) and start sensing current and voltage. (Please refer to figure

2) If a fault is detected such as an input under voltage or any other fault, the UCC28722 will terminate

the gate drive pulses and discharge CDD to initiate an under voltage lockout. This capacitor will be

discharged with the run current of the UCC28722 (IRUN) until the VDD turnoff (VVDD(off)) threshold is

reached. Note the CDD discharge time (tCDDD) from this forced soft start can be calculated knowing the

controller run current (IRUN) without out gate driver switching and the controller’s VDD turnoff

threshold (VVDD(off)) and the following equations. If no fault is detected, the UCC28722 will continue

driving QA and controlling the input and output currents and a soft start will not be initiated.

ms

IR

V

VVCt

RUN

T

INMAX

offVDDonVDD

DDCDDD 332

)()(

, Discharge for soft start Reset

VDD

0VDRV

VVDD(on) =21V

VVDD(off) =7.7V3 Initial DRV Pulses After VDD(ON)

Figure 2, VDD and DRV at Startup with Fault

SLUA700

UCC28722/UCC28720 5W USB BJT Flyback Design Example 13

Select VS voltage divider (RS1, RS2):

uAI runVSL 225)( VS Line-sense run current

Note RS1 so the converter will go into under voltage lockout when the input is below 80% of the

minimum specified input voltage.

kI

Va

a

RrunVSL

INMIN

S 9.93

8.02

)(

1

2

1

Select a standard resistor for the design

kRS 5.821

Calculate RS2

k

R

VaVV

VR

S

DGOUTS 7.23

4

4

1

22

Select a standard resistor for the design

kRS 4.272

Calculate VS divider power dissipation (PVS)

mWRR

aVVDP

SS

DGOUTMAX

VS 2.121

2

2

Select auxiliary diode (DE) for this design that had a forward voltage drop (VDE) of 0.6V.

VVDE 6.0

VVaVVV DEDGOUTDD 3.172 , UCC28700 supply voltage at VDD

Va

aVVV INMAXDDRDE 952

1

2 , maximum reverse voltage across VDE

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14 UCC28722/UCC28720 5W USB BJT Flyback Design Example

Calculate DE power dissipation (PDE)

mWVIIP DEAVGDRSRUNDE 6.9)( )(

Recalculated power budget

mWPPPP DEVSBUDGETBUDGET 54

Preload Resistor Selection (RZ):

To keep the output voltage from climbing at no load a pre-load resistor is required. This is generally a

trial an error process. For this design the preload resistor that kept the output regulated under no load

conditions was 10 kΩ.

KRZ 0.10

Calculate RZ power dissipation (PRZ)

mWR

VP

Z

OUTRZ 5.2

2

Recalculated power budget and there is 52 mW of margin left in the power budget to meet the efficiency

requirements of the design. Note in production designs, more margin might be required. Also note

these calculations are estimations and the final design may need to be adjusted to hit efficiency

requirements and regulation requirements.

mWPPP RZBUDGETBUDGET 52

Internal Blanking

The UCC28722 controller regulates the output voltage by sensing the auxiliary (Aux) winding. This

removes the need for opto isolator feedback scheme reducing the cost of the design. However, this

voltage control feedback scheme is susceptible to leakage spikes at the switch node that occur in most

flyback converters. This signal is coupled through the turns ratio of the transformer (T1) and shows up

on the Aux winding during tLK_RESET , please refer to figure 3 for details.

To help insure the leakage spike on the Aux winding does not cause a control issue the UCC28720/22

blanks (tB) the Aux signal to the controller for 600 ns to 2.2 us depending on loading. Please see the

data sheet details [1]. Note the ringing on the auxiliary winding needs to be less than 100mV peak

to peak after tB. Snubbing circuitry on the secondary and/or auxiliary winding may be required to

reduce ringing.

SLUA700

UCC28722/UCC28720 5W USB BJT Flyback Design Example 15

Aux/DE Cathode

RCS

DRV

0V

tB

0V

tLK_RESET

VS Samples Aux Voltage for Control

QA on

QA off

Aux Ringing after tB < 100mV

Figure 3, Auxiliary Winding VS Blanking

To ensure the leakage spike does not cause control issues it needs to be dissipated before the Aux

blanking (tB) has terminated. The tank frequency (fLC) between the switch node capacitance (CSWN) and

the transformer leakage inductance (LLK) should be greater than 1MHz.

SWNLK

LCCL

f

2

1

MHzns

fLC 15002

1

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16 UCC28722/UCC28720 5W USB BJT Flyback Design Example

Select line compensation resistor RLC:

Resistor RLC provides offset to the peak current comparator input (CS). RLC is adjusted to terminate the

gate drive signal (B) early to prevent primary current (A) from over shooting [1]. Please refer to figures

4 and 5 for details.

Figure 4, Peak Current Limit Comparator Figure 5, CS(A), QAg(B), VQADS Signals

25LCK , Line Compensating Ratio [1]

Calculate RLC initial resistor setting based on QADS rise and fall time (tr)

kL

atRRKR

PM

rCSSLCLC 3.6

11 , Starting Point for RLC

In circuit adjust RLC so the maximum output current is (IOUT). For this design RLC was set to 1 kΩ.

kRLC 1

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UCC28722/UCC28720 5W USB BJT Flyback Design Example 17

Estimate no load input power (PNL):

HzfMIN 650 , Minimum operating frequency

uAIWAIT 95 , VDD input current at 1 kHz operating frequency [1]

mW

f

fVIIVIP

MAX

MINDDDRSDRS

DDWAITVDD 9.52

(min)(max)

, Estimated UCC28722 power dissipation

Estimate switching losses (PSWFM) at high line at fMIN

mW

ftI

aVVVPMINr

PPK

VDGOUTINMAXSWFM 6.12

31

uW

fI

L

PMIN

PPKLPK

LLK 922

3

2

, estimate of leakage power dissipation at no load

The estimated no load input power (PNL) is roughly 42 mW.

mWPPPPPP LLKRTRZSWFMVDDNL 42

5W EVM Schematic:

Figure 6, UCC28720EVM-212 Schematic

SLUA700

18

64%

66%

68%

70%

72%

74%

76%

78%

10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

% E

ffic

ien

cy

Output Power

Efficiency

Efficiency @ 115V RMS

Efficiency @ 230V RMS

Figure 7, Efficiency

REFERENCES

[1] UCC28722 Data Sheet, Constant-Voltage, Constant-Current Controller with Primary Side

Regulation, SLUSBL7, December 2013, http://www.ti.com/lit/gpn/ucc28722

[2] Using the UCC28722EVM-212, UCC28700EVM-212 5W USB Adapter, SLUU968, July 2012,

http://www.ti.com/litv/pdf/sluua92

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