Uart 16550

The 16550 UART• Universal Asynchronous Receiver

Transmitter • Baud rates up to 1.5 M bauds

(signal elements/s)• = Data rate (bps) for binary data• Compatible with Intel and other

Processors• Includes:

- A programmable baud rate generator - 16-byte FIFO buffers at input and output to help processor deal with data bursts

Asynchronous Serial Data Communication

• Data sent asynchronously using the format illustrated below

• We often use one start bit and one stop bit to frame the data, which is usually 8-data bits with or without parity

Usually a byte of data

The 16550 UART: Functional Description

40 pin DIP

• Totally independent Transmitter (TX) and Receiver (RX) Sections

• This allows communication in the following modes: - Simplex: Only TX or RX is used (one direction all the time)- Half Duplex: TX then RX (two directions at different times)- Full Duplex: TX and RX simultaneously (two directions at the same time)

• Can control a modem using six signals, e.g. #DSR (Data Set Ready) input, #DTR (Data Terminal Ready) output….Here the UART is the data terminal and modem is the dataset.

The 16550 UART: Typical Configuration

UART

PControl

Receiver

TransmitterSerialComm.Link

SIN

SOUT

Memory

Data

DMA Data Transfers:Memory UART Directly Without going through the P

16-byte FIFO Input Buffer

16-byte FIFO Output Buffer

PS

PS

Serial to ParallelOr Parallel to SerialConverters

The 16550 UART: Pin Assignments

40 pin DIP

3 I/O Address bits from Processor(Table 11-5)

Baud rate Clock output

Chip Select Inputs(Multiple I/Ps)

Modem Interface: Inputs & Outputs

Data bus to Processor

Interrupt Processor

Master Reset (tie to P Reset I/P)

Serial data INput from RX

Serial data OUTput to TX

Receiver Clock input

Read & Write Control inputs from P(with complements for versatility

User defined outputs

Crystal orExternal Clock Input

TX ready for data. Put data intoUART by DMA

RX ready with data. Take data fromUART by DMA

Address Strobe (not needed with Intels)

UARTs in the PC

• Used to control the COM ports of the PC

- UART at I/O address 3F8-3FF: COM Port 0

- UART at I/O address 2F8-2FF: COM Port 2

Programming the UARTTwo Stages:

a. Initialization Dialog: (Setup)- Follows RESET- Has two steps:

1. Program the line control register (Set asynchronous transmission parameters:

# of stop, data, and parity bits, etc.) 2. Program the baud rate generator for the required

baud rate

b. Operation Dialog: (Actual Communication)

A2 A1 A0 Function

0 0 0 Receiver buffer (read data from RX) and transmitter holding (write data to TX). Also write LS byte of baud rate divisor

0 0 1 Interrupt enable. Also write MS byte of baud rate divisor

0 1 0 Interrupt identification (read) and FIFO control Register (write)- Used for operation dialog programming

0 1 1 Line control Register (Write into the line control register to program asynchronous communication at initialization)

1 0 0 Modem control

1 0 1 Line status LSTAT (Read the line status register to see if TX or RX are ready and to check for errors )

1 1 0 Modem status

1 1 1 Scratch

The 8 I/O Byte Locations on the UART

1. Programming the Line Control RegisterI/O Address: A2 A1 A0 = 011

Data Length = 5 bits

Data Length > 5 bits

Parity ControlSee next slide

To allow programmingThe baud rate generator

See Table on next slide

A break is a minimum of 2 frames of 0’s

a. InitializationDialogProgramming

DL bit must be setbefore you can load the divisorfor the baud generator

ST P PE Function

0 0 0 No parity

0 0 1 Odd parity

0 1 0 No parity

0 1 1 Even parity

1 0 0 Undefined

1 0 1 Send/receive 1 (send 1 in place of the parity bit)

1 1 0 Undefined

1 1 1 Send/receive 0 (send 0 in place of the parity bit)

The 3 Parity Control Bits in the Line Control Register

Baud Rate Divisor Value

110 10,473

300 3840

1200 920

2400 480

4800 240

9600 120

19,200 60

38,400 30

57,600 20

115,200 10

• Baud rate is programmed by loading a 16-bit divisor for the crystal oscillator (or external input) frequency into the I/O port addresses:

{A2 A1 A0} = 000: LS Byte of divisor {A2 A1 A0} = 001: MS Byte of divisor

• Divisor value is determined by the Oscillator frequency and the baud rate required:

Divisor = Oscillator frequency / (16 * Baud rate)

Table shows divisor values required for various baud rates for osc frequency = 18.432 MHz

2. Programming the Baud rate Generator

(Active Low)

;Initialization dialog for Figure 11-45;Baud rate 9600, 7 bit data, odd parity, 1 stop bitLINE EQU 0F3H ; A2 A1 A0 = 011 for the Line Control RegisterLSB EQU 0F0H ; A2 A1 A0 = 000 for LSB of divisorMSB EQU 0F1H ; A2 A1 A0 = 001 for MSB of divisorFIFO EQU 0F2H ; A2 A1 A0 = 010 for the FIFO Control Register

INIT PROC NEARMOV AL,10001010BOUT LINE,AL ; Enable Baud rate programming See slide 108

; program Baud 9600; Divisor = 120d (see Table on slide 110)

MOV AL,120 ; LSB of divisorOUT LSB,ALMOV AL,0 ; MS Byte of divisorOUT MSB,ALMOV AL,00001010B ;program 7 bit data, oddOUT LINE,AL ;parity, 1 stop bit

;(& disable baud rate programming?)MOV AL,00000111B ;enable transmitter and receiverOUT FIFO,AL ;by writing into the FIFO control Reg.RET

INIT ENDP

Must write this into FIFO Registerto enable communicationand operation dialog programming

16550 FIFO Control Register (Write)

111

I/O Address: A2 A1 A0 = 010

Required to enableactual communication(Operation Dialog)

16550 Line Status Register (LSTAT)I/O Address: A2 A1 A0 = 101

Before writing datafor transmission, Ensure TX is ready to take it [TH (bit 5) = 1]

Before reading datafrom receiver, ensureRX has data [DR (bit 1) = 1]

Error status bitsAny being 1 indicatesAn error

b. OperationDialogProgramming

;A procedure that transmits the byte in AH serially ;via the 16650 UART

LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)

DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)

SEND PROC NEAR USES AX.REPEAT ;test the TH bit (bit 5) in to see if TX is available

IN AL,LSTATTEST AL,20H ;20H is the mask for the TH bit

.UNTIL !ZERO?MOV AL,AHOUT DATA,AL ;send data to TXRET

SEND ENDP

(LSTAT)

; Procedure receives byte from UART into AL if no comm. error; If error detected, it load Al with ‘?’ as an alert

LSTAT EQU 0F5H ; The Line status register (LSTAT) (A2 A1 A0 = 101)

DATA EQU 0F0H ; TX/RX Data Register at (A2 A1 A0 = 000)

REVC PROC NEAR.REPEAT

IN AL,LSTAT ;test DR bitTEST AL,1

.UNTIL !ZERO?TEST AL,0EH ;test for any error.IF ZERO? ;no error

IN AL,DATA ;Read RX Data Register into AL.ELSE ;any error

MOV AL,’?’ ;Put “?” in AL to indicate error.ENDIFRET

RECV ENDP