Two Wire Interface TWI - Milwaukee School of … Wire Interface •TWI Timing • R/W bit indicates a read or write operation is to follow • Read is active high • ACK • The master

Two Wire InterfaceTWI

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Two Wire Interface

• ATmega Block Diagram

• Two Wire Interface

aka TWI

• Nearly identical to I2C• I2C is a Phillips Registered

Name

3 © tjEE 2920 – Fall 2016

Two Wire Interface

• Overview

• 8 bit synchronous shift register used to communicate externally

• 9 bit total communication packet• uni-directional

• Most often used to communicate with peripherals• displays, sensors, converters

• Supports multiple masters and multiple slaves

• 4 modes of operation• Master Receive• Master Transmit• Slave Receive• Slave Transmit

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Two Wire Interface

• Overview

• Open drain configuration• outputs only pull down

• pull up resistors or current sources pull up

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Two Wire Interface

• TWI Timing

• SDA – data line

• SCL – clock line

• Data must be valid during the entire positive clock cycle time

Note: data changes occur during SCL low

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Two Wire Interface

• TWI Timing

• Special timing requirements for

• start transmission

• stop transmission

• repeated start transition• master does not relinquish the bus in this mode

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Two Wire Interface

• TWI Timing

• Addressing• Indicate which slave to transmit to or receive from by first

transmitting the “address” of the desired device

• Often this value is hardwired via external pins on the slave device

• 7 bits for each address

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Two Wire Interface

• TWI Timing

• R/W bit indicates a read or write operation is to follow• Read is active high

• ACK• The master drives the data bus from start through the R/W bit and

then releases the bus

• The slave then pulls down the bus in the last clock cycle to indicate a completed transmission

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Two Wire Interface

• TWI Timing

• ACK – cont’d• If the master fails to see the slave pull down the bus in the 9th clock

cycle (NACK)• Transmission failed

• Some sort of error action is required

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Two Wire Interface

• TWI Timing

• Data packet• After getting an ACK on the address – data can be sent

• 8 bits of data

• 1 bit for a data ACK

• This can be repeated many times

11 © tjEE 2920 – Fall 2016

Two Wire Interface

• Implementation

• Bus Interface Unit• creates bus signals

• Address match unit• determines if this device is

beingaddressed

• Bit rate generator• derives the clock from the

systemclock

• Control Unit

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Two Wire Interface

• Implementation

• Two wire control register drives the modes and process• TWINT – interrupt flag – set at the end of each action• reset by writing a 1 to it or by the ISR

• TWEA – enable ACK – enables slave mode and receive mode

• TWSTA – start – causes a start to be transmitted

• TWSTO – stop – causes a stop to be transmitted

• TWWC – write collision flag – set when data is written to the register when the interrupt flag is low

• TWEN – enable the TWI

• TWIE – enable interrupts – ISR

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Two Wire Interface

• Implementation

• Bit Rate

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Two Wire Interface

• Implementation

• Status Register• Current status

• Data Register• R/W data

• Slave Address Register

• TWGCE – global callenable (0x00)

• Slave Mask Register• when set to 1 – the

corresponding bit is NOT used to determine a match

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Two Wire Interface

• Implementation

• Interrupt driven process (internal to the TWI)

• Next step is initiated by clearing the interrupt flag• All registers must be set before this happens

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Two Wire Interface

• Operation – Master Transmit

• To initiate a start

• NOTE: writing a 1 to TWINT clears the flag

clearing the flag initiates the next action

wait for reset flag & check status

• Write address + W

• Clear the reset flag transfer

wait for reset flag & check status

• Write data

• Clear the reset flag transfer

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Two Wire Interface

• Operation – Master Transmit –cont’d

wait for reset flag & check status

• Write data (repeat as needed)

• Clear the reset flag transfer

wait for reset flag & check status

• Send STOP

• Clear the reset flag transfer

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Two Wire Interface

• Operation – Master Transmit

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Two Wire Interface

• Operation

• Master Receive, Slave Transmit, Slave Receive

• All very similar

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Two Wire Interface

• Example code

#include <avr/io.h>

void TWI_error(uint8_t val){;}

void TWI_master_transmit(uint8_t slv_addr, uint8_t data){//// Two wire master transmit function//

// Send Start// clear interrupt to start TWI hardware// Enable TWI, Send StartTWCR = (1 << TWINT) | (1 << TWSTA) | (1 << TWEN);

// wait for start transmission to complete// wait for interrupt flag to be setwhile (!(TWCR & (1 << TWINT))){;}

// Was start transmission successful// check status codeif ((TWSR & 0xF8) != 0x08){TWI_error(TWSR);}

// Send slave address and Write// Load slave address into data reg// set write - "0"// enable twi and clear interrupt to start processTWDR = slv_addr;TWCR = (1 << TWEN) | (1 << TWINT);

// wait for address transmission to complete// wait for interrupt flag to be setwhile (!(TWCR & (1 << TWINT))){;}

// Was transmission successful// check status codeif ((TWSR & 0xF8) != 0x18){TWI_error(TWSR);}

// Send Data// load data into data reg// enable twi and clear interrupt to start processTWDR = data;TWCR = (1 << TWEN) | (1 << TWINT);

// wait for data transmission to complete// wait for interrupt flag to be setwhile (!(TWCR & (1 << TWINT))){;}

// Was transmission successful// check status codeif ((TWSR & 0xF8) != 0x28){TWI_error(TWSR);}

// Send stop// enable twi and clear interrupt to start process// set stop bitTWCR = (1 << TWSTO) | (1 << TWEN) | (1 << TWINT);

}