o-stage amplifier status test buffer – to be replaced with IRSX i signal • recent / final (hopefully) design uses load resistor and voltage gain stage for input; this is faster, lower noise, and more robustly stable • 3.5 V supply voltage to minimize power and to limit output to safe input range of IRSX ASIC 10× −9× 0.5 × typical PMT pulse @ 3200 V single photoelectron 200 ps risetime 8 mV peak (on 25 Ω load) typical output pulse (same conditions, different event) PMT pulse @ 3200 V 600 ps risetime 300 mV peak (to IRSX) G. Visser, Indiana Univ.
two-stage amplifier status. recent / final (hopefully) design uses load resistor and voltage gain stage for input; this is faster, lower noise, and more robustly stable 3.5 V supply voltage to minimize power and to limit output to safe input range of IRSX ASIC. G. Visser , Indiana Univ. - PowerPoint PPT Presentation
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Transcript
two-stage amplifier status
test buffer – to be replaced with IRSX
isignal
• recent / final (hopefully) design uses load resistor and voltage gain stage for input; this is faster, lower noise, and more robustly stable• 3.5 V supply voltage to minimize power and to limit output to safe input range of IRSX ASIC
new front board status • connects to boardstack via pogo pins (on boardstack, landing pads on front board) enables mating with misalignment tolerance• “radical” design of signal routing using thick multilayer board with blind holes decouples PMT and readout board pad locations (both sides have their firm constraints), and reduces routing length for improved high speed signal integrity
signal trace routing in progress (90% complete)
press-fit pin receptacle for PMT (shown on preamp test board)
below here is backup / for reference / for our detailed discussion as needed
iTOP two-stage preamp updateG. Visser / IU November 11th 2013 this is the “final” circuit configuration
except:• calibration signal path still t.b.d.• resistor values may change (dependent on pcb layout parasitics)
• DC coupled• signal current return through VREF plane, AC coupled to bottom of 2nd MCP• bury the signal lines in front and carrier board for shielding (from, e.g., digital crosstalk)
• 1st stage noninverting for lowest noise and more constant input impedance• gain = 10×
• 2nd stage inverting for required output polarity• inverting amp can also be used to sum in calibration signal (without degrading risetime of PMT signal)• gain = −9× (or less...)• 3.5V supply limits output swing to protect the ASIC
• test buffer – to be replaced with IRSX
isignal
578 ps risetime300 mV peak
amplified single-photoelectron pulses @ -3200 V
a typical pulse
risetime histogram (from scope)
arbi
trar
y sc
ale
– no
t cou
nts!
Tek DPO7254C
100 mV/div1.25 ns/div
roughly 3×105 gain (see later slide)
raw single-photoelectron pulse @ -3200 V
This is a somewhat larger than average pulse:
≈200 ps risetime≈500 ps width
Voltage on 25 Ω load (double-terminated cable)
The noise and bandwidth limitations of this scope are significant here. The true pulse is likely rather faster and quieter.
2 mV/div1.25 ns/div
pulse integral spectrum @ 3200V
two-stage amp
(Zgain = 3188 Ω)
direct to scope
(Zgain = 25 Ω)
• Gate = 11 ns• Some double pulses and afterpulses are counted here• Zgain above (used for X axis scale) are design values, not calibrated
roughly 3×105 gain(average charge)
pulse peak amplitude spectrum
3200V
3700V
coun
ts (l
inea
r sca
le)
at 3200V, 89% of pulses are >50 mV
pulse peak amplitude spectrum
coun
ts (l
inea
r sca
le)
JT0298 PMT
slew rate limitation
At the observed 600 ps small-signal risetime, this becomes an issue when pulse height >≈ 800 mV.There may be an extra “time walk” due to this for large pulses; needs consideration and/or avoidance.
3200V 3700V
noise (and gain flatness)
8 μV/div @ 1 MHz BW150 MHz/div
Note this is a linear scale (to better show gain/noise flatness).The peak at ~100 MHz is a local radio station.With −90× gain, the input referred noise is about 1.33 nV/sqrt(Hz).