TSW3000 Demo Kit (Rev. B) - TI

TSW3000 Demo Kit

User's Guide

November 2005

SLWU013B

TSW3000 Demo Kit

User's Guide

Literature Number: SLWU013B

March 2004–Revised November 2005

Contents

1 Demo Kit Configuration Options ................................................................................... 71.1 DAC Component.................................................................................................... 7

1.2 VComm Configuration.............................................................................................. 7

1.3 VCXO................................................................................................................. 7

1.4 VCO .................................................................................................................. 7

2 Block Diagrams .......................................................................................................... 92.1 System Block Diagram ............................................................................................. 9

2.2 Demo Kit Block Diagram........................................................................................... 9

3 Key Texas Instruments Components ........................................................................... 103.1 CDCM7005......................................................................................................... 10

3.2 DAC5687 ........................................................................................................... 10

3.3 TRF370x............................................................................................................ 10

3.4 TRF3750............................................................................................................ 10

4 Software Installation .................................................................................................. 105 Software Operation.................................................................................................... 10

5.1 CDCM7005 Software ............................................................................................. 11

5.2 TRF3750 Software ................................................................................................ 13

5.3 DAC5687 Software................................................................................................ 14

5.4 DAC5687 GUI Register Descriptions ........................................................................... 15

6 Board Setup.............................................................................................................. 176.1 Jumper Settings ................................................................................................... 17

6.2 Input/Output Connectors ......................................................................................... 18

6.3 Parallel Port ........................................................................................................ 18

6.4 DC Power Requirements......................................................................................... 18

7 Demo Kit Test Configuration....................................................................................... 187.1 Test Setup Block Diagram ....................................................................................... 19

7.2 Test Equipment.................................................................................................... 19

7.3 Calibration .......................................................................................................... 19

7.4 Test Specifications ................................................................................................ 19

8 Basic Test Procedure................................................................................................. 208.1 Initial Inspection ................................................................................................... 20

8.2 Engage Power Supplies .......................................................................................... 20

8.3 Program the CDCM7005 ......................................................................................... 20

8.4 Program the TRF3750............................................................................................ 20

8.5 DAC5687 Program ................................................................................................ 21

8.6 Carrier Suppression............................................................................................... 21

8.7 Sideband Rejection ............................................................................................... 23

9 Optional Configurations ............................................................................................. 259.1 External LO ........................................................................................................ 25

9.2 External Reference................................................................................................ 25

9.3 Monitor DAC Output .............................................................................................. 25

10 Filter Specifications ................................................................................................... 2610.1 Baseband Filter.................................................................................................... 26

SLWU013B–March 2004–Revised November 2005 Table of Contents 3

11 Layers and Schematics .............................................................................................. 2611.1 Bill of Materials .................................................................................................... 26

11.2 Layers............................................................................................................... 30

11.3 Schematics ......................................................................................................... 40

Contents4 SLWU013B–March 2004–Revised November 2005

List of Figures

1 System Block Diagram ...................................................................................................... 92 Demo Kit Block Diagram.................................................................................................... 93 TSW3000 Startup Screen ................................................................................................. 114 Default CDCM7005 SPI GUI.............................................................................................. 125 TRF3750 GUI - Main Menu ............................................................................................... 136 TRF3750 GUI - Advanced Menu ......................................................................................... 147 DAC5687 GUI .............................................................................................................. 158 Test System Block Diagram .............................................................................................. 199 Default DAC GUI With fDAC/8 Tone From NCO ........................................................................ 2210 Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments ................................... 2311 DAC GUI With Typical Settings To Minimize LO and Sideband ..................................................... 2412 Sideband and LO........................................................................................................... 2513 Top Layer.................................................................................................................... 3014 Top Layer (NH) ............................................................................................................. 3115 Layer 2....................................................................................................................... 3216 Layer 3....................................................................................................................... 3317 Layer 4....................................................................................................................... 3418 Layer 4 (NH) ................................................................................................................ 3519 Layer 5....................................................................................................................... 3620 Bottom Layer................................................................................................................ 3721 Bottom Silkscreen .......................................................................................................... 3822 Drill Drawing ................................................................................................................ 3923 Schematic - Page 1 ........................................................................................................ 4024 Schematic - Page 2 ........................................................................................................ 4125 Schematic - Page 3 ........................................................................................................ 4226 Schematic - Page 4 ........................................................................................................ 4327 Schematic - Page 5 ........................................................................................................ 4428 Schematic - Page 6 ........................................................................................................ 4529 Schematic - Page 7 ........................................................................................................ 46

SLWU013B–March 2004–Revised November 2005 List of Figures 5

List of Tables

1 Frequency Bands ............................................................................................................ 72 CDCM7005 Register Values.............................................................................................. 123 Jumper List.................................................................................................................. 174 Input/Output Connections ................................................................................................. 185 Demo Kit Specifications ................................................................................................... 196 Frequency Designations................................................................................................... 217 Bill of Materials ............................................................................................................. 26

List of Tables6 SLWU013B–March 2004–Revised November 2005

1 Demo Kit Configuration Options

1.1 DAC Component

1.2 VComm Configuration

1.3 VCXO

1.4 VCO

User's GuideSLWU013B–March 2004–Revised November 2005

TSW3000 Demo Kit

The TSW3000 Demo Kit can be configured in different ways to evaluate different components in differentfrequency bands. This section outlines the various component configurations. Based on the configuration,testing and board setup must be altered to accommodate the given components and features.

The TSW3000 Demo Kit is built for the DAC5687, although this Demo Kit can also support the DAC5686since the two devices are pin compatible. The procedures outlined in this document are primarily suited forthe DAC5687, but can be modified easily for the DAC5686 if desired.

The analog quadrature modulator requires a common-mode dc voltage of approximately 3.7 V. In order toutilize the dc-offset adjustment capabilities of the DAC568x for carrier suppression, it is imperative tomaintain a dc path from the DAC output to the modulator input. The common-mode voltage for themodulator is maitained with a passive resistor network that is designed to provide the proper operationpoint for the DAC568x and the TRF370x modulator. By design, in order to preserve the proper dc levels,the DAC gain should be kept at maximum (15), though deviation by a few steps is generally acceptablewith no degradation in performance.

The CDCM7005 requires a VCXO source to derive its output clock signals. The VCXO is at referencedesignator U10 on the back side of the board. The frequency of the VCXO can be changed to operate theDemo Kit with different clocking schemes for different modulation standards or for specific customerrequirements. Denote which VCXO frequency is on the board so that the CDCM7005 part can be set upproperly. The following conventions are typically used:

• WCDMA: Derivatives of 61.44 MHz (i.e., 122.88 MHz, 245.76 MHz, 491.52 MHz)• GSM: Derivatives of 52 MHz (i.e., 104 MHz, 208 MHz)• CDMA2K: Derivativies of 78.6432 (i.e., 157.2864 MHz, 314.5728 MHz)

The VCO outputs the RF signal used for the LO drive on the analog quadrature modulator. The RF outputfrequency is contingent on the LO frequency value.

The RF frequency band of the VCO must be noted in order to know how to program the TRF3750 andwhere to measure the output RF signal from the modulator. The typical bands of operation are shown inTable 1.

Table 1. Frequency Bands

UMTS PCS GSM900 DCS1800

FREQUENCY 2110-2170 MHz 1930-1990 MHz 935-960 MHz 1805-1880 MHz

SLWU013B–March 2004–Revised November 2005 TSW3000 Demo Kit 7

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Demo Kit Configuration Options

TSW3000 Demo Kit8 SLWU013B–March 2004–Revised November 2005

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2 Block Diagrams

2.1 System Block Diagram

DAC

I/QModulator90°

0°

LPA TX

Diplexer

ANT

RX

LNA

A/DI/Q

Demod

2.2 Demo Kit Block Diagram

16

DAC5687

16

CLK1

I

Q

TRF370x

I/QModulator

RF

LO

VCO

TRF3750

VCXO

PLL

Ref Osc

CDCM7005

CLK2

Block Diagrams

The basic radio system block diagram in Figure 1 demonstrates where the TSW3000 Demo Kit fits in theoverall transceiver. The dash-line box illustrates the components found on the TSW3000 Demo Kit board.

Figure 1. System Block Diagram

The basic Demo Kit block diagram is shown in Figure 2. The shaded boxes illustrate the key TexasInstruments components found on the TSW3000 Demo Kit board.

Figure 2. Demo Kit Block Diagram


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3 Key Texas Instruments Components

3.1 CDCM7005

3.2 DAC5687

3.3 TRF370x

3.4 TRF3750

4 Software Installation

5 Software Operation

Key Texas Instruments Components

The CDCM7005 clock distribution chip is used to generate and synchronize the clock outputs to thesystem. The device has five outputs which can be either LVPECL or LVCMOS and can be divided downby 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a 90 degreephase shift.

The DAC5687 is a 16-bit interpolating dual digital-to-analog converter (DAC). The device incorporates adigital modulator, independent differential offset control, and I/Q amplitude control. The device is typicallyused in baseband mode or in low IF mode in conjunction with an analog quadrature modulator.

The TRF370x is a direct upconvert I/Q modulator. The device accepts differential input voltage atbaseband or low IF frequencies and outputs an RF signal based on the LO drive frequency.

The TRF3750 is a PLL chip used in the synthesizer section to generate the LO frequency required for theI/Q modulator.

This section summarizes the installation procedures for the software required to operate the Demo Kit.Once all of the software is loaded, it is recommended to reboot the computer.

• Extract TSW3000-Installv2p0.zip• Execute setup.exe

The following describes the use of the software required to set the TSW3000 Demo Kit in the baselineconfiguration for the CDCM7005, TRF3750, and DAC5687. The software should be configured in theorder presented below. The first step requires starting the TSW3000 software. This opens a window asshown in Figure 3. The tabs on the left side of the window allow selection of different GUI controllers forthe DAC5687, TRF3750, and CDCM7005. The lower left portion of the screen contains links to this user'sguide as well as the data sheets for the DAC5687, TRF3750, and the CDCM7005.


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5.1 CDCM7005 Software

Software Operation

Figure 3. TSW3000 Startup Screen

By using the provided CDCM7005 serial peripheral interface (SPI) software, the user can load settings tothe CDCM7005 internal registers. This must be performed every time the TSW3000 Demo Kit is poweredup, since the CDCM7005 has default settings that are loaded at power up and the settings may be slightlydifferent than the ones required to operate the Demo Kit. Executing the program brings up the interfaceseen in Figure 4. The default settings are correct for a VCXO of 491.52 MHz and a 10 MHz reference ason the TSW3000. The CDCM7005 GUI allows register settings to be saved and can be loaded back inafterwards. This can be accomplished with the Save and Load Settings buttons near the right side of theGUI.

It is recommended that any unused output clocks be tri-stated. In this case the TSW3000 only usesOUT_MUX_1 to drive the DAC5687. OUT_MUX_0, OUT_MUX_2, OUT_MUX_3, OUT_MUX_4 should betri-stated unless there is a need to use the other output clocks.


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Software Operation

Figure 4. Default CDCM7005 SPI GUI

The divider parameters, M and N, are determined according to the following equation based on theinternal reference frequency and internal VCXO frequency.

FREF = (FVCXO× M)/(N × P)

The p parameter is the VCXO input divider and set through the FB_MUX value. The M and N countervalues need to be adjusted depending on the board configuration. The M and N counter registers aredetermined by the reference frequency and the VCXO frequency. The OUT_MUX sets the divide ratios forthe individual output clocks. The OUTSEL determines whether the output clocks will be used assingle-ended CMOS or differential LVPECL. With a 10-MHz reference oscillator the CDCM7005 settingsare shown in Table 2 for a variety of common VCXO frequencies. For other frequencies, see to theCDCM7005 data sheet for more details.

Table 2. CDCM7005 Register Values

VCXO Freq. (MHz) 491.52 245.76 122.88 61.44

Divider M 125 125 125 125

Divider N 768 768 768 768

FB_MUX 8 4 2 1

12 TSW3000 Demo Kit SLWU013B–March 2004–Revised November 2005

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5.2 TRF3750 Software

Software Operation

The TRF3750 software is used to program the PLL chip to lock the VCO oto a desired frequency output.The main menu of the program is shown in Figure 5.

Figure 5. TRF3750 GUI - Main Menu

The options in the front panel allow the user to program the desired frequency of the VCO, the desiredfrequency of the PFD, the reference frequency, and the prescaler selection. The software then displaysthe actual VCO frequency, PFD frequency and the R, N, A, and B counter values to be programmed intothe TRF3750. Hitting the Send button writes these values to the TRF3750. In default mode on a defaultboard, only the desired VCO frequency (2100 MHz to 2200 MHz) needs to be changed. For other VCOranges, other parameters may need to be changed.

The Advanced Operation button will bring up another user interface as shown in Figure 6.


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5.3 DAC5687 Software

Software Operation

Figure 6. TRF3750 GUI - Advanced Menu

This menu allows control of more register settings. For details on these settings, see the TRF3750 datasheet (SLWS146). The register of interest in this menu is the MUXOUT CONTROL which can be used todetermine the function of LED D4. This mode defaults to Digital PLL Lock Detect and causes the LED D4to light up when the PLL successfully locks. Normally, these menu settings do not need to be changed.

By using the provided software, the user can write and read control register information to the DAC5687.At first startup of this software, it is imperative to select the Pll Port Config button to bring up the parallelport configuration settings. From the menu, select the TSW3000 setting. This configures the port to becompatible with the TSW3000. Once the Demo Kit is powered on with the parallel port configured andconnected properly, then the GUI shown in Figure 7 is displayed with the default settings read from thedevice. If there is a problem with the communication, such as the Demo Kit is not powered on or theparallel port cable is not connected, an error message will be displayed instructing the user to correct theproblem. Once corrected, hit the Read All button to read the default settings of the device.


http://www-s.ti.com/sc/techlit/SLWS146

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5.4 DAC5687 GUI Register Descriptions

Software Operation

Figure 7. DAC5687 GUI

For normal operation, the user needs only to select values and switches as desired. The values areautomatically sent to the device and read back to verify their configuration.

5.4.1 Register Controls• Load Regs– Loads register values from a saved file to the DAC5687 and updates the GUI.• Save Regs– Saves current GUI registers settings to a text file for future use.• Read All– Reads the current registers of the DAC5687. This is used to verify settings on the front

panel.• Send All– Sends the current front panel registers to the device. This is generally only used when the

Demo Kit power has recycled or the device has been reset and the user wants to load the displayedsettings to the device.

5.4.2 Configuration Controls• Full Bypass– When set, all filtering, QMC, and NCO functions are bypassed.• FIR Bypass– Bypass all interpolation filters. QMC INCO functional. Limited to FDAC = 250 MHz• FIFO Bypass– When set to bypass, the internal four sample FIFO is disabled. When cleared, the FIFO

is enabled.• FIR A– A side first FIR filter in high-pass mode when set, low-pass mode when cleared.


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Software Operation

• FIR B– B side first FIR filter in high-pass mode when set, low-pass mode when cleared.• Dual Clk– Only used when the PLL is disabled. When set, two differential clocks are used to input the

data to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is usedas the DAC sample clock.

• Interleave– When set, interleaved input data mode is enabled; both A and B data streams are input atthe DA(15:0) input pins.

• Inverse Sinc– Enables inverse sinc filter.• Half Rate Input– Enables half rate input mode. Input data for the DAC A data path is input to the chip

at half speed using both the DA(15:0) and DB(15:0) input pins.• Sif– Sets sif_4-pin bit. A 4-pin serial interface mode is enabled when on, 3-pin mode when off. The

DAC5687 Demo Kit is configured for a 3-pin serial interface, so setting to a 4-bit serial interface makesreading registers impossible with the GUI.

• Inv. PLL Lock– Only used when PLL is disabled and dual clock mode is disabled. When cleared, inputdata is latched into the chip on rising edges of the PLLLOCK output pin. When set, input data islatched into the chip on falling edges of the PLLLOCK output pin.

• PLL Freq– Sets PLL VCO center frequency to low or high center frequency.• PLL Kv– Sets PLL VCO gain to either high or low gain.• Qflag– Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator when

interleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timingrelationship.

• 2's Comp– When set, input data is interpreted as 2's complement. When cleared, input data isinterpreted as offset binary.

• Rev A Bus– When cleared, DA input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB.When set, DA input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.

• Rev B Bus– When cleared, DB input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB.When set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.

• USB– When set, the data to DACB is inverted to generate upper side band output.• Inv. Clk I(Q)– Inverts the DAC core sample clock when set, normal when cleared.• Sync_Phstr– When set, the internal clock divider logic is initialized with a PHSTR pin low to high

transition.• Sync_cm– When set, the coarse mixer is synchronized with a PHSTR low-to-high transition.• Sync_NCO– When set, the NCO phase accumulator is cleared with a phstr low-to-high transition.• Phstr Clk Div Select– Selects the clock used to latch the PHSTR input when restarting the internal

clock dividers. When set, the full rate CLK2 signal latches PHSTR and when cleared, the divided downinput clock signal latches PHSTR.

• DAC Serial Data– When set, both DAC A and DAC B input data is replaced with fixed data loaded intothe 16-bit serial interface DAC Static Data.

– Counter Mode– Controls the internal counter that can be used as the DAC data source: off; all16b; 7b LSBs; 5b MIDs; 5b MSBs.

– DAC Static Data– When DAC Serial Data is set, both DAC A and DAC B input data is replacedwith fixed data loaded with this value. Range = 0 - 65535.

• Alt. PLLLOCK Output– Can be used to determine alternate outputs on the PLLLOCK pin when usingthe internal PLL mode. The EXTLO pin must be open when using this mode.

• NCO– When set, enables NCO.

– NCO Gain– Sets NCO gain resulting in a 2x increase in NCO output amplitude. Except for Fs/2 andFs/4 mixing NCO frequencies, this selection can result in saturation for full-scale inputs. Considerusing QMC gain for lower gains.

• QMC– When set, enables the QMC.

– QMCA Gain– Sets QMC gain A to a range = 0 to 2047. See the data sheet for more information.– QMC B Gain– Sets QMC gain B to a range = 0 to 2047. See the data sheet for more information.– QMC Phase– Sets QMC phase to a range = -512 to 511. See the data sheet for more information.

Used to adjust for I/Q phase imbalance.• Mode– Used to select the coarse mixer mode. See the DAC5687 data sheet for more information.


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6 Board Setup

6.1 Jumper Settings

Board Setup

• PLL Divider– Sets VCO divider to div by 1, 2, 4, or 8.• Interpolation – Sets FIR Interpolation factor: X2, X4, X4L, X8. X4 uses lower power than 4xL, but

Fdac = 320 MHz max when NCO or QMC are used.• Phstr Init. Phase – Adjusts the initial phase of the fs/2 and fs/4 cmix block at PHSTR.• Sync FIFO– Sync source selection mode for the FIFO. When a low to high transition is detected on

the selected sync source, the FIFO input and output pointers are initialized. See the DAC5687 datasheet for source description.

5.4.3 DAC A(B) Gain• DAC Coarse Gain– Sets coarse gain of DAC A(B) full-scale current. Range is 0 to 15. See the

DAC5687 data sheet for full-scale gain equation.• DAC Fine Gain– Sets fine gain of DAC A(B) full scale current. Range is -128 to127. See the DAC5687

data sheet for full-scale gain equation. Used to adjust for I/Q amplitude imbalance.• DAC DCOffset– Sets DAC A(B) dc-offset register. Range is -4096 to 4095. Used to adjust for carrier

suppression.• Sleep– DAC A(B) sleeps when set, operational when cleared.

5.4.4 NCO• NCO DDS– Sets NCO DDS registers. See the DAC5687 data sheet for formula.• NCO Phase– Sets initial NCO phase registers. See the DAC5687 data sheet for more information.• FDAC (MHz), NCO IF (MHz)– Used to calculate the required NCO DDS value.

5.4.5 Additional Control/Monitor Registers• Version– Displays the version of the silicon. If a version of 0 is read then the communication is not

functioning and an error message will be displayed.

The TSW3000 Demo Kit has on-board jumpers that allow the user to selectively disengage devices asdesired. The unit is shipped with jumpers in place that activate all of the devices on board. Table 3explains the functionality of the jumpers on the board.

Table 3. Jumper List

JUMPER LABEL FUNCTION CONDITION DEFAULT

W1 PLL Lock 2-pin access port for monitoring PLL lock of the Open InstalledDAC5687

W2 PWD Power down for the TRF370x Powered Pin 1, 2

W6 LO Buffer Disengages power to LO buffer amp Powered Installed

W5 IOVDD Toggles 3.3 V or 1.8 V to IOVDD on the DAC5687 3.3 V Engaged Pin 1, 2

J15 pin 2 PLLVDD Toggles power to the DAC PLL Not Powered Pin 1, 2

J15 pin 5 SLEEP Power down for the DAC5687 Open Removed

J15 pin 8 EXTLO Toggles internal reference ground Grounded Pin 7, 8

J15 pin 11 TXENABLE Selects interleaved data Powered Pin 11, 12

J15 pin 14 TESTMODE DO NOT POPULATE! Open Removed

J15 pin 17 QFLAG Used to flag the DAC5687 channel B data in Open Removedinterleave mode

J15 pin 20 CDC_PD Power down of the CDCM7005 Open Removed

J15 pin 23 REF_SEL Selecets reference for CDCM7005 Open Removed

J15 pin 27 PLL_PWD Power down the TRF3750 Powered Pin 26, 27


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6.2 Input/Output Connectors

6.3 Parallel Port

6.4 DC Power Requirements

7 Demo Kit Test Configuration

Demo Kit Test Configuration

Table 3. Jumper List (continued)

JUMPER LABEL FUNCTION CONDITION DEFAULT

J15 pin 29 RESET Resets the DAC5687 when low Open Removed

The input and output connections are shown in Table 4.

Table 4. Input/Output Connections

REFERENCE DESIGNATOR CONNECTOR TYPE DESCRIPTION

J13 34-pin header I channel data input

J14 34-pin header Q channel data input

J9 SMA RF output

J10 SMA Optional LO input

J8 SMA Optional external reference

J2 SMA Output clock 1 from CDCM7005

J3 SMA Output clock 2 from CDCM7005

J5 SMA Optional I out A from DAC5687

J19 SMA Optional Q out B from DAC5687

J6 SMA Input for external VCXO for CDCM7005

J7 SMA PLL lock status on DAC5687

J4 SMA Phase synchronization on DAC5687

RF shield covers should be in place over the synthesizer section and the RF modulator section. Theseshields provide isolation of the RF sections on the board.

The TSW3000 Demo Kit contains a 25-pin parallel port connector (J1) to interface to a standard computerparallel port. Programming of the CDCM7005, DAC5687, and TRF3750 are accomplished through thisport.

The Demo Kit requires a single dc-voltage supply that is nominally 6 V. From that supply, the 5 V, 3.3 V,and 1.8 V required for the devices on the board are generated internally through linear voltage regulators.It is possible to use a higher input voltage; however, care should be taken not to over dissipate theon-board voltage regulators.


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7.1 Test Setup Block Diagram

TSW3000EVM DUT

J7Clock

PowerSupply GND

+6 V

16

25

J9PatternGenerator

16

J17 J11

PC Controller

J14

J13

J1

SpectrumAnalyzer

7.2 Test Equipment

7.3 Calibration

7.4 Test Specifications

Demo Kit Test Configuration

The test set up for general testing of the TSW3000 Demo Kit is shown in Figure 8.

Figure 8. Test System Block Diagram

The following is a list of the test equipment required for testing the TSW3000 Demo Kit. Equivalent modelsmay be used for certain applications, but may produce different results due to limitations within theinstrument.

• Dual Power Supply: Any with current readout capability• Spectrum Analyzer: Rhode & Schwartz FSU, Agilent PSA, or equivalent

This particular piece can measure >70-dBc ACPR with the noise cancellation option active. Thisamount of dynamic range is required to accurately measure the ACPR of the Demo Kit. Anotherspectrum analyzer can be substituted if it achieves as good or better dynamic range.

• Pattern Generator: Agilent 16702B• Oscilloscope: Tektronix 650 or equivalent

Used to probe clock output signals and for debugging.• Digital Voltmeter: Agilent 34401A or equivalent

In order to record proper output power the insertion loss of the output cable must calibrated. Measure theinsertion loss of the cable from J9 to the spectrum analyzer; set the analyzer's reference level offset tothat value.

The test specifications are outlined in Table 5.

Table 5. Demo Kit Specifications

MIN MAX UNITS

CURRENT

+6 V 1.5 A

CW TESTS


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8 Basic Test Procedure

8.1 Initial Inspection

8.2 Engage Power Supplies

8.3 Program the CDCM7005

8.4 Program the TRF3750

Basic Test Procedure

Table 5. Demo Kit Specifications (continued)

MIN MAX UNITS

Carrier suppression 30 dBc

Sideband rejection 25 dBc

Spurious Output

2nd harmonic 45 dBc

Aliased LSB (pos) 40 dBc

Output clock 40 dBc

Aliased USB 15 dBc

Aliased USB (neg) 8 dBc

WCDMA ACPR

Channel power -14 dBm

ACPR -Low 70 dBc

ACPR -High 70 dBc

This section outlines the basic test procedure to get the Demo Kit operational. Disconnect the cables atJ13 and J14 that connect to the pattern generator. Connect the power supply cable and the RF output tothe spectrum analyzer.

Inspect the board to determine which devices were used.

• Note the VCXO frequency (U10) that is on the board• Note the VCO frequency band (Y3) that is on the board

Engage 6-V power supply

• Verify the current reading is between 0.8 A to 1.3 A when configured with the DAC5687

Use the Default Settings on the CDCM7005 GUI (See Section 5.1). This generates a 491.52-MHz clock.

• Set the OUT_MUX_0, 2, 3, 4 to tristate. Only OUT_MUX_1 is used for clocking the DAC5687• Hit the GUI Send button• Verify that LEDs D1, D2, and D3 are illuminated

Use the Default Settings in the TRF3750 GUI (See Section 5.2). This places a carrier at 2.14 GHz

• Hit the GUI send button.• Verify the LED D4 is illuminated. This indicates lock of the VCXO and TCXO reference.• Monitor RF output from the spectrum analyzer• Verify a single frequency tone at the default 2.14 GHz.


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8.5 DAC5687 Program

8.6 Carrier Suppression


Table 6. Frequency Designations

VCO BAND UMTS GSM900 PCS DCS1800

Midband (MHz) 2140 950 1960 1850

Low (MHz) 2110 935 1930 1805

High (MHz) 2170 960 1990 1880

• Disable the PLL by removing the jumper at J15, pins 2 and 3, if not already removed.• Verify DACA and DACB Coarse Gain is set to 15• Set Mode to 0000 (No Coarse Mixing)• Ensure DAC Offsets and DAC fine gain for both A and B are set to 0• Set the spectrum analyzer as follows:

– Center Freq: 2.14 GHz– RBW: 30 kHz, VBW: 300 kHz– Span: 491.52 MHz– Attn: 5 dB– Ref Level: 10 dBm

The carrier suppression can be tuned for better performance by adjusting the dc-offset controls on theDAC5687. The default DAC GUI is shown below with the NCO mixer turned on to output a 61.44-MHztone. The output spectrum is illustrated in Figure 10.


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Figure 9. Default DAC GUI With fDAC/8 Tone From NCO


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8.7 Sideband Rejection


Figure 10. Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments

An iterative process is used to achieve the best performance.

• Place a normal marker at the peak upper sideband, place a delta marker at the carrier signal, and notethe initial delta value.

• Set initial DACA offset to 1000 and DACB offset to -1000• Change DACA offset by 1000 steps and monitor the output performance change.• If performance gets better, then repeat the process with an additional 1000 steps. If the performance

gets worse or doesn't change, then change the offset in the other direction by 1000 steps.• Once the performance remains basically unchanged, repeat the process on DACB offset with 1000

step changes.• Once optimized, go back to the A side and repeat the tuning process with a step size of 100.• Continue tuning. After each complete cycle, reduce the step size down (i.e., to 10, then to 1 if desired).• A performance greater that 65 dBc should be achievable.

Sideband rejection is determined by the two quadrature signals to the modulator being exactly 180degrees out of phase and exactly the same amplitude. Amplitude and phase imbalance between the twopaths yield an unwanted lower sideband. The amplitude variation between the two paths can becompensated for by adjusting the DAC fine gain controls or by adjusting the QMC gain controls if thedevice is operating with the QMC on. The phase can be compensated by using the QMC phaseadjustment. Note this is only possible when the coarse mixer is not used in the fDAC/4 mode. Coarsemixing in the fDAC/4 mode causes the relative phase information between I and Q paths to be mixed. In thefDAC/2 mode there are no cross terms (terms are 0) and the relative phase information is maintainedbetween I and Q paths.


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• Place marker delta on the lower sideband• Turn on the QMC. Set the Gain of the QMC to 1024 for gain of 0 dB for I and Q paths. Other initial

settings may be needed depending on the state of the NCO gain and signal amplitude.• Change the phase of the QMC by small increments until the sideband is minimized.• Change the QMC A or B gains in increments of 1 until the sideband is minimized.• The overall performance should be greater than 60 dBc from the other sideband with amplitude and

phase corrections.• Re-optimized the dc-offset values as required to maintain carrier suppression performance as

specified.

Figure 11. DAC GUI With Typical Settings To Minimize LO and Sideband

Sideband and LO are reduced into the noise floor. Clock related spurs can be filtered out using an RFfilter.


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9 Optional Configurations

9.1 External LO

9.2 External Reference

9.3 Monitor DAC Output

Optional Configurations

Figure 12. Sideband and LO

To configure the board for external LO implement the following modifications

• Remove R225• Place R2: 0-Ω resistor, this connects the external LO on J10 to the TRF3702 modulator• Remove W6 (disengages power to RF amplifier)• Disable the TRF3750 PLL CE by setting J15-25, 26. This puts GND on CE of the TRF3750 and

disables the PLL.

To configure the board for an external reference implement the following modifications.

• Remove R144, this disconnects the on board 10-MHz reference• Place R201: 0-Ω resistor, external reference can be hooked up to J8


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10 Filter Specifications

10.1 Baseband Filter

11 Layers and Schematics

11.1 Bill of Materials

Filter Specifications

9.3.1 Single Ended

To configure the board to monitor the DAC output by utilizing the transformers on board to achieve asingle-ended output, implement the following modifications.

• Remove R187, R188, R191, R190, R208, R209, R210, R211• Place R200, R224, R222, R223: 0-Ω resistors• Place R179, R183, R212, R213: 100-Ω resistor. This configures the DAC output as in the DAC5687

data sheet for 4:1 impedance transformer.

Monitor outputs at J5 and J19.

The TSW3000 Demo Kit layout provides the opportunity to place components to realize up to a 7th orderLC filter. The Demo Kit is by default populated with a 500-MHz LC low-pass filter to help eliminate DACimages and also out of band clock spurs which may mix into RF frequencies.

10.1.1 RF Filter/Output Match

The TSW3000 Demo Kit layout also provides the opportunity to place a small 3rd order LC filter on theoutput of the modulator for either filtering or impedance matching purposes. This filter has been disabledby removing the shunt capacitive elements and replacing the series inductor element with a 0-Ω resistor.

This chapter contains the layers and schematics for the TSW3000 Demo Kit.

Table 7 lists the parts used in constructing the TSW3000 Demo Kit.

Table 7. Bill of MaterialsValue QTY Part Number Vendor Ref Des Not Installed

CAPACITORS

TANT 47 µF, 10%, 10 V 7 ECS-T1AD476R Panasonic C25, C67, C70, C74, C105,capacitor C124, C160

TANT 10 µF, 10%, 10 V 18 ECS-T1AX106R Panasonic C24, C35, C37-C41, C51,capacitor C83, C99, C116, C117,

C121, C123, C129, C153,C156, C161

TANT 10 µF, 10 V, 10% 2 T491C106K010AS Kemet C22, C101capacitor

TANT 22 µF, 10 V, 10% 1 T491C226K010AS Kemet C96capacitor

1 µF, 25 V, 10% capacitor 6 ECJ-3YB1E105K Panasonic C47, C50, C53, C54, C144,C159

0.01 µF, 50 V, 10% capacitor 5 ECJ-2VB1H103K Panasonic C57, C60, C64, C102, C109

0.1 F, 16 V, 10% capacitor 8 ECJ-2VB1C104K Panasonic C20, C21, C23, C26, C27,C75, C81, C106

1 pF, 50 V, ±0.25 pF capacitor 4 ECJ-2VC1H010C Panasonic C30, C32, C125, C126

2.2 pF, 50 V, ±0.25% capacitor 3 08055A2R2CAT2A AVX C19, C31, C68

0.0018 µF, 50 V 5% capacitor 0 ECJ-2VC1H182J Panasonic C66, C72

6.8 pF, 50 V, ±0.25% capacitor 2 08055A6R8CAT2A AVX C63, C65

47 pF, 50 V, 5% capacitor 0 ECJ-2VC1H470J Panasonic C93, C95

1 µF, 16 V, 10% capacitor 1 ECJ-1VB1C105K Panasonic C91


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Layers and Schematics

Table 7. Bill of Materials (continued)Value QTY Part Number Vendor Ref Des Not Installed

0.1 µF, 16 V, 10% capacitor 16 ECJ-1VB1C104K Panasonic C28, C43-C45, C48, C76,C78-C80, C82, C87, C89,C90, C134, C151, C152

0.01 µF, 16 V, 10% capacitor 5 ECJ-1VB1C103K Panasonic C46, C52, C56, C62, C130

10 pF, 50 V, ±0.5 pF, capacitor 8 ECJ-1VC1H100D Panasonic C61, C97, C107, C108,C111, C127, C128, C158

22 pF, 50 V, 5%, capacitor 3 ECJ-1VC1H220J Panasonic C146, C148, C149

33 pF, 50 V, 5%, capacitor 0 ECJ-1VC1H330J Panasonic C142

0.47 µF, 6.3 V, 10%, capacitor 1 ECJ-1VB0J474K Panasonic C92

1 pF, 50 V, 5%, capacitor 0 ECJ-1VC1H010C Panasonic C98


100 pF, 50 V, 5%, capacitor 5 ECJ-1VC1H101J Panasonic C132, C133, C135-C137



1000 pF, 50 V, 5%, capacitor 4 ECJ-1VC1H102J Panasonic C88, C139, C140, C147

0.1 µF, 10 V, 10% capacitor 34 ECJ-0EB1A104K Panasonic C1-C18, C29, C36, C49,C58, C69, C73, C84, C85,

C86, C100, C104,C112-C115, C120

0.01 µF, 16 V, 10% capacitor 2 ECJ-0EB1C103K Panasonic C71, C122

0.001 µF, 25 V, 10% capacitor 2 ECJ-0EB1E102K Panasonic C119, C131

0.033 µF, 10 V, 10% capacitor 1 ECJ-0EB1A333K Panasonic C34

RESISTORS

2 kΩ resistor, 1/10 W, 1% 2 ECJ-0EB1C103K Panasonic R8, R11

10 kΩ resistor, 1/10 W, 1% 6 ERJ-6ENF1002V Panasonic R17, R34-37, R155

47.5 Ω resistor, 1/10 W, 1% 2 ERJ-6ENF47R5V Panasonic R146, R147

10 Ω resistor, 1/10 W, 1% 1 ERJ-6ENF10R0V Panasonic R3

0 Ω resistor, 1/10 W, 5% 16 9C06031A0R00JLHF Yageo R6, R9, R47, R110, R114, R10, R14, R48, R109, R124,T R133, R144, R171, R172, R145, R181, R182,

R178, R189, R193, R225, R200-R202, R222-R224,R232, R247, R249 R228, R229, R245, R250

1 kΩ resistor, 1/16 W, 1% 3 ERJ-3EKF1001V Panasonic R1, R4, R226 R7, R44

2 kΩ resistor, 1/16 W, 1% 1 ERJ-3EKF2001V Panasonic R227

3.92 kΩ resistor, 1/16 W, 1% 1 ERJ-3EKF3R92V Panasonic R135

4.75 kΩ resistor, 1/16 W, 1% 2 ERJ-3EKF4751V Panasonic R125, R141

10 kΩ resistor, 1/16 W, 1% 9 ERJ-3EKF1002V Panasonic R115, R116, R149, R151,R195, R196, R199, R218,

R248

20 kΩ resistor, 1/16 W, 1% 1 ERJ-3EKF2002V Panasonic R136

100 kΩ resistor, 1/16 W, 1% 6 ERJ-3EKF1003V Panasonic R30, R31, R32, R113, R130,R131

15 Ω resistor, 1/16 W, 1% 4 ERJ-3EKF15R0V Panasonic R187, R188, R190, R191

18.2 Ω resistor, 1/16 W, 1% 1 ERJ-3EKF18R2V Panasonic R122

22.1 Ω resistor, 1/16 W, 1% 4 ERJ-3EKF22R1V Panasonic R16, R18, R197, R237

5.62 Ω resistor, 1/10 W, 1% 3 RC0603FR-075R62L Yageo R137, R138, R148

49.9 Ω resistor, 1/16 W, 1% 9 ERJ-3EKF49R9V Panasonic R13, R39, R40, R43, R46, R12R238, R239, R243, R244

82.5 Ω resistor, 1/16 W, 1% 6 ERJ-3EKF82R5V Panasonic R126, R127, R161, R162,R163, R164

100 Ω resistor, 1/16 W, 1% 10 ERJ-3EKF1000V Panasonic R19, R20, R21, R22, R27, R2, R5, R179, R183, R212,R28, R29, R45, R140, R150 R213

110 Ω resistor, 1/16 W, 1% 0 ERJ-3EKF1100V Panasonic R235

130 Ω resistor, 1/16 W, 1% 6 ERJ-3EKF1300V Panasonic R19, R20, R21, R22, R27,R28, R29, R45, R140, R150

150 Ω resistor, 1/16 W, 1% 2 ERJ-3EKF1500V Panasonic R15, R221 R33, R38


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162 Ω resistor, 1/16 W, 1% 1 ERJ-3EKF1620V Panasonic R142

200 Ω resistor, 1/16 W, 1% 2 ERJ-3EKF2000V Panasonic R132, R134

221 Ω resistor, 1/16 W, 1% 4 ERJ-3EKF2210V Panasonic R208-R211 R236



475 Ω resistor, 1/16 W, 1% 1 ERJ-3EKF4750V Panasonic R117 R118, R123

750 Ω resistor, 1/16 W, 1% 3 ERJ-3EKF7500V Panasonic R23, R24, R26



15.8 Ω resistor, 1/16 W, 1% 1 ERJ-3EKF1582V Panasonic R41

30.1 Ω resistor, 1/16 W, 1% 1 ERJ-3EKF3012 Panasonic R42

10 Ω resistor, 1/16 W, 1% 1 ERJ-2RKF10R0X Panasonic R255

Surface Mount Socket strips 4 310-93-164-41- Mill-Max RP5- RP8105000

51 Ω resistor pack 0 CTS RP5-RP8

22 Ω resistor pack 4 4816P-001-220 Bourns RP1, RP2, RP3, RP4

INDUCTORS

11 EXC-ML32A680U Panasonic FB1, FB3, FB6, FB,7 FB10,FB11, FB14-FB18

Ferrite Bead 5 EXC-ML20A390U Panasonic FB2, FB4, FB8, FB9, FB12

1 623-2773021447 Mouser FB13

Inductor, 18 nH 4 LLQ2012-F18NG Toko L9, L11, L13, L14

Inductor, 2.7 nH 4 LLQ2012-F2N7J Toko L10, L12, L15, L16

0 Ω resistor, 1/8 W, 5% 5 9C08052A0R00JLHF Yageo L2, L4, L7, L8, L17T

2.2 nH Inductor 0 LL2012-FH2N2S Toko L19

22 nH Inductor 1 0805CS-220X_B_ Coilcraft L18

IC'S ETC.

DAC5687IPZP 1 DAC5687IPZP Texas Instruments U1

CDCM7005RGZ 1 CDCM7005RGZ Texas Instruments U12

CDCV304PW 1 CDCV304PW Texas Instruments U17

TRF3702IRHC 1 TRF3702IRHC Texas Instruments U11

TRF3750IPW 1 TRF3750IPW Texas Instruments U14

THS4221DBVR 1 THS4221DBVR Texas Instruments U18

TPS76750QPWP 1 TPS76750QPWP Texas Instruments U6



SN74HC241DW 1 SN74HC241DW Texas Instruments U4

SN74LV125AD 1 SN74LV125AD Texas Instruments U13

Amplifier DC-5000 MHz 1 SGA-5386 Sirenza U15

VCO 1 ROS-2170-7 Mini-Circuits Y3

VCXO 1 TC0-2111-491.52 Toyocom U10

Crystal Oscillator 1 OSC3B0 at 10 MHz Vectron Y2

4:1 Transformer 2 T4-1-KK81 Mini-Circuits T1, T2

Black Test Point 1 5011K Keystone TP12

Red Test Point 4 5000K Keystone E1, TP1, TP18, TP19

CONNECTORS, JUMPERS, ETC.

SMA Plug W/Stand Off 3 901-144-8RFX AMP J4, J5, J19

SMA connectors 7 16F3627 Newark J2, J3, J6-J10

Switch 1 EVQ-PJX04M Panasonic S1

Red Banana Jack 1 ST-351A Allied J11


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Black Banana Jack 1 ST-351B Allied J17

Green SM_LED_1206 4 CMD15-21VGC/TR8 Panasonic D1, D2, D3, D4

30 Pin Header 1 HTSW-120-07-L-T Samtec J15

34 Pin Header 2 TSM-117-01-S-DV-LC Samtec J13, J14

Connectors 1 745536-2 AMP J1

Nuts 2 J1

Mounting screws 2 J1

Unformed Fence 0.13 in with 2 14R-CBSU-24 Leader-Tech N/Q0.5 in spacing no standoff

3POS power jack 1 RAPC722 Switchcraft J12

3POS_header 2 HTSW-150-07-L-S Samtec W2, W5

2POS_header 2 HTSW-150-07-L-S Samtec W1, W6

MECHANICAL ASSEMBLY AND REWORKS

1 Leader-TechFence cover

1

Screws 6

Stand Off Hex (1/4 x 0.5") 6 1902CK-ND Allied

1 W1

1 W2 - Connect pins 1 and 2

1 W5 - Connect pins 1 and 2

1 W6 - Placed

1 J15 - Conn. pin 7 and 8(ExtLO)

Jumper 1 J15 - Conn. pin 1 and 2(PLL_VDD)

1 J15 - Conn. pin 11 and 12(TXEnable)

1 J15 - Conn. pin 23 and 24(REF_SEL)

1 J15 - Conn. pin 26 and 27(PLL_PWD)


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11.2 Layers


The Demo Kit is constructed on a 6-layer, 6.2 inch x 8 inch, 0.062-inch thick PCB using FR-4 material.See Figure 13 through Figure 22 show the PCB layout for the Demo Kit.

Figure 13. Top Layer


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Figure 14. Top Layer (NH)


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Figure 15. Layer 2


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Figure 16. Layer 3


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Figure 17. Layer 4


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Figure 18. Layer 4 (NH)


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Figure 19. Layer 5


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Figure 20. Bottom Layer


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Figure 21. Bottom Silkscreen


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Figure 22. Drill Drawing


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11.3 Schematics

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SH

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T:O

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TS

W30

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A 17

R. H

OPP

EN

STE

INY

. DE

WO

NC

K

C6

.1u

F

DV

DD

26

DG

ND

27

SD

EN

B2

8S

CL

K2

9S

DIO

30

SD

O3

1D

VD

D3

2T

XE

NA

BLE

33

DA

153

4D

A14

35

DA

133

6D

VD

D3

7D

GN

D3

8D

A12

39

DA

114

0D

A10

41

DA

94

2D

A8

43

DV

DD

44

DG

ND

45

IOV

DD

46

IOG

ND

47

DA

74

8D

A6

49

DA

55

0

DA4 51DA3 52DA2 53DA1 54DA0 55DVDD 56DGND 57CLKGND 58CLK1 59CLK1C 60CLKVDD 61CLK2 62CLK2C 63CLKGND 64PLLGND 65LPF 66PLLVDD 67DVDD 68DGND 69PLLLOCK 70DB0 71DB1 72DB2 73DB3 74DB4 75

DB

57

6D

B6

77

DB

77

8IO

GN

D7

9IO

VD

D8

0D

GN

D8

1D

VD

D8

2D

B8

83

DB

98

4D

B10

85

DB

118

6D

B12

87

DG

ND

88

DV

DD

89

DB

139

0D

B14

91

DB

159

2D

GN

D9

3P

HS

TR

94

/RE

SE

TB

95

SLE

EP

96

TE

ST

MO

DE

97

QF

LAG

98

DG

ND

99

DV

DD

10

0

AGND1 AVDD2 AVDD3 AGND4 IOUTB25 IOUTB16 AGND7 AVDD8 AGND9 AVDD10 EXTIO11 AGND12 BIASJ13 AVDD14 EXTLO15 AVDD16 AGND17 AVDD18 AGND19 IOUTA120 IOUTA221 AGND22 AVDD23 AVDD24 AGND25

U1

DA

C56

87

DA

0D

A1

DA

2D

A3

DA

4

DA

5D

A6

DA

7

DA

8D

A9

DA

10

DA

11D

A1

2

DA

13

DA

14

DA

15

DB

0D

B1

DB

2D

B3

DB

4DB

5D

B6

DB

7

DB

8D

B9

DB

10

DB

11D

B1

2

DB

13

DB

14

DB

15

CL

K2C

CL

K2

CL

K1C

CL

K1

+1.

8VD

DA

(0..1

5)

C5

.1u

F

C4

.1u

F

C2

.1u

F

C1

.1u

F

C8

.1u

F

SCL

KS

DIO

SC

LK

SD

IO

C9

.1u

FC

10

.1u

FC

11.1

uF

C1

4

.1u

F

C1

2.1

uF

C1

3

.1u

F

TX

EN

AB

LET

XE

NA

BL

E

SD

EN

1S

DE

N1

IOV

DD

R2

5

93.1

C3

4 .03

3u

F

C3

3 33

0p

F

R1

3

49.9

R4

1K

+3.

3VA

S1

SW

−P

BC

16

.1u

F

R1

1K

IOV

DD

E1

TP

1

C1

8

.1u

F

C1

7

.1u

F

+3.

3VA

+3.

3VA

+1.

8VD

+1.

8VD

+3.

3VC

LK

TE

STM

OD

ESL

EE

P

QF

LA

G

R3

9

49.9

R1

2

49.9

SLE

EP

TE

ST

MO

DE

QF

LAG

C8

6

.1u

F

C8

5

.1u

F

C8

4

.1u

F

C2

9

.1u

F

C1

5

.1u

F

+3.

3VA

R4

0

49.9

(SH

5)

(SH

5)

(SH

5)

(SH

2) (S

H 2

)

(SH

5)

(SH

5)

(SH

5)

(SH

5)

+C2

4

10

uF,

10

V

+C

38

10

uF,

10

V

+C3

7

10

uF,

10

V

+C3

9

10

uF,

10

V

+C4

0

10

uF,

10

V

+C

41

10

uF,

10

V

RE

SET

RE

SE

T(S

h 2

, 4

)

CL

K2C

B

CL

K2B

CL

K1C

B

CL

K1B

CL

K2

CB

CL

K2

B

CL

K1

CB

CL

K1

B

R4

51

00

R1

50

10

0C4

6 .01

uF

C5

6

.01

uF

C5

2 .01

uF

C6

2 .01

uF

(SH

2) (S

H 2

)(S

H 2

)

1

2345

J4 MC

X

1. D

O N

OT

INS

TALL

DB

(0..1

5)

IOU

TA1

IOU

TA2

IOU

TB

1IO

UT

B2

(SH

2)

IOU

TA1

(SH

3)

IOU

TA2

(SH

3)

IOU

TB

2(S

H 3

)IO

UT

B1

(SH

3)

DB

[0..

15

]

1

2345

J7 SMA

C1

34

.1u

F

+C

15

3

10

uF,

10

V

+3.

3VA

R2

36

22

1

R2

35

110

+3.

3VA

(No

te 1

)

(No

te 1

)

R2

37

22.1

CLK

IN1

OE

2

1Y0

3

GN

D4

1Y1

5V

DD

/3.3

V6

1Y2

7

1Y3

8

U1

7

CD

CV

304

R1

97

22.1

(No

te 2

)

2. C

HA

NG

E T

O 0

OH

M F

OR

50

OH

M L

OA

D

1 3

2W

5

+3.

3VA

+1.

8VD

(No

te 1

)

EX

T_L

OE

XT

_LO

(SH

2)

PLL

_VD

DP

LL

_V

DD

(SH

2)

W1

R2

50

0

R2

49

0 PHST

R(No

te 1

)

(SH

2)

PH

ST

R

C3 .1uF

R2

55

10

NO

TE

S:

(1−

2)

R4

649

.9

R4

349

.9

FB

15

FER

RIT

E


The following figures show the schematic for the TSW3000 Demo Kit.

Figure 23. Schematic - Page 1


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CO

NT

RO

L #

TS

W3

00

0

A

27

R. H

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EN

STE

IN

Y. D

EW

ON

CK

DAT

A P

OR

T 1

DAT

A P

OR

T 2

11

62

15

31

44

13

5

912

6 81

011

7

RP1 22

11

62

15

31

44

13

5

912

6 81

011

7

RP2

22

11

62

15

31

44

13

5

9

12

681

011

7

RP4 22

11

62

15

31

44

13

5

9

12

681

011

7

RP3

22

DB

(0..1

5)

DA

(0..1

5)

DA

0D

A1

DA

2D

A3

DA

4D

A5

DA

6D

A7

DA

8D

A9

DA

10

DA

11D

A1

2D

A1

3D

A1

4D

A1

5

DB

0D

B1

DB

2D

B3

DB

4D

B5

DB

6D

B7

DB

8D

B9

DB

10D

B11

DB

12D

B13

DB

14D

B15

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A1

0A

11A

12

A1

3A

14

A1

5

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

12

34

56

78

91

011

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

J13

34

PIN

_ID

C

12

34

56

78

91

011

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

J14

34

PIN

_ID

C

1

2

3

4

5

6

7

8

9

10 11

12

13 1

4

15

16 1

7

18

19 2

0

21

22 2

3

24

25 2

6

27

28 2

9

30

J15

+3.

3VA

SLE

EP

TX

EN

AB

LE

TEST

MO

DE

QFL

AG

SLE

EP

TX

EN

AB

LE

TE

ST

MO

DE

QF

LAG

3 R

OW

30

PIN

CO

NN

EC

TOR

(SH

1)

(SH

1)

(SH

1)

(SH

1)

(SH

1)

(SH

1)

RE

SE

TR

ESE

T(S

H 1

, 4

)

1. D

O N

OT

INS

TALL

PL

L_

VD

DP

LL_V

DD

(SH

1)

EX

T_L

OE

XT

_LO

(SH

1)

PHST

RP

HS

TR

(SH

1)

NO

TE

S:

12345678910

RP5

51

12345678910

RP6 51

(No

te 1

)

12345678910

RP7

51

12345678910

RP8 51

(No

te 1

)

(No

te 1

)

CD

C_P

DC

DC

_PD

(SH

4)

RE

F_SE

LR

EF

_SE

L(S

h 4

)PL

L_PW

DP

LL_P

WD

(Sh

7)

(No

te 1

)




www.ti.com

FIL

E:

Dra

wn

By:

Eng

inee

r:

ti12

500

TI B

oule

vard

. D

alla

s, T

exas

752

43Ti

tle:

SH

EE

T:O

F:

SIZ

E:

DAT

E:

RE

V:

24

−O

ct−

20

05

DO

CU

ME

NT

CO

NT

RO

L #

TS

W30

00A

37

R. H

OPP

EN

STE

INY

. DE

WO

NC

KN

OT

ES:

L9

18nH

C1

9

2.2

pF

C6

3

6.8

pF

C3

0

1p

F

L11

18 n

H

L1

2

2.7

nH

L1

0

2.7

nH

L2

0nH

L4

0nH

L1

3

18 n

H

C3

1

2.2

pF

C6

5

6.8

pF

C3

2

1p

F

L1

4

18 n

H

L1

6

2.7

nH

L1

5

2.7

nH

L7

0 nH L8

0 nH

R8

2K

R11 2K

IOU

TA1

IOU

TA2

(Sh

1)

(Sh

1)

QR

EF

QS

IG

ISIG

IRE

F

E3

E4

E5

E6

TP

12

IOU

TB

1

IOU

TB

2

(Sh

1)

(Sh

1)

1. D

O N

OT

INST

AL

L

IOU

TB

1

IOU

TB

2

IOU

TA1

IOU

TA2

R2

09

22

1

R2

08

22

1

R1

87

15

R1

88

15

R2

39

49.9

R2

38

49.9

VC

M

R1

79

10

0R

18

31

00

+3.

3VA

R2

10

22

1

R2

11

22

1

R1

90

15

R1

91

15

R2

44

49.9

R2

43

49.9

+3.

3VA

+5V

A

R2

12

10

0

R2

13

10

0

1

2345

J9 SMA

C2

6

.1u

F

C1

26

1p

F

C1

25

1p

F

C2

0

.1

uF

+5V

A

+5V

A

GND1

GND2

GND3

LO4

GND5

VC

C6

PW

D7

RF

OU

T8

GND 9

VCC 10

GND 11

GND 12

QVIN 13

IVIN

14

IRE

F1

5

QR

EF

16

U11

TR

F3

70

2

1 3

2W

2

+5V

A

L1

70

C7

2(N

ote

2)

C6

6

(No

te 2

)(N

ote

2)

C7

5

.1

uF

C8

1

.1

uF

R1

21

27

4

R1

22

18.2

R11

92

74

LO

CA

L_O

SCLO

CA

L_O

SC

(SH

7)

(No

te 1

)(N

ote

1)

(No

te 1

)(N

ote

1)

(No

te 1

)(N

ote

1)

RE

FOU

T

C9

3

47

pF

(No

te 1

)

C9

5

47

pF

(No

te 1

)

1

2345

J5 SMA

+3.

3VA

IOU

TA

R1

89

0

46

321T

1

T4

−1

T−

KK

81

R2

00

0 R2

24

0(No

te 1

)

(No

te 1

)

R2

10

0(N

ote

1)

1

2345J1

9SM

A

+3.

3VA

R1

93

0

4 6

3 2 1

T2

T4

−1

T−

KK

81

R2

23

0R2

22

0 (No

te 1

)

(No

te 1

)IO

UT

B

R5

10

0(N

ote

1)

(1−

2)

VC

M

C2

3

.1

uF

C6

8

2.2

pF

FB

16

FB

18

FB

17




www.ti.com

FIL

E:

Dra

wn

By:

Eng

inee

r:

ti12

500

TI B

oule

vard

. D

alla

s, T

exas

752

43Ti

tle:

SH

EE

T:O

F:

SIZ

E:

DAT

E:

RE

V:

24

−O

ct−

20

05

DO

CU

ME

NT

CO

NT

RO

L #

TS

W30

00A

47

R. H

OPP

EN

STE

INY

. DE

WO

NC

K

NO

TE

S:

PR

I_R

EF

36

VB

B4

0

RE

F_S

EL

35

CP

_OU

T3

1

CT

RL

_L

E2

9

CT

RL

_C

LK

28

CT

RL_

DAT

A2

6

PL

L_

LO

CK

25

SE

C_R

EF

37

STA

TU

S_R

EF2

3

/VC

XO

_IN

42

STA

TU

S_V

CX

O22

VC

XO

_IN

43

YO

A4

6

Y4B

17

YO

B4

7

Y4A

16

Y1A

3

Y1B

4

Y2A

7

Y2B

8

Y3A

11

Y3B

12

/PD

1

/RE

SE

T/H

OLD

14

VC

C_

CP

33

U1

2A

CD

CM

7005

RE

F_IN

CTR

L_LE

CTR

L_D

ATA

CT

RL

_CL

K

R2

37

50

R2

47

50

R2

67

50

D2

D3

D1

CP_

OU

T

CL

K1

B

CL

K1

CB

CL

K2

B

CL

K2

CB

CL

K1B

CL

K2B

CL

K2C

B

CL

K1C

B

VC

XO

_IN

VC

XO

_IN

B

CT

RL

_L

E

CT

RL_

DAT

A

CT

RL

_C

LK

(Sh

5)

(Sh

5)

(Sh

5)

(Sh

1)

(Sh

1)

(Sh

1)

(Sh

1)

GN

D2

4V

CC

2V

CC

5V

CC

6V

CC

9V

CC

10

VC

C1

3V

CC

15

VC

C1

8V

CC

19

VC

C2

0V

CC

21

VC

C4

1V

CC

44

VC

C4

5V

CC

48

AV

CC

27

AV

CC

30

AV

CC

32

AV

CC

38

AV

CC

39

U1

2B

CD

CM

7005

+C

10

1

10

uF

C1

04

.1u

F

C5

8

.1u

F

C11

3

.1u

F

+3.

3VC

LK

C7

1

.01

uF

C7

3

.1u

F

R1

51

10

K

R1

49

10

K

+3.

3VC

LK

+3.

3VC

LK

V_C

TR

L1

GN

D3

VC

C6

OU

T4

EN

2O

UT

_B

5

U1

0V

CX

O1

V_C

TR

L

R1

26

82.5

R1

27

82.5

R1

28

13

0

R1

29

13

0

R1

41

4.7

5K

R1

42

16

2

C9

1

1u

F

C9

2

.47

uF

C8

81

00

0p

F

R7

1K

RE

F_O

SC

RE

SET

RE

SE

T

R1

24

0

(No

te 1

)

CL

OC

K D

IST

RIB

UT

ION

R1

61

82.5

R1

62

82.5

R1

63

82.5

R1

64

82.5

R1

52

13

0

R1

53

13

0

R1

54

13

0

R1

56

13

0

+3.

3VC

LK

1

2345

J3SM

A E

ND

OU

T C

LK

2R

18

22.1

Y3

1

2345

J2SM

A E

ND

OU

T C

LK

1

R1

6

22.1

Y4

(Sh

1,

2)

RE

F_O

SC

(Sh

7)

+C

96

22

uF

1. D

O N

OT

INST

AL

LTOY

OC

OM

211

5−

49

1.5

2M

HZ

R1

09

0

CD

C_L

CK

(No

te 1

)

CD

C_

LC

K(S

h 5

)

R2

21

15

0

C11

4

.1u

F

CD

C_P

DC

DC

_PD

(Sh

2)

C3

6

.1u

F

+3.

3VC

LK

R1

91

00

R2

11

00

R2

01

00

R2

21

00

+3.

3VC

LK

+3.

3VC

LK

C8

7

.1u

F

C9

0

.1u

FR

38

15

0

R3

31

50

(No

te 1

)

(No

te 1

)

R1

5

15

0

RE

F_SE

LR

EF

_SE

L(S

h 2

)

V_C

TR

L

R1

0

0

R1

4

0(N

ote

1)

(No

te 1

)

R6

0

R9

0

C11

0

56

0p

F

C8

9

.1u

F

+3.

3VC

LK

+C

99

10

uF,

10

V

C4

5

.1u

F

VB

B

VB

B

CD

C_R

EF

1

2345

J6SM

A E

ND

R1

72

0

R11

00

R11

40

R1

71

0

FB

14

FER

RIT

E

+C

22

10

uF

AV

CC

(No

te 1

)

CD

C_P

D

CD

C_R

EF

CD

C_R

EF

(SH

7)

C1

22

.01

uF

C1

31

.00

1u

F

C1

20

.1u

F

C4

9

.1u

F

C6

9

.1u

F

C1

00

.1u

F

C11

2

.1u

F

C11

5

.1u

F

C11

9

.00

1u

F




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FIL

E:

Dra

wn

By:

Eng

inee

r:

ti12

500

TI B

oule

vard

. D

alla

s, T

exas

752

43Ti

tle:

SH

EE

T:O

F:

SIZ

E:

DAT

E:

RE

V:

24

−O

ct−

20

05

DO

CU

ME

NT

CO

NT

RO

L #

TS

W30

00A

57

R. H

OPP

EN

STE

IN

Y. D

EW

ON

CK

1 2 3 4 5 6 7 8 91

011 1

41

3

15

16

17

18

19

20

21

22

23

24

25

12

J1D

B25

F−R

A

R3

41

0K

R3

51

0K

R3

61

0K

R3

71

0K

R3

10

SD

EN

1

SCL

K

SD

IOC2

1

.1u

F

+3.

3VA

SD

IO

SC

LK

SD

EN

1

(Sh

1)

(Sh

1)

(Sh

1)

OE

11

1A1

2

1A2

4

1A3

6

1A4

8

2A1

11

2A2

13

2A3

15

2A4

17

GN

D1

02Y

43

2Y3

5

2Y2

7

2Y1

9

1Y4

12

1Y3

14

1Y2

16

1Y1

18

OE

21

9

VC

C2

0

U4

SN

74

HC

24

1D

W

R1

71

0K

DA

TAC

LKSD

EN

1

SD

EN

2

1OE

1

1A

2

2OE

4

2A

5

1Y

3

2Y

6

GN

D7

3Y

83

A9

3OE

10

4Y

114

A1

2

4OE

13

VC

C1

4

U1

3S

N7

4LV

12

5A

D

CT

RL

_CL

K

CT

RL

_DA

TA

CT

RL

_C

LK

CT

RL_

DAT

A

C2

8.1

uF

+3.

3VA

R2

81

00

R2

7

10

0

R2

9

10

0

R3

0

10

0K

R3

2

10

0K

R3

1

10

0K

C6

1

10

pF

C1

28

10

pF

C1

27

10

pF

+3.

3VA

+3.

3VA

+3.

3VA

(Sh

4)

(Sh

4)

(Sh

4)

CT

RL

_L

E

R1

55

10

K

SD

IO

PLL

_LE

PLL_

DAT

APL

L_C

LKPL

L_LC

K

PL

L_

LE

PLL

_DAT

AP

LL

_C

LK

PL

L_

LC

K

(SH

7)

(SH

7)

(SH

7)

(SH

7)

R2

28

0

R2

29

0

1. D

O N

OT

INS

TALL

(No

te 1

)

(No

te 1

)

CD

C_

LC

KC

DC

_LC

K(S

h 4

)

R2

47

0

R2

48

10

KC

97

10

pF

+3.

3VA

NO

TE

S:




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FIL

E:

Dra

wn

By:

Eng

inee

r:

ti12

500

TI B

oule

vard

. D

alla

s, T

exas

752

43Ti

tle:

SH

EE

T:O

F:

SIZ

E:

DAT

E:

RE

V:

24

−O

ct−

20

05

DO

CU

ME

NT

CO

NT

RO

L #

+3.

3VA

FB3

C4

7

1u

F

C5

7

.01

uF

+C

67

47

uF

TS

W30

00A

67

R. H

OPP

EN

STE

INY

. DE

WO

NC

K

+5V

_PLL

FB6

C5

0

1u

F

C6

0

.01

uF

+C

70

47

uF

C2

7

.1u

F

FB1

+5V

A

+C

12

4

47

uF

+C

116

10

uF,

10

V

+6

VF

B11

+C

25

47

uF

C5

3

1u

F

C1

02

.01

uF

6VJ1

1

RE

D

6V

+C

10

5

47

uF

J17

BL

AC

K

AV

DD

+3.

3VC

LKF

B1

0

C5

4

1u

F

C6

4

.01

uF

+C

74

47

uF

C4

3

.1u

F

R1

30

10

0K

+3.

3VP

LLFB

7

C1

59

1u

F

C1

09

.01

uF

+C

16

0

47

uF

NO

TE

S:

R1

81

0 (No

te 1

)

+6

V

GN

D/H

SIN

K1

GN

D/H

SIN

K2

GN

D3

NC

4

EN

_5

IN6

IN7

NC

8

GN

D/H

SIN

K9

GN

D/H

SIN

K1

0G

ND

/HS

INK

11

GN

D/H

SIN

K1

2

OU

T1

3

OU

T1

4F

B/N

C1

5R

ES

ET

_1

6

NC

17

NC

18

GN

D/H

SIN

K1

9G

ND

/HS

INK

20

U7

TP

S7

67

33

QP

WP

+6

V

+C

117

10

uF,

10

V

C4

8

.1u

F

R1

31

10

0K

GN

D/H

SIN

K1

GN

D/H

SIN

K2

GN

D3

NC

4

EN

_5

IN6

IN7

NC

8

GN

D/H

SIN

K9

GN

D/H

SIN

K1

0G

ND

/HS

INK

11G

ND

/HS

INK

12

OU

T1

3

OU

T1

4F

B/N

C1

5R

ES

ET

_1

6N

C1

7

NC

18

GN

D/H

SIN

K1

9G

ND

/HS

INK

20

U8

TP

S7

67

01

QP

WP

+6

V

+1.

8VD

+C

12

1

10

uF,

10

V

C4

4

.1u

F

R11

3

10

0K

GN

D/H

SIN

K1

GN

D/H

SIN

K2

GN

D3

NC

4

EN

_5

IN6

IN7

NC

8

GN

D/H

SIN

K9

GN

D/H

SIN

K1

0G

ND

/HS

INK

11G

ND

/HS

INK

12

OU

T1

3O

UT

14

FB

/NC

15

RE

SE

T_

16

NC

17

NC

18

GN

D/H

SIN

K1

9G

ND

/HS

INK

20

U6

TP

S7

67

50

QP

WP

+6

V

+C

51

10

uF,

10

V

1. D

O N

OT

INS

TALL

1 32J1

2

3PO

S−PO

WE

R−

JAC

K

R4

2

30

.1K

R4

1

15

.8K

FB

13




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FIL

E:

Dra

wn

By:

Eng

inee

r:

ti12

500

TI B

oule

vard

. D

alla

s, T

exas

752

43Ti

tle:

SH

EE

T:O

F:

SIZ

E:

DAT

E:

RE

V:

24

−O

ct−

20

05

DO

CU

ME

NT

CO

NT

RO

L #

TS

W30

00

7

R. H

OPP

EN

STE

IN

CE

10

RE

FIN

8

LE

13

DA

TA1

2

CL

K11

CPGND 3

AGND 4

DGND 9

RF

INB

5

MU

XO

UT

14

RF

INA

6

RS

ET

1

CP

2

VP

16

DVDD15

AVDD7

U1

4T

RF

37

50

C1

39

10

00

pF

R4

41

K

CL

K

DA

TA

LE

R1

36

20

KC

14

0

10

00

pF

C1

30

.01

uF

C1

41

82

pF

C7

9

.1u

F

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