Trigger & DAQ Ole Hansen SBS Collaboration Meeting 19 March 2010.

Trigger & DAQTrigger & DAQ

Ole HansenOle Hansen

SBS Collaboration MeetingSBS Collaboration Meeting

19 March 201019 March 2010

GEp(5) Trigger GEp(5) Trigger ConsiderationsConsiderations

Very high luminosity, L ≈ 8x10Very high luminosity, L ≈ 8x103838 cm cm-2-2ss-1-1

Open detectors, large solid angleOpen detectors, large solid angle

ChallengesChallenges:

Trigger setup:Trigger setup: Trigger on calorimeter hitsTrigger on calorimeter hits High calorimeter thresholdsHigh calorimeter thresholds Coincidence of e’-p angular correlationsCoincidence of e’-p angular correlations

H(e,e’p) elasticH(e,e’p) elastic

GEp(5) Calorimeter RatesGEp(5) Calorimeter Rates

HCALHCAL ECAL

Electron rate estimate w/2.5 Electron rate estimate w/2.5 GeV threshold (85% of EGeV threshold (85% of Eelaselas): ): ≈ ≈ 60 kHz60 kHz

(CDR section (CDR section 5.1.7)5.1.7)

Hadron rate estimate using Hadron rate estimate using SLAC & DESY data, Wiser code:SLAC & DESY data, Wiser code:w/4.5 GeV threshold: w/4.5 GeV threshold: ≈ 1.5 MHz≈ 1.5 MHz

Background rate vs. cut on deposited Background rate vs. cut on deposited energy energy (MC studies in progress)(MC studies in progress)

≈ ≈ 5 kHz5 kHz coincidence rate coincidence ratew/ 50 ns windoww/ 50 ns window

NB: GoodNB: Goodresolutionresolution≈ ≈ 8%/8%/EE

e’-p Kinematic Correlatione’-p Kinematic Correlation10 x 20 HCAL blocks 20 x 76 ECAL blocks

(CDR section (CDR section F.3)F.3)

Calorimeter SumsCalorimeter Sums10 x 20 HCAL blocks 20 x 76 ECAL blocks

(CDR section (CDR section F.3)F.3)

sum-32

4x37 = 148sum-32

7x17 = 119

sum-16

sum-16

Calorimeter SectioningCalorimeter SectioningHCAL sums of 16: 7x17 = 119 ECAL sums of 32: 4x37 = 148

(CDR section (CDR section F.3)F.3)

7x7

4x10

4x9

Calorimeter SectioningCalorimeter SectioningHCAL sums of 16: 7x17 = 119 ECAL sums of 32: 4x37 = 148

(CDR section (CDR section F.3)F.3)

Rate reduction: x5Rate reduction: x5

correlate49 36

(40)

ECAL SumsECAL Sums

x5

x5

x5

x5

sum-8to ADCs

3

3

3

3

to other

Electronics exists (used with “BigCal” in Hall C)Electronics exists (used with “BigCal” in Hall C)

148 x sum-32

HCAL SumsHCAL Sums

12-bit pipelinedFADCs

CPU

TI

SMART

TRIG

12-bit pipelinedFADCs

x16x8

x200

16x8 bits/16 ns = 8 Gb/sper FADC (!)

.

.

.

4x(7x7) = 196 sum-16logic signals

x196

““SMART Trigger” ModuleSMART Trigger” Module

VME

Deserializer

13 x 8 Gb/s

≈ 2 kBSRAM FIFO

FPGA64 x 8-bit sums& discriminators

VERY PRELIMINARY

FPGA64 x 8-bit sums& discriminators

DigitalOut tocoinc.FPGAs

Fan-out

192

est. processing time 500-800 ns

L2 Coincidence LogicL2 Coincidence Logic

For each calorimeter section (4x):

CAEN 1495FPGA

VME module(160 inputs)

≈50 ns latency

VME

36 (40) x ECAL sum-32

SmartHCALsum,≈≈1 µs1 µs

latencylatency

49 x HCAL sum-16To L2

triggerOR

≈≈1 µs1 µsvariable delay

L1 trigger

Two-Level TriggerTwo-Level Trigger

Level 1Level 1– ≈≈100 ns latency100 ns latency– Generated by electron arm (≈60 kHz rate)Generated by electron arm (≈60 kHz rate)– Gate for Fastbus & non-pipelined VMEGate for Fastbus & non-pipelined VME

Level 2Level 2– Assume up to ≈1 μs latencyAssume up to ≈1 μs latency– FPGA-based coincidence logicFPGA-based coincidence logic– ≈≈1 kHz physics rate1 kHz physics rate– Fast Clear FB & VME after L2 timeout Fast Clear FB & VME after L2 timeout < 10% < 10%

DTDT

DAQ RequirementsDAQ Requirements

Data rate driven by Trackers:Data rate driven by Trackers:

(assuming 2 bytes/channel – 7 bits address, 9 bits (assuming 2 bytes/channel – 7 bits address, 9 bits data)data)

Other detectors, contingency, …Other detectors, contingency, … design for design for ≈100 MB/s≈100 MB/s data rate data rate

Experiment Trigger Rate (kHz)

# GEM channels

Avg. Occupancy

(% )

Event Size (kB)

Data Rate (MB/ s)

GEp(5) 2.5 100,000 15 30 75 GMn, GEn 5.0 30,000 8 4.8 24

12 GeV Upgrade Electronics12 GeV Upgrade Electronics

Under development by JLab DAQ groupUnder development by JLab DAQ group Fully pipelinedFully pipelined 200 kHz L1 trigger rate capability200 kHz L1 trigger rate capability Synchronous trigger distribution, 250 MHz ref. clockSynchronous trigger distribution, 250 MHz ref. clock VME64x front-end crates with support forVME64x front-end crates with support for

– High-speed readout modes (2eVME, 2eSST) up to 200 MB/sHigh-speed readout modes (2eVME, 2eSST) up to 200 MB/s– On-module event buffering - up to 200 eventsOn-module event buffering - up to 200 events– Gigabit uplinks to event builderGigabit uplinks to event builder

CODA 3 softwareCODA 3 software Will use some of this technology + custom modulesWill use some of this technology + custom modules

Future Front EndsFuture Front Ends(graphics from Dave Abbott)(graphics from Dave Abbott)

Trigger Interface (TI)CODA 2 & 3

supportFADC F1TDC

CPU:Intel or MotorolaLinux or vxWorks

Dual GigE >200 MB/sCODA 2 & 3 ROC

Clock/Trigger Signal

Distribution (SD)

Crate TriggerProcessor (CTP)

(optional)

VME64x/VXS Crate

Trigger & Clock

(via fiber)

Data(via

GigabitEthernet)

Hall A Data PathHall A Data Path

ROC ROC

GigabitSwitch

ADAQLEvent

Builder

1x (or 2x) GigE

Trigger & DAQ Trigger & DAQ ResponsibilitiesResponsibilities

New HampshireNew Hampshire– ECAL analog calorimeter summing logicECAL analog calorimeter summing logic

RutgersRutgers– CAEN v1495 coincidence logicCAEN v1495 coincidence logic

INFN Rome & GenovaINFN Rome & Genova– GEM readout electronics & DAQ interfaceGEM readout electronics & DAQ interface

Jefferson LabJefferson Lab– HCAL digital summing electronicsHCAL digital summing electronics– DAQ setupDAQ setup

Norfolk StateNorfolk State– 22ndnd and 3 and 3rdrd tracker front-end electronics tracker front-end electronics

Near-Term PlansNear-Term Plans

Test 10x10 cmTest 10x10 cm22 GEMs during PREX (spring GEMs during PREX (spring 2010) 2010)

GEM VME readout prototypes expected GEM VME readout prototypes expected ready in spring or summer 2010 (maybe for ready in spring or summer 2010 (maybe for PREX)PREX)

Ongoing tests & prototyping with CAEN Ongoing tests & prototyping with CAEN v1495 FPGAs at Rutgersv1495 FPGAs at Rutgers

v1495 radiation hardness test during PREXv1495 radiation hardness test during PREX

CAEN 1495 FPGA CAEN 1495 FPGA PrototypingPrototyping(Rutgers)(Rutgers)

Have 3 v1495s for Fermilab E906Have 3 v1495s for Fermilab E906 Programming & testing of E906 trigger Programming & testing of E906 trigger

conditions (256 inputs) in progressconditions (256 inputs) in progress Gaining experience with hardware and Gaining experience with hardware and

softwaresoftware

SummarySummary

GEp(5) Trigger requires some R&DGEp(5) Trigger requires some R&D– Digital summing logic for HCALDigital summing logic for HCAL– FPGA coincidence logicFPGA coincidence logic

Data Acquisition fairly challenging, but Data Acquisition fairly challenging, but doabledoable– ≈≈100 MB/s data rate @ up to 5 kHz trigger rate100 MB/s data rate @ up to 5 kHz trigger rate– 12 GeV DAQ architecture, CODA 312 GeV DAQ architecture, CODA 3– Pipelined electronicsPipelined electronics– Custom modulesCustom modules

First prototyping & testing underwayFirst prototyping & testing underway