Tri-Level-Cell Phase Change Memory (PCM): Toward an Efficient and Reliable Memory System Nak Hee Seong Sungkap Yeo Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332 [email protected]{sungkap, leehs}@gatech.edu Presented By: Anand Dhole Shalini Satre
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Tri-Level-Cell Phase Change Memory (PCM): Toward an Efficient and Reliable Memory System Nak Hee Seong Sungkap YeoHsien-Hsin S. Lee School of Electrical.
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Tri-Level-Cell Phase Change Memory (PCM): Toward an Efficient and
Reliable Memory System
Nak Hee Seong Sungkap Yeo Hsien-Hsin S. Lee
School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332
ContentsPCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion
PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion
Phase Change Memory (PCM)Promising alternative memory
technologyTwo states
◦Crystalline (SET)◦Amorphous (RESET)
Multi-level-cell PCM◦Intermediate states◦Store more data per cell
Single Level Cell (SLC) [1]
Low resistivityHigh resistivity
Set
Reset
SLC vs MLC
0
1
Two Storage Levels
2LC or SLC = one bit per cell
002
012
102
112
Four Storage Levels
4LC = two bits per cell
SLC PCM
103
# of Cells
SET RESETi
t
i
t
106
103 Difference
MLC PCM
1k
# of Cells
SET RESETi
t
i
t
1M
i
t
StorageLevel 0
StorageLevel 1
StorageLevel 2
StorageLevel 3
Error ModelCritical problems
◦Resistance Drift Resistance of PCM cell increases over time
◦Soft errors Not permanent failure Have solutions to resolve Soft error caused by resistance drift Error rate is proportional to initial resistance value Error rate is negligible in SLC PCM In MLC PCM, resistance drift at intermediate levels
◦ Iterative-writing mechanism Degrades write latency For 4LC, 4x~8x slower than that of SLC [1]
Resistance Drift [1]
# of Cells
SET RESET
T = 1
StorageLevel 0
StorageLevel 1
StorageLevel 2
StorageLevel 3
Decision Boundaries Programmed Boundaries
Resistance Drift
# of Cells
SET RESET
T = 2
StorageLevel 0
StorageLevel 1
StorageLevel 2
StorageLevel 3
Resistance Drift
# of Cells
SET RESET
T = 4
StorageLevel 0
StorageLevel 1
StorageLevel 2
StorageLevel 3
Resistance Drift
# of Cells
SET RESET
StorageLevel 0
StorageLevel 1
StorageLevel 2
StorageLevel 3
Drift-induced Soft Errors!!!
T = 8
Drifted ResistancePower Law Equation
IIdrift
IIdrift
t
tRtR
t
tRtR
101010 log log )(log
)(
Proposed SolutionProposed tri-level-cell PCM
◦Soft error rate matches that of DRAM◦Gain performance of SLC PCM
PCMBackground and MotivationTri-Level-Cell (3LC) PCM3LC PCM in PracticeEvaluationConclusion
Background and Motivation
Flash Memory w.r.t. PCM◦ Switching mem. ele. requires more voltage & time.◦ Degrades more rapidly◦ More susceptible to radiation
Change Memory: Toward an Efficient and Reliable Memory System",ISCA'13
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