1 EE311/ Trends 1 tanford University araswat Prof. Krishna Saraswat Department of Electrical Engineering Stanford University Stanford, CA 94305 [email protected]Trends in Integrated Circuits Technology EE311/ Trends 2 tanford University araswat Courtesy Prof. Tsu-Jae King (Sources: VLSI Research Inc.; United Nation yearbook; World Bank Database; IMF) Miniaturization => Market growth Miniaturization => Market growth Technology Scaling Investment Market Growth Better Performance/Cost Semiconductors have become increasingly more important part of world economy
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1
EE311/ Trends1 tanford Universityaraswat
Prof. Krishna Saraswat
Department of Electrical EngineeringStanford UniversityStanford, CA 94305
Channel• Surface scattering - the “universal mobility” tyranny• DIBL ⇒ drain to source leakage• Subthreshold slope limited to 60mV/decade (kT/q) ⇒ Increased Ioff• VG - VT decrease ⇒ reduced ION
Net result: Bulk-Si CMOS device performance increase commensurate withsize scaling is unlikely beyond the 70 nm node
High E-Field• Mobility degradation• Reliability
te
6
EE311/ Trends11 tanford Universityaraswat
MOSFET Scaling Limit: Leakage
Lo et al.,IEEE EDL, May 1997.
Gate Leakage S/D Leakage
Source: Marcyk, Intel
Total Leakage Trend
Total Power Trends
Ability to control Ioff will limit gate-length scaling– Thermionic emission over barrier– QM tunneling through barrier– Band-to-band tunneling from body to drain
To suppress D/S leakage, need to use:– Higher body doping to reduce DIBL
⇒ lower mobility, higher junction capacitance, increased junction leakage– Thinner gate dielectric to improve gate control ⇒ higher gate leakage– Ultra-shallow S/D junctions to reduce DIBL ⇒ higher Rseries
EE311/ Trends12 tanford Universityaraswat
45
MOSFET Scaling Problem: Saturation of Saturation of IIDsatDsat
200
400
600
800
0.1 0.2
0.25
0.3 0.4 0.6 0.8 1.0
NMOS
PMOS
IDsat (A/m) (drive current)
Channel Length (µm)
• Data from IBM, TI, Intel, AMD, Motorola andLucent
• Low OFF current desirable
0
0.4
0.8
1.2
1990 1995 2000 2005
1
10
Supply
Voltage (
V)
Drive C
urr
ent (m
A/µ
m)
Changhoon Choi, PhD Thesis, Stanford Univ., 2002
Constant OFF current Limit Relaxed OFF current Limit
Source: Intel
Low Vt
High Vt
IOFF,high Vt
IOFF,low Vt
Vg
log Id
0
7
EE311/ Trends13 tanford Universityaraswat
!
Eeff =q
"Si(Ndep +# $ NChannel ) Ndep= depletion charge density
NChannel = charge induced in the channel
Increases in substrate doping ⇒ Ndep ⇑ Gate oxide thickness decrease ⇒ NChannel ⇑ Eeff increases with scaling ⇒ µ ⇓ Reduced gate oxide thickness increases remote charge scattering ⇒ µ ⇓ High k dielectrics have higher coulombic scattering due to surface states
and phonon scattering ⇒ µ ⇓
Coul
ombi
c Phonon
SurfaceRoughness
µ
Eeff
Effects of Scaling Bulk MOSFET on Mobility
S. Takagi et al., IEEE TED, 41 (1994) 2357. srphCeff µµµµ
1111++=
EE311/ Trends14 tanford Universityaraswat
New Structures and Materials forNanoscale MOSFETs
1. Electrostatics - Double Gate - Retain gate control over channel - Minimize OFF-state drain-source leakage2. Transport - High Mobility Channel - High mobility/injection velocity - High drive current for low intrinsic delay3. Parasitics - Schottky S/D - Reduced extrinsic resistance4. Gate leakage - High-K dielectrics - Reduced power consumption5. Gate depletion - Metal gate
1
23
GG
Si
S D Si
SiO2
C
BULK SOI Double gate
Bottom Gate
Top Gate
Source Drain
High µchannel High-K
45
8
EE311/ Trends15 tanford Universityaraswat
Combining New Device Structures withCombining New Device Structures withNew MaterialsNew Materials
We will be here withthese innovations
We arehere today
• With better injection and transport we may be able toimprove MOSFET ION
• With better electrostatics we may be able to minimize Ioff
EE311/ Trends16 tanford Universityaraswat
0.001
0.01
0.1
2000 2010 2020
micron
1
10
100
nm
45 nm
65 nm
32 nm
22 nm
16 nm
11 nm
8 nm
Generation
LGATE
Evolutionary
CMOS Exotic Revolutionary
CMOS
Nanotechnology Eras
ReasonablyFamiliar
NanotubesNanowires
ReallyDifferent
Source: Mark Bohr, Intel
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EE311/ Trends17 tanford Universityaraswat
Scaling of MOS Gate Dielectric
(Ref: S. Asai,Microelectronics Engg., Sept. 1996)
Gate SiO2 thickness is approaching < 10 Å to improve device performance• How far can we push MOS gate dielectric thickness?• How will we grow such a thin layer uniformly?• How long will such a thin dielectric live under electrical stress?• How can we improve the endurance of the dielectric?
ID ! gm !K
thickness
EE311/ Trends18 tanford Universityaraswat
•Below 20 Å problems with SiO2– Gate leakage => circuit instability, power dissipation– Degradation and breakdown– Dopant penetration through gate oxide– Defects
Problems in Scaling of Gate Oxide
Defects and
nonuniformity of film
Dielectric breakdown
Reliability due to
charge injection
Si substrate
Polysilicon gate electrode
Dopant
penetration
gate oxide
Leakage current
10
EE311/ Trends19 tanford Universityaraswat
Dielectric Degradation
What are the mechanisms for damage and breakdown?How can we engineer the gate dielectric to minimize the damage?
• Degradation during device operation due to high E field causing current injection• Degradation during fabrication due to charging in plasma processing
cathode
e
Anode
oxide
Eox
N(E)
E
EE311/ Trends20 tanford Universityaraswat
0.00001
0.001
0.1
10
1000
1801301007050
Technology Generation (nm)
Cur
rent
(µA
/µm
)
Igate
Ioff
Ion
Source G. Bersuker, et al. Sematech
Gate Oxide Scaling Issues: Leakage
• Ion is not increasing with scaling • Igate ⇑, power dissipation ⇑• Circuit instability
11
EE311/ Trends21 tanford Universityaraswat
High-k MOS Gate Dielectrics
K ≈ 20
Historically Cox has been increased by decreasing gate oxidethickness. It can also be increased by using a higher K dielectric
Si3N4 K ≈ 8
40 ÅToday Near future
Long term
20 Å SiO2 K ≈ 4!
ID"C
ox"
K
thickness
100 Å high K
Si
Higher thickness -> reduced gate leakage
Ichannel ∝ charge x source injection velocity∝ (gate oxide cap x gate overdrive) vinj∝ CCoxox (VGS - VT) Esource µµinjinj
EE311/ Trends22 tanford Universityaraswat
Perkins, Saraswat and McIntyre,Perkins, Saraswat and McIntyre,StanfordStanford Univ Univ. 2002. 2002
Capacitance and Leakage for High-k GateDielectric Films Grown Using ALCVD
Gat
e Le
akag
e (A
/cm
2 )
10-10
10-8
10-6
10-4
10-2
100
0 0.05 0.1 0.15 0.2
Leakage (A/cm
2) @ V
FB
± 1 V
1/C'
ox (µm
2/fF)
SiO2
4 nm
2.5 nm
ALCVD ZrO2
Gat
e C
urre
nt@
VFB
+1V
(A/c
m2 )
Equivalent SiO2 Thickness (nm)
Silicon Germanium
Chui, Kim, Saraswat and McIntyre,Chui, Kim, Saraswat and McIntyre,StanfordStanford Univ Univ. 2004. 2004
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EE311/ Trends23 tanford Universityaraswat
!s = f VG( ) =1
"VG
!
ID"QI " eqVG /# kT
!
QI " eq#s /kT
!
" =1+1
2 # C ox
q$sNa
|%p |Where
Subthreshold Behavior
source
VG
• Diffusion of carriers over thebarriers to the channel.
• Fermi-dirac distribution ofcarriers: e-E/kT
• Gate reduces the barrier tocurrent flow.
Fermi Diracdistribution
draine
VT
VDD
ID
(log scale)
VG
ILEAK
or
IOFF
VDD- V
T
60 mV/decade60 mV/decade
ION
ON
OFF
(ln )
G
D
VS
I
!=!
EE311/ Trends24 tanford Universityaraswat
In devices with long channel lengths, the gate is completely responsible fordepleting the semiconductor (QB). In very short channel devices, part of thedepletion is accomplished by the drain and source bias
Since less gate voltage is required to deplete QB, VT↓ as L↓. Similarly, as VD
↑, more QB is depleted by the drain bias, and hence VT↓. These effects areparticularly pronounced in lightly doped substrates.
Effect of Reducing Channel Length
junctiondepletion
region
poly gate
n+ n+
p-substrate
poly gate
n+ n+
p-substrate
depleted by gate charge
VT
Drawn Channel Length, L
VT
Supply Voltage, VD
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EE311/ Trends25 tanford Universityaraswat
p-well
poly gate
n+ n+
VDD
Drain-Induced Barrier Lowering (DIBL)• Exacerbates subthreshold leakage in short-channel devices• Soft punchthrough induced by drain-to-substrate depletion region
• |VT | ↓ as VD ↑ [drain-induced short channel effects (SCE)]• VD ↑ drain-to-substrate depletion region grows with more reverse bias• Lateral electric fields in drain-induced depletion region lowers source-to-
channel barrier, allowing more carriers to diffuse from source to channel
reduction of electron barrierheight in conduction band (CB)
at edge of source
CB
VDD
source drain
p-well
poly gate
n+n+
EE311/ Trends26 tanford Universityaraswat
Q depletedby source
Q depletedby drain
B B
N+ source N+ drain
Gate
P-Si
Depletion region
L!
L
rj
VT = VFB ! 2 "#F !QB
Cox" 1 ! 1+
2 "W
rj!1
$
% &
'
( ) "rj
L
*
+ ,
-
. /
•Roll-off in threshold voltage as the channel length is reduced•VT roll-off is reduced as junction depth(rj) is decreased•Sheet resistance increases as junction depth is reduced
L. Yau, Solid-State Electronics, vol. 17, pp. 1059, 1974
Why do we need to scale junction depth?
14
EE311/ Trends27 tanford Universityaraswat
Source: Jasonn Woo, UCLA
30 nm 50 nm 70 nm 100 nm0
20
40
60
80
100
120
140NMOSScaled by ITRS Roadmap
Rc
Rdp
Rext
Rov
Physical Gate Length
Serie
s R
esis
tanc
e (o
hms)
Rc RdpRext
Rov
x
y = 0
GateSiO2
Metal
Next(x)
Nov(y)
Source/Drain Resistance
Problem in junction scaling:• Sheet resistance of a junction is a strong function of doping density• Maximum doping density is limited by solid solubility and it does not scale• Silicidation can minimize the impact of junction sheet resistance (Rs,Rd)• Contact resistance Rc is one of the dominant components for future technology
EE311/ Trends28 tanford Universityaraswat
Contact Resistance
Specific contact resistivity
Doping density
(Ref: S. Swirhun, PhD Thesis, Stanford Univ. 1987)
!c = !co exp2"Bqh
#sm*
N
$
% & &
'
( ) ) ohm * cm2
• Contact resistance is a strong function ofdoping density at the metal/silicon interface
• Solid sulubility of dopants does not scale !
PROBLEMS
15
EE311/ Trends29 tanford Universityaraswat
Solutions to Shallow JunctionResistance Problem
Extension implants Elevated source/ drain
Silicidation Schottky Source/Drain
EE311/ Trends30 tanford Universityaraswat
Problems with Poly-Si Gate.This occurs because of high E - field due to a combination of highersupply voltage and thinner gate oxide.
• Effect of depletion is to increase effective tox and thus reduce Cox• A reduced Cox implies reduction in gm and thus ID(on)• Ionized impurities in the gate electrode cause “remote charge scattering”
⇒ Reduced mobility
tox(electrical)
tox(physical)
Gate depletion
Oxide
Substrate
Poly-Si gate
Need metal gate electrode with proper workfunction
16
EE311/ Trends31 tanford Universityaraswat
Ultra-Thin Body Single Gate SOI
Ultra-Thin Body DoubleGate SOI
Evolution of MOSFET Structures
GateGate
Silicon Substrate
Source Drain
TBOX
Si
SiO2
SOI
Source Drain
Gate 1Gate 1 Vg
Tox
SOI
Gate 2Gate 2
Si
Ref: Philip Wong, IEDM Short Course, 1999
BULK
Advantages of Ultra-Thin Body SOI• Depleted channel ⇒ no conduction path
is far from the gate• Short channel effects controlled by
geometry• Steeper subthreshold slope• Lower or no channel doping• Higher mobility• Reduced dopant fluctuation
EE311/ Trends32 tanford Universityaraswat
Non PlanarNon Planar MOSFETs
UC Berkeley
Gate
Source Drain
Intel
Tri Gate FET
SourceSource DrainDrain
GateGate
SiO2
Channel
Double Gate FinFETVertical FET
Stanford, AT&T
17
EE311/ Trends33 tanford Universityaraswat
Transport: Effects of Biaxial Tensile Strain on Si Energy BandsHoyt, 2002
- reduced intervalley scattering- smaller in-plane effective transport mass
Δ2
Δ4
[001]
[010]
[100]
Δ Es ~ 67 meV/ 10% Ge
Δ4
Δ2
Δ6Ec
Bulk Si Strained Si
µ = q!
m*c
Strained Si grown on Relaxed Si1-xGex
biaxial tension
HH
LH
Spin-Orbit
E EValence Band
HH/LH degeneracy lifted at Γ
- reduced interband scattering- smaller in-plane transport mass due to band deformation
Γ
Bulk Si Strained Si
in-planeout-of-plane
kk
Δ Es ~ 40meV/10% Ge
ml
mtmt
mt < ml
Single ellipsoid
EE311/ Trends34 tanford Universityaraswat
Strained Si gate oxide
Si Substrate
Relaxed Si1-xGex
n+ poly LTOspacer
n+ n+
Si1-xGex Graded layer
0.80
1.0
1.2
1.4
1.6
1.8
2.0
0.0 0.10 0.20 0.30 0.40
Mobility enhancement ratio
Substrate Ge fraction, x
VDS
= 10 mV
300 K
Measured, J. Welser, et al.,
IEDM 1994.
Calculated for strained Si
MOS inversion layer
S. Takagi, et al., J. Appl. Phys. 80, 1996.Mob
ility
Enh
ance
men
t Fac
tor
NMOS
Mobility Enhancements in Strained-Si MOSFETs
Intel
PMOS
Gibbons Group, Stanford
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EE311/ Trends35 tanford Universityaraswat
Nanowire and Nanowire and Nanotube FETsNanotube FETsALD HfO2 Coated of Ge NW FET
sourcegate
drain
dielectric
semiconductor
~20nmmetal
~10nm
Channel
Au
Nanoparticle
GeContaining
Vapor
Ge Nanowire
Ge NW Growth
Key Challenge: Controlled growthCatalyst Support
CnHmCnHm Fe
Gate
HfO2
10 nm SiO2
p++ Si
SD
Carbob Nanotube MOSFETCarbob Nanotube Growth
EE311/ Trends36 tanford Universityaraswat
B
+ =
Spintronics
Seemingly Useful Devices
Limited Current DriveCryogenic operation
Limited Fan-OutCritical dimension control
Need high spin injectionand long spin coherence time Limited thermal stability
New architectures needed
~ 2 nm
Challenging fabricationand process integration
CarbonNanotubes
Controlled growth
19
EE311/ Trends37 tanford Universityaraswat
• In general this device scaling methodologydoes not take into account many other chipperformance and reliability issues, e.g.,interconnects, contacts, isolation, etc.
• These factors are now becoming an obstaclein the evolution of integrated circuits.
EE311/ Trends38 tanford Universityaraswat
Device Isolation pitch as a function ofminimum dimension
With decreasing feature size the requirement onallowed isolation area becomes stringent.
0.0 0.2 0.4 0.6 0.8 1.0Minimum dimension [µm]
0.0
0.5
1.0
1.5
2.0
2.5
16M
64M
1G
P. Fazan, Micron, IEDM-93
Activ
e Ar
ea p
itch
(µm
)
20
EE311/ Trends39 tanford Universityaraswat
Scaling of Device Isolation
NitridePad oxide
Fully recessed LOCOS
Nitride Pad oxide
Semi-recessed LOCOSNitride
Field oxide
After field oxidation
After field oxidation
LOCOS based isolation technologies have serious problemsin loss of area due to bird’s beak.
Deep trench isolation
N-wellP-substrate
Shallow trench isolation
Trench isolation can minimize area loss
EE311/ Trends40 tanford Universityaraswat
Scaling of interconnections
OldNew (scaled)
• Bigger chip => longer interconnects• Scaling to smaller dimensions => reduced cross section• Larger R, L and C
21
EE311/ Trends41 tanford Universityaraswat
Interconnect Delay Is Increasing
• Chip size is continuallyincreasing due toincreasing complexity– Increase in R, L and C
• Device performance isimproving but interconnectdelay is increasing
• Need better materials– Metal with lower resistivity– Dielectrics with lower K– Other solutions, e.g., 3D,