TREE Adders - University of Wisconsin–Madisonpages.cs.wisc.edu/.../handouts/case-study/Shoaib_parall… · PPT file · Web view2009-11-24 · Parallel Prefix Adders A Case Study

Parallel Prefix Adders

A Case Study

Muhammad Shoaib Bin AltafCS/ECE 755

Outline

• Motivation• Introduction• Various Tree adders• Comparison• Layout of Kogge-Stone• Conclusion

Motivation

• Addition: a fundamental operation– Basic block of most arithmetic operations– Address calculation

• Faster, faster and faster• How?

– Ripple Carry Adder Look Ahead– Carry Select, carry Skip– Good for small number of bits but…– Need some change for wider adders

Square root select

Linear select

Ripple adder

20 40N

t p(in

uni

t del

ays)

600

10

0

20

30

40

50

Propagate and Generate Logic

• For a full adder, define what happens to carries– Generate: Cout = 1 independent of C

• G = A • B

– Propagate: Cout = C• P = A B

Prefix Adder Equations• Equations often factored into G and P• Generate and propagate for groups

spanning i:j

• Base case

• Sum:

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P G

P P P

:

:

i i i i i

i i i i i

G G A BP P A B

0:0 0

0:0 0 0inG G C

P P

1:0i i iS P G 3:0 3:0 3:3 3:3 2:0G C G P G

3:0 3:0 3:2 3:2 1:0G C G P G

Notations

Ripple Carry Adder

S1

B1A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4 Cin

G0 P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC0C1C2C3

Cout

C4

Ripple Carry Adder

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0C C C C C C C C C C C C C C C C

15:15 14:14 13:13 12:12 11:11 10:10 9:9 8:8 7:7 6:6 5:5 4:4 3:3 2:2 1:1 0:0G G G G G G G G G G G G G G G G

7:0 7:7 7:7 6:0C G P G

3:0 3:3 3:3 2:0C G P G

11:0 11:11 11:11 10:0C G P G

15:0 15:15 15:15 14:0C G P G

Look Ahead Basic ideaAN-1, BN-1A1, B1

P1

S1

• • •

• • • SN-1

PN-1Ci, N-1

S0

P0Ci,0 Ci,1

A

:0 1:0 1:0( , , )k k k k k k kC f A B C G PC

Lookahead: Topology

Expanding Lookahead equations:

All the way:Co,3

Ci,0

VDD

P0

P1

P2

P3

G0

G1

G2:0 1 1 2:0( )k k k k k kC G P G P C

:0 1 1 1 0 0 0( (.... ( )))k k k k kC G P G P P G PC

Logarithmic Lookahead Adder

A7

F

A6A5A4A3A2A1

A0

A0A1

A2A3

A4A5

A6A7

F

tp log2(N)

tp N

Carry lookahead Trees

1:0 1 1 0 1 0 0

2:0 2 2 1:0

2:0 2 2 1 2 1 0 2 1 0 0

2 2 1 2 1 0 0 0

2:1 2:1 0

( ) ( )( )

C G PG PPCC G PGC G PG P PG P PPCG PG P P G PCG P C

• This idea can be extended to build hierarchal trees

Prefix Adder Structure

• Implement the idea of Carry Lookahead tree

Brent-Kung Adder

• Stages– 2(logN-1)

• Fan out– 2

• Avoids Explosion of wires• Odd Computation then

even• In any row at the most

one pair

Brent-Kung Adder3:2 3:3 3:3 2:2C G P G 15:14 15:15 15:15 14:14C G P G

7:0 7:4 7:4 3:0C G P G 15:8 15:12 15:12 11:8C G P G

4:0 4:4 4:4 3:0C G P G 14:0 14:14 14:14 13:0C G P G

Sklansky Adder

• Stages– Log N

• Fan out– Doubles at each level

• Large delay at end

Sklansky Adder3:2 3:3 3:3 2:2C G P G 15:14 15:15 15:15 14:14C G P G

3:0 3:2 3:2 1:0C G P G 15:12 15:14 15:14 13:12C G P G

7:0 7:4 7:4 3:0C G P G 15:0 15:8 15:8 7:0C G P G

Kogge-Stone Adder

• Stages– Log N

• Fan out– 2 at each stage

• Long wires• More PG cells Power• Widely Used

Kogge-Stone Adder3:2 3:3 3:3 2:2C G P G

15:14 15:15 15:15 14:14C G P G

3:0 3:2 3:2 1:0C G P G 15:12 15:14 15:14 13:12C G P G

7:0 7:4 7:4 3:0C G P G 15:0 15:8 15:8 7:0C G P G

Han-Carlson Adder

• Mix of Kogge-Stone and Brent-Kung

• Stages– Log N +1

• Fan out– 2

• Trades logical level for wire length

• In any row at the most one pair

Han-Carlson Adder3:2 3:3 3:3 2:2C G P G 15:14 15:15 15:15 14:14C G P G

5:0 5:2 5:2 1:0C G P G 15:8 15:12 15:12 11:8C G P G

7:0 7:4 7:4 3:0C G P G 15:0 15:8 15:8 7:0C G P G

Knowles Adder

• Using Kogge-stone and Sklansky

• Stages– Log N

• Fan out– 3

• Wires

Knowles Adder3:2 3:3 3:3 2:2C G P G 15:14 15:15 15:15 14:14C G P G

5:0 5:2 5:2 1:0C G P G

15:8 15:12 15:12 11:8C G P G

7:0 7:4 7:4 3:0C G P G 15:0 15:8 15:8 7:0C G P G

4:3 4:4 4:4 3:3C G P G

8:0 8:1 8:1 0:0C G P G

Ladner-Fischer Adder

• By Combining Brent-Kung and Sklansky

• Stages– Log N +1

• Fan out– N/4 +1

• Wires

Ladner-Fischer Adder3:2 3:3 3:3 2:2C G P G 15:14 15:15 15:15 14:14C G P G

5:0 5:4 5:4 3:0C G P G 13:8 13:12 13:12 11:8C G P G

7:0 7:4 7:4 3:0C G P G 15:0 15:8 15:8 7:0C G P G 8:0 8:8 8:8 7:0C G P G

Comparison Among Adders

N=16 N=32 N=64 N=128

Brent-Kung 10.4 13.7 18.1 24.9

Sklansky 13 21.6 38.2 70.8

Kogge-Stone 9.4 12.4 17 24.8

Han-Carlson 9.9 12.1 15.1 19.7

Knowles 9.7 12.7 17.3 25.1

Ladner-Fischer

9.9 11.5 14.9 18.9

Carry Incre. 15.7 27.5 46.8 84.3

Logical effort of carry propagate adders, David Harris, 2003

In term of delays

If wire capacitance neglected Kogge-Stone is best

Valency of a Tree

• Valency– Number of groups

combine together to make larger groups

– Earlier examples were of valency 2

– High Valency• Less logic levels• Each stage has grater delay

– Doesn’t make sense for static CMOS

Sparseness of Tree

• Compute Carries for blocks only

• Reduce– Wire count– Gate count– Power

Implementation of KS Adder

• Domino Logic when performance is major concern

VDD

Clk Pi= ai + bi

Clk

ai bi

VDD

Clk Gi = aibi

Clk

ai

bi

PropagateGenerate

Implementation of KS Adder

VDD

Clkk

Pi:i-k+1

Pi-k:i-2k+1

Pi:i-2k+1

VDD

Clkk

Gi:i-k+1

Pi:i-k+1

Gi-k:i-2k+1

Gi:i-2k+1

Propagate Generate: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P G

P P P

Layout of KS Adder

64 bit Adder

Layout of KS Adder

• Area completely dominated by wires–

• Delay– 7.46 ns

• Power– 26.1 mW

• 904 Cells with 8 levels• A comparison with 3D implementation is also given

235.4k m

Few Observations

• Wire delay exceeds logic delay in many cases• The wire delay increases with width of adder• Effect of feature size• 3D stacking can help in decreasing area,

power and delay

Conclusion

• Fast Adders required for N>32• Irregular hybrid schemes are possible• Kogge-Stone, Knowels require large number of

parallel wiring tracks• Large wires will increase wiring capacitances• Choice is yours….• Trade off between delays and Area• 3D integration can help in reducing the delays

further