transmission gate and pass transistor logic.pdf

7/27/2019 transmission gate and pass transistor logic.pdf

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Pass Transistor CircuitsThe CMOS Transmission Gate

Design ExampleTransmission Gate Design Methodology

Pass Transistor Circuits

Dr DC Hendry

October 2007

Dr DC Hendry Pass Transistor Circuits
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Outline I

1 Pass Transistor Circuits

2 The CMOS Transmission Gate

3 Design Example

4 Transmission Gate Design Methodology

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We can view the complementary CMOS gate as switching theoutput pin to one of power or ground.

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A slightly more general gate is obtained if we switch theoutput to one of power; ground; or any of the input signals.


P T i Ci i
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In such designs the MOSFET is considered to be a passtransistor.


P T i t Ci it
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In such designs the MOSFET is considered to be a passtransistor.

When used as a pass transistor the device may conductcurrent in either direction.


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Pass Transistor Truth Table

XA

B


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XA

B

A B X

0 0 Z


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XA

B

A B X

0 0 Z0 1 0


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XA

B

A B X

0 0 Z0 1 01 0 Z


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The CMOS Transmission GateDesign Example

Transmission Gate Design Methodology


XA

B

A B X

0 0 Z0 1 01 0 Z1 1 1


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Properties of Pass Transistors

For the n-channel pass transistor circuit note that:

1 Z in the truth table implies a floating node.


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2 For the n-channel pass transistor, when A = B = 1, theoutput voltage at X is:

Vx = min(VB Vt,VA)


Pass Transistor CircuitsC OS G
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Vx = min(VB Vt,VA)

3 This ifVA = VB = 3.3V and Vt = 0.6V then Vx = 2.7V.


Pass Transistor CircuitsTh CMOS T i i G
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Vx = min(VB Vt,VA)

3 This ifVA = VB = 3.3V and Vt = 0.6V then Vx = 2.7V.4 This reduction in output voltage makes cascading of pass

transistor circuits difficult.


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Cascaded Pass Transistors

Vdd 3Vt

Vdd

Vdd 2Vt

Vdd

Vdd

Vdd

Vdd Vt

Figure: Cascaded pass transistors


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Cascaded Pass Transistors - 2

1 With an n-channel transistor high voltages are degraded byone Vt.


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2 Similar circuits with a p-channel device degrade (byincreasing) a logic zero by one Vt.


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3 So such circuits are normally confined to the internal circuitryof a gate.


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3 So such circuits are normally confined to the internal circuitryof a gate.

4

Full logic levels can be regenerated with an inverter at theoutput of the gate.




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Two-to-One Mux

ZS

S

B

A

Figure: Two-to-one Mux


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Two-to-One Mux - 2

When S = 1 the output Z is connected to B




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Two-to-One Mux - 2

When S = 1 the output Z is connected to BWhen S = 0 the output Z is connected to A



D i E l
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Two-to-One Mux - 2

When S = 1 the output Z is connected to BWhen S = 0 the output Z is connected to A

Note that the connection made is bidirectional



D i E l
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The CMOS Transmission Gate

The CMOS transmission gate consists of two MOSFETs, onen-channel responsible for correct transmission of logic zeros,



Design Example
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The CMOS transmission gate consists of two MOSFETs, onen-channel responsible for correct transmission of logic zeros, andone p-channel, responsible for correct transmission of logic ones.



Design Example
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The CMOS transmission gate consists of two MOSFETs, onen-channel responsible for correct transmission of logic zeros, andone p-channel, responsible for correct transmission of logic ones.

B

C

C

A

Figure: CMOS Transmission Gate Circuit

When C = 1, A and B are connected, both logic zero and logic oneare passed without degradation.Dr DC Hendry Pass Transistor Circuits


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Transmission Gate Symbols

Transmission gates are widely used and shorthand symbols areused.



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The standard symbol (not used often) is:

C

A B

C



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g pTransmission Gate Design Methodology



The standard symbol (not used often) is:

C

A B

C

The most commonly used symbol is simply:A B

C



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g pTransmission Gate Design Methodology

Design Example:

A common design technique used with transmission gate structuresis the use of multiplexor based architectures. Consider the Booleanfunction



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Design Example:


f= AS2S1 + BS2.S1 + S2S1



Design ExampleT i i G D i M h d l
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Design Example:


f= AS2S1 + BS2.S1 + S2S1

This may be rewritten as (the reason will become clear later):

f= AS2S1 + BS2.S1 + 1.S2S1 + 0.S2S1



Design ExampleT i i G t D i M th d l
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Transmission Gate Implementation:

f

S1 S1 S2 S2

A

B

1

0

Figure: Implementation with Transmission Gates

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Pass Transistor CircuitsThe CMOS Transmission GateDesign Example



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Transmission Gate Implementation - 2

1 Note the need for the term 0.S1S2. If not present then whenS1 = S2 = 1 the output f would float.

2 Each transmission gate may now be replaced with two

transistors.





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transistors.3 Where lines connect only to logic 1 the nMOS devices may be

omitted.





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omitted.

4 Where lines connect only to logic 0 the pMOS devices may be

omitted.



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a s ss o Gate es g et odo ogy





omitted.

4 Where lines connect only to logic 0 the pMOS devices may beomitted.

5 nMOS and pMOS devices may be grouped to minimise thenumber of wells required.





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g gy

Transistor Schematic

Vdd

A

B

S2 S2 S1 S1

f

Figure: Transistor Level Schematic for Design



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Design Methodology

A suitable design methodology, in addition to the correct logicoutput, must ensure:



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Design Methodology


The output is always driven to logic 1 or logic 0.



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Design Methodology


The output is always driven to logic 1 or logic 0.There are no sneak paths, such as:

B

f

1

0

A



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Viable Approaches

Viable design approaches are:

Choose a number of inputs as mux select inputs and proceedas above.



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Viable Approaches



Plot variables on K-maps.



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Viable Approaches



Plot variables on K-maps.

Tabular methods such as modifications of Quine-McCluskey -

not covered here.



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Plotting Variables

f= ab+ bcd+ acd



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Plotting Variables

f= ab+ bcd+ acd

and we will look for a network using d and d as inputs. Plottingthe function on a K-Map gives:



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Plotting Variables

f= ab+ bcd+ acd

and we will look for a network using d and d as inputs. Plottingthe function on a K-Map gives:

f ab

cd

00 01 11 10

10

11

0100 1 1 1 0

1 0 0 0

1 0 1 1

1 0 0 0Dr DC Hendry Pass Transistor Circuits


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Plotting again with d as input

Now plot the K-Map using d as an input, giving:



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f ab

c

00 01 11 10

1

0 1 d d 0

1 0 d d




Pl i i i h d i
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f ab

c

00 01 11 10

1

0 1 d d 0

1 0 d d

Giving the Boolean expression for f as:

f= 1.ab+ bcd+ ac.d+ abc.0 + abc.0

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transmission gate and pass transistor logic.pdf

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