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Transmeta’s New Proces sor Another way to design CPU By Wu Cheng Meng @csie.ccu. edu.tw
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Transmeta’s New Processor

Jan 22, 2016

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Transmeta’s New Processor. Another way to design CPU. By Wu Cheng Meng @csie.ccu.edu.tw. What’s Crusoe CPU. X86 ISA Compatible Simple VLIW Hardware Software/Hardware Mixed Architecture Low Power Self-Turning of Clock & Voltage. Structure. Structure. X86 Applications. - PowerPoint PPT Presentation
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Page 1: Transmeta’s New Processor

Transmeta’s New Processor

Another way to design CPU

By Wu Cheng Meng @csie.ccu.edu.tw

Page 2: Transmeta’s New Processor

What’s Crusoe CPU

• X86 ISA Compatible

• Simple VLIW Hardware

• Software/Hardware Mixed Architecture

• Low Power

• Self-Turning of Clock & Voltage

Page 3: Transmeta’s New Processor

Structure

Page 4: Transmeta’s New Processor

Structure

X86 Applications

X86 BIOS

Code Morphing Software

X86 Operating System

VLIW Processor

Page 5: Transmeta’s New Processor

VLIW Hardware

• 64/128 bits molecule

• 2 Integer, 1 Float, 1 LD/ST, 1 Branch

• Optimized for simple, fast and low-power

[F]ADD BRCCLDADD

128 bit molecule

Page 6: Transmeta’s New Processor

Code Morphing Layer

• Started When Boot

• Translate/Optimize ISA to Native ISA

• Insert Instrument Code to …– Execute path analysis– Detect CPU need for efficient power

consuming– Any other analysis ..

Page 7: Transmeta’s New Processor

Code Morphing Layer

8-16M

Physical Memory on main-board

Code Morph itself And Translated Code Cache

Virtual Physical Memory BIOS and OS can see

Page 8: Transmeta’s New Processor

Translation Step

Interpretation Translate one instruction at a time

Simple-minded Optimize Code that Compilers do

Highly Optimized Reorder the instructions and make parallelism

Page 9: Transmeta’s New Processor

Special Issues for X86

• Generate Same Condition Code

• Operates same 80-bit floating point

• TLB has same protection bits

• TLB address mapping as X86 processors

Page 10: Transmeta’s New Processor

Precise Interrupt

• Precise Interrupt– Shadow Registers (int / fp)– Gated Store Buffer– Commit Operation– Rollback Operation

Page 11: Transmeta’s New Processor

Alias Hardware

• Alias Hardware (Memory)– Reorder limited by load/store pairs– Load-and-protect

• Save address and size of loaded data

– Store-Under-Alias-Mask• Check alias hardware

• Raise exception when overwrite

Page 12: Transmeta’s New Processor

Example of Aliasld %r30, [%x] // first load from location x

st %data, [%y] // might overwrite location x

ld %r31, [%x] // this accesses location X again

use %31

ldp %r30, [%x] // load from location x and protect it

stam %data, [%y] // traps if it writes x

use %30 // may use data from first load

Page 13: Transmeta’s New Processor

Self-Modifying Code

• Keep a “translated” bit in MMU

• When a protected page is written– Invalidate the affected translation(s)

Page 14: Transmeta’s New Processor

Low Power!!!

Pentium!!! Crusoe

Reduced Power Consumption mainly by reduced x86 decode logic