August 24, 2010 Solving 4G Challenges for Pico, Micro and Macrocell Platforms Jim Johnston CTO Communications Convergence Processing Mindspeed Technologies, Inc. Transcede ™
August 24, 2010
Solving 4G Challenges for Pico, Micro and Macrocell Platforms
Jim JohnstonCTO
Communications Convergence Processing
Mindspeed Technologies, Inc.
Transcede ™
Nasdaq: MSPD
+
New Networked Applications
The Next Internet Wave – Mobility and Content
Explosive demand for Mobile Broadband=
Innovative New Platforms
2
Nasdaq: MSPD
Impact on Service Providers
… Overloaded Networks
Source: Infonetics Q4’2009
0
100
200
300
400
500
600
700
800
900
1,000
CY04 CY05 CY06 CY07 CY08 CY09 CY10 CY11 CY12 CY13
Su
bsc
rib
ers
(M
)
Wireline broadband Cellular mobile broadband
TB Per Month
2009 2010 2011 2012 2013 2014
1,800,000
3,6000,000
109% CAGR 2009-2014
0.09 EBper mo
0.2 EBper mo
0.6 EBper mo
1.2 EBper mo
2.2 EBper mo
3.6 EBper mo
3
Source: 2010 Cisco VNI Mobile
Nasdaq: MSPD
eNode B
PA
D/A
A/D
Equ.OFDMA
MODEMaGW
FEC
SecurityIP Packet
IP Packet
MAC
MIMO
4G LTE -2010
QoS
Mobility Management
RFNative IP Packets
2G to 4G - System Architecture Evolution- to the Evolved Packet Core
BTS BSC
MSCPA
D/A
A/D
Equ.
TDMA
MODEMTRAU
Speech codec
FECA-bis: TDMA: TDM
2G GSM – 1990s
RF PSTN
Time Slots-DSx
Node B
PA
D/A
A/D
Equ.
CDMA
MODEMRNC SGSN
Serving GPRS
Support Node
GGSNGateway GPRS
Support Node
FEC
IP Packets
Over ATM Cells/TimeSlots
IP Packet3G W-CDMA – 2000s
Media GW
Video processing
Speech Codec
Voice band dataQoS
Security
Mobility Mgt
MAC
RF
Mobile
Operator Core
Network
Packet Switching
4
Nasdaq: MSPD
Mobile Broadband Architecture – Going Distributed
Supported Subscribers
1200 400 200 50 10
BusinessPico Femto
Residential
Enterprise
Femto
BusinessMetroBusinessBusiness
Micro
Urban
Macro
Metro High-Density Subs
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Serving a broad range of basestations - from Macro to Femto
Nasdaq: MSPD
Mindspeed SoC Competencies
Multi-Processor
Communications Technologies
AlgorithmsStandards
Certification
Power density (dB)
Frequency
Convergence Applications
Voice, Video,
and Modems
Packet
Processing
Multi-Core Software
Software
Architecture
Software
Verification
6
Nasdaq: MSPD
IQ - CPRI
CevaXDSP
FFTRAKE
Cortex A9s
Cortex A9sCipher
FEC
IPEthernet
Transcede™eNodeBs
SoCs
SiliconArchitecture
Evolution
RoHC
Application
Specific
Architecture
Solution
Silicon & System Architecture Innovation
IQ - Proprietary
FPGAs
OldBTS
Solutions
FPGAs
DSPs DSPs
NetworkProcessors
AbisT1/E1-ATM
IQ - CPRI
LTE PHY
LTE MAC
LTE RLC
LTE PDCP
LTE RRCIP
Ethernet
eNodeB Protocol
Stack
SystemArchitecture
Evolution
Application Agnostic ComponentArchitecture
Solution
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Nasdaq: MSPD
< $300
Transcede™ Dramatically Reduces System BOM
… while significantly accelerating Time-to-Market
App I/O
App Hardware
Accelerator
DSP Farm
NPUs
FPGAs
> $3000
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Nasdaq: MSPD
eNB Transcede™ - Multi-Core SoC
T4000:
600MHz/300MHz
T4020:
750MHz/366MHz
NoC: AXI Packet Network on Chip
MAP
MAP
High Performance SERDES IO
High Performance DSP Farm
High Performance SMP RISC
General Purpose Peripherals
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Nasdaq: MSPD
Processors: Instruction and Data Level Parallelism
600MHz to 750MHz Operation
4 A9 Multi-Processing Cores
SMP & AMP support
Parallel Cores with HW Snoop Logic
32bit Instructions
Load/Store Register File
13 stage Pipeline
Small L1 Memories
32kB Program Cache
32kB Data Cache
Large L2 Memories
512kB Unified Cache
Embedded Trace Module
Complex Instruction Diagnostics
Dual Data/Program DMA/Cache
Extensive Tool Chain
C-Compliers/Debugger/etc.
High Efficiency
Instruction Level
Parallelism
600MHz to 750MHz Operation
256bit-8 Way VLIW DSP
8-32bit Parallel Instructions
Most common size
16-16bit Parallel Instruction
9 stage Pipeline
128bit 4/8 MAC SIMD
4- 16bit x 16bit MACs
8- 8bit x 8bit MACs
Large L1 Memories
96kB Program RAM
Direct Mapped Cache Option
128kB Data RAM
Banked Simultaneous Access
On-chip Emulation Module
Complex Breakpoints/Trace/etc.
Dual Data/Program DMA/Cache
Extensive Tool Chain
C-Compliers/Debugger/etc.
High Efficiency
Instruction & Data Level
Parallelism
600MHz to 750MHz Operation
160bit-VLIW DSP
Fine Grain VLIW
160bit SIMD
24bit x 16bit MACs
Built in FFT Radix Support
Large L1 Memories
10kB Program RAM
80kB Data RAM
Banked Simultaneous Access
External Sequencer Control
High Performance DMA
Side-band Multi-Core SequencingControl Channel
Processor to Processor Pipelined Data Flow
High Efficiency Data Level Parallelism
MAP
11
Nasdaq: MSPD
Processors: Instruction and Data Level Parallelism
12
Cortex- A9CPU
High Core Level Instruction Parallelism
Control/Branch Code Focus
Symmetric Multi-Core Instruction Parallelism
Nasdaq: MSPD 13
600MHz to 750MHz CevaX1641 8-way VLIW DSP
600MHz to 750MHz Operation
256bit-8 Way VLIW DSP 8-32bit Parallel Instructions
Most common size
16-16bit Parallel Instructions
128bit 4/8 MAC SIMD 4- 16bit x 16bit MACs
8- 8bit x 8bit MACs
Large L1 Memories 96kB Program RAM
Direct Mapped Cache Option
128kB Data RAM
Banked Simultaneous Access
On-chip Emulation Module Complex Breakpoints/Trace/etc.
Dual Data/Program DMA/Cache
Extensive Tool Chain C-Compliers/Debugger/etc.
High Core Level Instruction Parallelism
Launch Rate Focus
High Core Level Data Parallelism
Parallel Math Focus
Nasdaq: MSPD
Mindspeed Application Processor
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Programmable Application Specific Signal Processing
CevaXCore L1
RAM
L1RAM
L1RAM
62.5% RAM, 37.5% Core
General Purpose Signal Processor
MAPCore
L1RAM
L1RAM
L1 RAM
45% RAM, 55% Core
Application Specific Signal Processor
Simplified Instruction PipelineLimited Control Code Focus
Small PRAM , L1 sized to limited function focus
FFT/DFTCore
L1RAM
L1RAM
35-40% RAM, 60-65% Core
Fixed Function Signal Processing
No InstructionsState Machine Control
RAM sized to one function
Limited Savings For Loss
In Application Flexibility
Nasdaq: MSPD
Mindspeed Application Processor (MAP)
600MHz to 750MHz Operation
160bit -1 Way VLIW DSP
160bit 4 MAC SIMD
- 4- 24bit x 16bit MACs
Built in FFT Radix Support
- Bit Reverse Addressing
Circular Buffering
Built in Byte Data RAM read
Very Wide/Large L1 Memories
- 10kB Program RAM,
- 80kB Data RAM
- Banked Simultaneous Access
External Sequencer Control
High Performance DMA for Data
4G/3G Application Library
15
Nasdaq: MSPD
CoreSight™ SoC HW SW Debug Support
Tightly coupled MAC/PHY
Streaming Real-Time Debug Capability!
16
Nasdaq: MSPD
Transcede™ 4000 SoC
Multi-LayerBus Structure
Mul
ti-La
yer
Bus
Str
uctu
re
Multi-LayerBus Structure
L2DSP RAM
L2DSP RAM
L2DSP RAM
CevaX1641
CevaX1641
CevaX1641
CevaX1641
CevaX1641
CevaX1641
CevaX1641
CevaX1641
CevaX1641
CevaX1641
MSPDMAP
MSPDMAP
MSPDMAP
MSPDMAP
MSPDMAP
MSPDMAP
MSPDMAP
MSPDMAP
MSPDMAP
MSPDMAP
MAPDMAs
ARMA9
ARMA9
L2Cache
MP Core+L1
ARMA9
ARMA9
ARMA9
ARMA9
L2Cache
L2Cache
MP Core+L1
FEC
sRIO
PCIe
CPRI
DDR3 DDR3
L3 SRAM
L3 SRAM
GigEMAC
GigEMAC
10-H
igh
Spe
ed S
erde
s TSMC 40G Process 0.9V
12W typical
31mm x 31mm
26 Processors
9.1MBytes RAM
>300M transistors
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Nasdaq: MSPD
Chainable Processing Tiles (Optical-20km or Electrical-20cm)
Seamless Scalability (Switchless)
Resulting In Lowest: Power, Cost, Area
Optical PMA
Optical PMA CP
RI
sRIO
T4K DSP+NP
sRIO
Gig
E
Optical PMA
X
2
RadioRRH=Remote Radio
HeadSmalleNB
S1 Interface
X2 Interface
Multi-SoC Chaining in eNB Cells
Each T4k is Chainable to other T4ks
Shared Inter-T4k Memory Maps
sRIO based HW Bridges
T4k(s) Share DDR,SRAM,IO,etc.
sRIO Mailbox System For Control
sRIO AXI DMA for Data Transfers
T4k(s) can chain between eNodeBs
Create a eNB optical X2 interface
sRIO or VPN GigE
T4k Distributed Antenna Systems
CPRI5.0 up to 20km
Between BBU and RRH @10GT/s
Optical PMA
Optical PMA
CP
RI
sRIO
T4K DSP+NP
sRIO
Gig
E
CP
RI
sRIO
T4K DSP+NP
sRIO
Gig
E
Optical PMA
Optical PMA
CP
RI
sRIO
T4K DSP+NP
sRIO
Gig
E
RRH
Radio
RRH
Radio
LargeeNB
Mul
ti-P
ort G
igE
Cop
per/
Opt
ical
PH
Y
S1 Interface
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Nasdaq: MSPD
Mobile Data Link Standards Evolution
2GDigital Voice OptimizedCircuit SwitchedData on Voice Structure
3G
3G
Digital Voice OptimizedPacket on Circuit SwitchedEnhanced Data on Voice
4G
4GDigital Data OptimizedPacket SwitchedVoice on Data Structure
Multi-Standard Drives eNB to
Software Defined Radio(SDR) Architecture
For HW Reuse
2008 2009 2010 2011 2012 2013
Notes: Throughput rates are peak theoretical network rates. Radio channel bandwidths indicated.Dates refer to expected initial commercial network deployment except 2008, which shows available technologies that year.
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Nasdaq: MSPD
New modeling approach allows application partitioning and profiling
early on in the design phase
Task Composer Tool
Sys HW
params
List of
Tasks
Task
Dependencies
Rqrd. DSP
Resources
Task
MIPS
Deadline
(latency)
Task
List
Pass/Fail
Indication
Innovation in Multi-Core Programming
However, C is a sequential language, so how do application developers map their
C code into multi -core SoCs?
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Nasdaq: MSPD
Radio to Router
NAS
RRC
PDCP
L1 L1 L1
L2
IP
SCTP
MAC
RLC
NAS
S1-AP
SCTP
L1
L2
IP
RRC
PDCP
MAC
RLC
Relay
S1-AP
UE eNodeB MMELTE-Uu S1-MME
Software Multi-Core HW Mapping: LTE PHY & L2
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Nasdaq: MSPD
Software Multi-Core HW Mapping: LTE PHY
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UL FEC 0
DL FEC 0
Optimized Match
of Instruction and Data
Parallelism
iDFT1iDFT0
RACH0
RACH1
FFT0
UL SIC
IO Move
FFT0
FFT1RACH0
RACH1
UL SIC
iDFT0
iDFT1DL FEC 0
UL FEC 0
PHY TASKS
IO Move
Nasdaq: MSPD
Key Differentiators of the Transcede™ Family
Software configurable for all flavors of LTE, W-CDMA and WiMAX (SDR)
--- Supports China standards, including TD-SCDMA and TD-LTE
Significantly reduces system bill of materials
Integrated L2 and L1 on a single SoC provides lowest possible latency
Simplified programming model allows easy adaptation
Roadmap of scalable SoCs delivers a range of performance/cost points across the range of base stations
THANKYOU!
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