training_learning_maps

8/7/2019 training_learning_maps

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C A

D E N C E

T R A I N I N G

LEARNING MAPS

TABLE OF CONTENTS

•

PCB and Package Design with Allegro Technology• Custom Design with Virtuoso and Assura Technology

• Digital Design and Encounter Technology

• Digital Verification, Languages, and Methodologies with Incisive Technology

Cadence Training Services learning maps provide a comprehensive visual

overview of the learning opportunities for Cadence customers. They providerecommended course flows as well as tool experience and knowledge levels toguide students through a complete learning plan. Learning Maps cover allCadence Technologies and reference courses available worldwide. For exactcourse names, descriptions, and schedules, please refer to each regional coursecatalog on Cadence.com.



Signal Integrity IC PackageDesign

LibraryDevelopment

PCB Design

Allegro

Design Reuse

Allegro Design

Workbench for

Engineers and

Designers

Allegro System

Architect

Allegro AMS

Simulator Adv.Analysis

Orcad Capture

Orcad Capture

CIS

Allegro PCB

Editor Basic

Techniques

Allegro RF PCB

PCB Editor Adv. Techniques

XL

Understanding high

frequency PCB design –

High-speed, RF,

and EMI

Allegro

PCB Power Integrity

Allegro

PCB SI EMControl

Allegro

PCB SI GXL

GXL

C o r e

E x p e r i e n c e d

M a s t e r

A n a l o g F o c

u s

Allegro Package

Designer

SiP Layout Allegro Design

Workbench for

Librarians

Allegro PCB

Librarian

Allegro Design

Workbench for

Administrators

SiP Digital SI

Allegro AMS

Simulator

Analog Simulation

with PSpice

Allegro PCB SI

Foundations

Allegro Design

Entry HDL Front-

to-Back Flow

Logic Design

Allegro

PCB Router Basics

Allegro PCB Editor

SKILL Language

Allegro Design Entry

HDL SKILL Language

Allegro FPGASystem Planner

Allegro PCBEditor IntermediateTechniques

Allegro GREIFP

XL

Allegro High-Speed Constraint Management

SiP RF Architect

Also available as an Internet Learning Series course Denotes Advance with Engineer Explorer classL, XL, GXL Denotes tiers of Cadence products used in course - Not applicable if no legend

Some course titles may vary. Please refer to your regional catalog for exact titles & course datasheets.

EE

EE

EE

EE EE

EE

Learning Map for

PCB and Package Design with Allegro ® Technology

Home

Pspice Advanced

Analysis



C o r e

M a s t e r


Layout Design and Physical VerificationIC CAD Analog, Mixed-Signal and RF Design

Virtuoso Design

Environment

SKILL LanguageProgramming

Virtuoso

Schematic Editor

L, XL

Analog Modeling with

Verilog-A

Behavioral Modeling with

Verilog-AMS or

VHDL-AMS

Virtuoso AMS Designer

Virtuoso

Floorplanner

Virtuoso

Chip Assembly Router

SKILL Programmingfor IC Layout Design

Advanced SKILL

Language Programming

SKILL Development of

Parameterized CellsVirtuoso

Connectivity-Driven

Layout

XL, GXLVirtuoso Analog

Simulation Techniques

XL, GXLVirtuoso UltraSim

Full-Chip Simulator

Virtuoso LayoutDesign Basics

L

Simulation and Analysis

Using OCEAN

Using Virtuoso

Spectre Circuit

Simulator Effectively

Virtuoso Space-based

Router

GXL

Assura PhysicalVerification (DRC/LVS)

Cadence QRC User

Transistor-level

Extraction

Assura Rules-Writer

RF Analysiswith Virtuoso Spectre

Circuit Simulator

XL, GXL Virtuoso DigitalImplementation

GXL

L, XL

Virtuoso LayoutMigrate

Virtuoso Design

Environment Setup

Also available as an Internet Learning Series course Denotes Advance with Engineer Explorer class

L, XL, GXL Denotes tiers of Cadence products used in course - Not applicable if no legend


Learning Map for

Custom Design with Virtuoso ® and Assura ® Technology

EE EE

EE

EE

EE

Home

EE

Virtuoso SpectreCircuit Simulator

LVirtuoso AnalogDesign Environment

L

EE

Mask Compose

Automated Reticle

Design Synthesis

Cadence QRC

Techgen Developer



C o r e

M a s t e r

Signoff and Analysis Design VerificationLogic Design Place-and-Route

Basic Static Timing

Analysis

Encounter RTL

Compiler

XL Signoff Timing Analysis

with Encounter Timing

System

Cadence QRC User

Cell-Level Extraction

Encounter

Conformal

Constraint Designer

XL

Advanced Logic

Equivalence Checking with

Encounter Conformal EC

XL

Encounter ConformalLow-Power Verification

XL

Custom Equivalence

Checking with Encounter

Conformal EC

GXL

Low-Power

Synthesis with Encounter RTL Compiler

Test Synthesis

Using Encounter RTL

Compiler

XL

Advanced

Synthesis with Encounter

RTL Compiler

GXL

Logic Equivalence

Checking with Encounter

Conformal EC

XL

Floorplanning,

Physical Synthesis,

Place and Route (Flat)

XL

Floorplanning,

Physical Synthesis, Place

and Route (Hierarchical)

XL

Advanced

Signoff Power-Grid

Analysis with Encounter Power System

Signoff

Power-Grid Analysis with

Encounter Power System

XL

XL

GXL

Encounter

Conformal ECO

XL

XL

Extended Checking with

Encounter Conformal EC

L


Home

Learning Map for

Digital Design with Encounter ® Technology

EE

Low-Power

Implementation

XL EE

EE

XL EE

EE EE






C o r e

M a s t e r


System C/C++Design & Verification

Incisive

SystemC, VHDL,

and Verilog

Simulation

XLVerilog

Language and

Application

LVHDL for

Verilog users

L

SystemVerilog

Advanced Verification

Using OVM/UVM

XL

Verilog for

VHDL users

L

Verification

with VHDL

L

Designing

with VHDL

L

Continued

Learning Map for

Digital Verification, Languages, and Methodologies with Incisive ® Technology

Incisive

Simulation of PSL

Assertions

SystemVerilog

for Design and

Verification

SystemC Synthesis

Using C to SiliconCompiler

SystemVerilog

Assertions

SystemC Verification

(SCV)

SystemC Transaction

Level Modeling

VHDL

Language and

Application

L C++ Language

Verification

with PSL

Formal Analysis

Fundamentals

with IFV

XL

Formal

Analysis Advanced

with IFV

XL

SystemC

Fundamentals

XL




XL

XL XL

EE EE

EE

EE EE

EE

Home



C o r e

M a s t e r


Metric-driven VerificationVerification Scripting

Verification

Planning Using

Enterprise Planner

XLSpecman

Elite Advanced

Verification

SpecmanEliteBasics for Environment

Users

XL

SpecmanElite

Basics for EnvironmentDevelopers

XL

Incisive

Comprehensive

Coverage

Incisive SystemC,VHDL, and Verilog

Simulation

XL

Perl for EDA

Engineering

Tcl Scripting for EDA +

Intro to Tk




Learning Map for

Digital Verification, Languages, and Methodologies with Incisive ® Technology

XL EE

XL EE

EE

Home

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