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October 4, 2016 Santa Clara Convention Center Mission City Ballroom Silicon Photonics for the New Internet Francesco Brianti
27

Track 3 session 7 - st dev con 2016 - silicon photonics

Apr 16, 2017

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Page 1: Track 3   session 7 - st dev con 2016 - silicon photonics

October 4, 2016

Santa Clara Convention Center

Mission City Ballroom

Silicon Photonics

for the New Internet

Francesco Brianti

Page 2: Track 3   session 7 - st dev con 2016 - silicon photonics

How ST Plays in the New Internet

Page 3: Track 3   session 7 - st dev con 2016 - silicon photonics

The New Internet 3

Smart Driving

• Advanced safety

• Assisted driving

• Infotainment

• Traffic monitoring

Smart Home and City

• Home and building automation

• Urban monitoring and control system

• Smart metering and distribution

• Heating and energy control

• Smart LED lighting

• Security and surveillance

Smart Industry

• Enterprise gateways and routers

• Networked devices

• Human-machine interface

• Machine-to-Machine communication

• Connected farms

Smart Things

• Connected wearable devices

• Virtual Reality

• Gaming

• Tele-health

• Drones

Data center

Cloud computing

Networking

Page 4: Track 3   session 7 - st dev con 2016 - silicon photonics

Where You “See” ST 4

Making driving safer, greener

and more connected

Enabling cities to make more of

available resources

Enabling the evolution of industry

towards smarter, safer and more

efficient factories and workplaces

Making homes smarter, for

better living, higher security,

and less waste

Making everyday things

smarter, connected and

more aware of their

surroundings

Page 5: Track 3   session 7 - st dev con 2016 - silicon photonics

But ST is also Here 5

Making driving safer, greener

and more connected

Enabling cities to make more of

available resources

Enabling the evolution of industry

towards smarter, safer and more

efficient factories and workplaces

Making homes smarter, for

better living, higher security,

and less waste

Making everyday things

smarter, connected and

more aware of their

surroundings

Page 6: Track 3   session 7 - st dev con 2016 - silicon photonics

First phase of the Internet

Expanding the Network

Page 7: Track 3   session 7 - st dev con 2016 - silicon photonics

Evolution of the Internet 7

Source: DARPA

1969

Page 8: Track 3   session 7 - st dev con 2016 - silicon photonics

Evolution of the Internet 8

Source: Brian Reid

1993

Page 9: Track 3   session 7 - st dev con 2016 - silicon photonics

Second phase of the Internet

Rewiring the Data Center

Page 10: Track 3   session 7 - st dev con 2016 - silicon photonics

Bits “Travel” Within The Data Center 10

Within Data Center (73.1%)

Storage, production and

development data, authentication

Data Center to Data Center (8.7%)

Replication, CDN, inter-cloud links

Data Center to User (18.2%)

Web, e-mail, VoD, …

Within Data Center

(75.4%)

Global Data Center traffic by destination

Source: Cisco Global Cloud index, 2014

2014

Page 11: Track 3   session 7 - st dev con 2016 - silicon photonics

… Demanding a New DC Topology 11

Traditional Three-Tier architecture• Hierarchical tree

• Most traffic leaves and enter datacenter

• Limited scalability

CORE

AGGREGATION

ACCESS

Designed for North – South traffic

Spine / Leaf architecture• Uniform switching Fabric

• Most traffic stays within data center

• Scalable architecture

SPINE

LEAF

Designed for East – West traffic

CORE

1~20m

0.1~2km

2km~metro

40G 100G 200G/400G

Page 12: Track 3   session 7 - st dev con 2016 - silicon photonics

…Increasing the Number of Ports 12

$0

$2

$4

$6

$8

$10

$12

0

2

4

6

8

10

12

14

2014 2015 2016 2017 2018 2019

Tho

usands

Mill

ion

s Average Selling Price

per Port (line)

100GbE Port

Shipments (Bars)

Source: CREHAN Research Inc.

Page 13: Track 3   session 7 - st dev con 2016 - silicon photonics

… Requiring Economy of Scale 13

Cost (CAPEX +OPEX)

Functionality [and Time](Range / accuracy / speed / size)

Discrete

Hybrid

Monolithic

Integrated 3D Optical Engine

Page 14: Track 3   session 7 - st dev con 2016 - silicon photonics

How ST Silicon Photonics can help

Page 15: Track 3   session 7 - st dev con 2016 - silicon photonics

Silicon Photonics

• Photonics

• Photonics is the technology associated with signal

generation, processing, transmission and detection

where the signal is carried by photons (i.e. light)

• Silicon Photonics

• Photonic devices produced within standard

silicon factory and with standard silicon processing

15

Page 16: Track 3   session 7 - st dev con 2016 - silicon photonics

Bringing SiPho to Reality

• Produce in a high volume silicon wafer fab

• Repeatability and uniformity

• Standard design flow and volume production

• Make photonics design [very] similar to CMOS ICs design

• Have a library of available elementary devices allowing to manipulate the light in the same way

as electrical signals

• Have a standard automated design flow

• Manage supply chain from wafers to final product (the 3D optical engine)

• On-wafer testing for electrical and optical functionalities

• Volume production ensuring required quality standard

16

Page 17: Track 3   session 7 - st dev con 2016 - silicon photonics

300mm Photonics

Tool Set Portfolio

300mm PHOTONICS

Technological Platform

Wafer Supply Strategy 17

Etch

SiGe & Ge epitaxies

193 nm Litho

Low T° DepNi,Co,Pt silicide

193 i

Existing Tools

• High volume

• Sub-90nm CMOS node tools

• 193nm/193i photolithography

• Improved process control versus 200mm

Page 18: Track 3   session 7 - st dev con 2016 - silicon photonics

Electro Optical Wafer Sort

Integrated 3D Optical Engine

Schematic Capture

CAD simulation

Optical Die

Chip on Wafer Bonding

Crolles 200 and 300mm Wafer Fab

From Development to Prototype 18

Page 19: Track 3   session 7 - st dev con 2016 - silicon photonics

Photonics Design Strategy 19

Brings dramatic increase in processing speed and significant power consumption reduction

Waveguide & optical splitter

Grating couplers Germanium PIN PD

High Speed

Phase Modulator

Page 20: Track 3   session 7 - st dev con 2016 - silicon photonics

Integration Strategy 20

Electronic IC= CMOS or BiCMOSCu-pillar

Independent evolution for optimal technology platform

(process flow & design environment)

Opto-Electronic

System

Photonic IC

Ni-pillar

3D

Integration

ElectronicIC

PhotonicIC

F2F Cu-pillar process, 40µm pitch

7m

m

11 mm

Opto-Electronic System = Photonic IC + Electronic IC

F2F Cu-pillar process, 40µm pitch

Page 21: Track 3   session 7 - st dev con 2016 - silicon photonics

Testing StrategyEIC PIC

EIC

PICOEWS

21

Optical Test

Optical fiber array head connected to laser instruments

Tunable CW laser source(s), driven by ATE test program during test execution

Power meters, triggered by ATE test program during test execution

Dynamic die alignment (x-y-z) through optical loop and proximity sensor

Optical tests integrated in the test program (EO std datalog output)

Electric Test

Cantilever “Half-Moon” probecard

Standard DC + Digital testing capability, without limitations vs EWS

Standard probing operation, including wafer mapping, load/unload, OCR,

networking etc.

Special anti-vibration environment (modified ATE and specific prober solution)

Page 22: Track 3   session 7 - st dev con 2016 - silicon photonics

STsP10028Ready for 100G PSM4 - QSFP28

22

3D Silicon

Photonics

STSP10028

1.3um CW

Laser or Lamp

testing assembly shown for simplicity

Fiber Attach

ElectronicIC

PhotonicIC

F2F Cu-pillar process, 40µm pitch

7m

m

11 mm

Compliant to 100G PSM4 QSFP28 MSA specifications

Page 23: Track 3   session 7 - st dev con 2016 - silicon photonics

Preparing for the Future

Page 24: Track 3   session 7 - st dev con 2016 - silicon photonics

Pervasion of Optics 24

Chip-to-Chip1 to 50 cm

Board-to-Board50 to 100 cm

Rack-to-Rack1 to 100 m

Metro and long-haul0.1 to 80 km

Volumes

Distance

Optical Copper

Bandwidth x Length

favors optical

Historical cross over: 100Gb/s*m

Page 25: Track 3   session 7 - st dev con 2016 - silicon photonics

Facilitated by SiPho 25

Silicon Photonics

Interposer with TSV

ASIC EIC

Optical Interposer with TSV and

Photonic Control IP embedded into ASIC

SiPho IC

SiPho Interposer

Optical Coupling

Classical Interposer

ASICOIC

EIC

3D Silicon Photonics integrated on

Classic Interposer

Optical

Coupling

OIC

EIC

3D Silicon low cost

Package and IO coupling

OIC

EIC

SiPho 3D Chipset

3D Silicon

standalone

Page 26: Track 3   session 7 - st dev con 2016 - silicon photonics

SiPho Turning the Corner

• Silicon Photonics technology is today an Industrial reality

• Usage of Silicon Photonics ST 3D Optical Engine in 100G QSP28 applications shows an

outstanding BOM reduction and assembly ease

• Silicon Photonics provides a sustainable, scalable, and viable path towards

On Board Optics for next generation networking equipment and infrastructure

There is nothing more powerful than an idea whose time has come – V. Hugo

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Page 27: Track 3   session 7 - st dev con 2016 - silicon photonics

Thank You