tps54361-q1

SW

VIN

GND

BOOT

FB

COMP

EN

RT/CLK

VI

VO

TPS54361-Q1

SS/TR

PWRGD

Output Current (A)

Effi

cien

cy (

%)

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65

70

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95

100

D029

VO = 12 V, gs = 630 kHzVO = 5 V and 3.3 V, gs = 400 kHz

36 V to 12 V12 V to 5 V12 V to 3.3 V

Product

Folder

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Documents

Tools &

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TPS54361-Q1SLVSCC4A –APRIL 2014–REVISED APRIL 2014

TPS54361-Q1 4.5-V to 60-V Input, 3.5-A, Step Down DC-DC Converter with Soft-Startand Eco-mode™

1 Features 3 DescriptionThe TPS54361-Q1 device is a 60-V, 3.5-A, step

1• Qualified for Automotive Applicationsdown regulator with an integrated high side MOSFET.• AEC-Q100 Qualified With the Following Results: The device survives load dump pulses up to 65 V per

– Device Temperature Grade 1: –40°C to 125°C ISO 7637. Current mode control provides simpleAmbient Operating Temperature Range external compensation and flexible component

selection. A low ripple pulse skip mode and supply– Device HBM ESD Classification Level H1Ccurrent of 152-µA enables high efficiency at light– Device CDM ESD Classification Level C3B loads. Shutdown supply current is reduced to 2 μA

• High Efficiency at Light Loads with Pulse Skipping when the enable pin is pulled low.Eco-mode™ Undervoltage lockout is internally set at 4.3 V but can

• 87-mΩ High-Side MOSFET increase using an external resistor divider at theenable pin. The output voltage startup ramp is• 152-μA Operating Quiescent Current andcontrolled by the soft start pin that can also be2-μA Shutdown Currentconfigured for sequencing/tracking. An open-drain• 100-kHz to 2.5-MHz Adjustable Switchingpower-good signal indicates the output is within 93%Frequency to 106% of the nominal voltage.

• Synchronizes to External ClockA wide adjustable switching-frequency range allows• Low Dropout at Light Loads with Integrated BOOT for optimization of either efficiency or external

Recharge FET component size. Cycle-by-cycle current-limit,• Adjustable UVLO Voltage and Hysteresis frequency foldback and thermal shutdown protects

internal and external components during an overload• UV and OV Power Good Outputcondition.• Adjustable Soft-Start and SequencingThe TPS54361-Q1 device is available in a 10-pin 4• 0.8-V 1% Internal Voltage Referencemm × 4 mm SON PowerPAD™ package.• 10-Pin SON with PowerPAD™ Package

• –40°C to 150°C TJ Operating Range Device Information(1)

• Supported by WEBENCH™ Software Tool DEVICE NAME PACKAGE BODY SIZETPS54361-Q1 SON (10) 4.00 mm × 4.00 mm

2 Applications(1) For all available packages, see the orderable addendum at

the end of the data sheet.• Vehicle Accessories: GPS (see SLVA412),Entertainment

• USB Dedicated Charging Ports and BatteryChargers (see SLVA464)

• 12-V, 24-V and 48-V Industrial, Automotive andCommunications Power Systems

4 Simplified Schematic

Efficiency vs Load Current

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

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TPS54361-Q1SLVSCC4A –APRIL 2014–REVISED APRIL 2014 www.ti.com

Table of Contents8.2 Functional Block Diagram ....................................... 131 Features .................................................................. 18.3 Feature Description................................................. 132 Applications ........................................................... 18.4 Device Functional Modes........................................ 273 Description ............................................................. 1

9 Application and Implementation ........................ 294 Simplified Schematic............................................. 19.1 Application Information............................................ 295 Revision History..................................................... 29.2 Typical Application .................................................. 296 Pin Configuration and Functions ......................... 3

10 Power Supply Recommendation ....................... 397 Specifications......................................................... 411 Layout................................................................... 397.1 Absolute Maximum Ratings ..................................... 4

11.1 Layout Guidelines ................................................. 397.2 Handling Ratings....................................................... 411.2 Layout Example .................................................... 417.3 Recommended Operating Conditions....................... 4

12 Device and Documentation Support ................. 427.4 Thermal Information .................................................. 412.1 Device Support...................................................... 427.5 Electrical Characteristics........................................... 512.2 Documentation Support ........................................ 427.6 Timing Requirements ................................................ 612.3 Trademarks ........................................................... 427.7 Switching Characteristics .......................................... 612.4 Electrostatic Discharge Caution............................ 427.8 Typical Characteristics .............................................. 712.5 Glossary ................................................................ 428 Detailed Description ............................................ 12

13 Mechanical, Packaging, and Orderable8.1 Overview ................................................................. 12Information ........................................................... 42

5 Revision History

Changes from Original (April 2014) to Revision A Page

• Changed device status from Product Preview to Production Data ....................................................................................... 1

2 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated

Product Folder Links: TPS54361-Q1


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BOOT

VIN

EN

SS/TR

RT/CLK

PWRGD

SW

GND

COMP

FB

10

9

1

2

3

4

5

8

7

6

TPS54361-Q1www.ti.com SLVSCC4A –APRIL 2014–REVISED APRIL 2014

6 Pin Configuration and Functions

10-Pin SON With PowerPADDPR Package

(Top View)

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

A bootstrap capacitor is required between BOOT and SW. If the voltage on this capacitor is below theBOOT 1 O minimum required to operate the high-side MOSFET, the gate drive is switched off until the capacitor is

refreshed.This pin is the error amplifier output and input to the output switch current (PWM) comparator. ConnectCOMP 7 O frequency compensation components to this pin.This pin is the enable pin, with an internal pullup current source. Pull EN below 1.2 V to disable. Float EN

EN 3 I to enable. Adjust the input undervoltage lockout with two resistors. See the Enable and AdjustUndervoltage Lockout section.

FB 6 I This pin is the Inverting input of the transconductance (gm) error amplifier.GND 8 – GroundVIN 2 I This pin is the input supply voltage with 4.5-V to 60-V operating range.

The PWRGD pin is an open drain output that asserts low if the output voltage is out of regulation becausePWRGD 10 O of thermal shutdown, dropout, over-voltage, or EN shut down.This pin is the resistor timing and external clock pin. An internal amplifier holds this pin at a fixed voltagewhen using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL

RT/CLK 5 I upper threshold, a mode change occurs and the pin becomes a synchronization input. The internalamplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop,the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.This pin is the soft-start and tracking pin. An external capacitor connected to this pin sets the output rise

SS/TR 4 I time. Because the voltage on this pin overrides the internal reference, SS/TR can be used for tracking andsequencing.

SW 9 O The SW pin is the source of the internal high-side power MOSFET and switching node of the converter.The GND pin must be electrically connected to the exposed pad on the printed circuit board for properThermal Pad – operation.

Copyright © 2014, Texas Instruments Incorporated Submit Documentation Feedback 3



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7 Specifications

7.1 Absolute Maximum Ratings (1)

over operating free-air temperature range (unless otherwise noted)MIN MAX UNIT

VIN –0.3 65EN –0.3 8.4BOOT 73FB –0.3 3

Input voltage VCOMP –0.3 3PWRGD –0.3 6SS/TR –0.3 3RT/CLK –0.3 3.6BOOT-SW 8

Output voltage SW –0.6 65 VSW, 10-ns Transient –2 65

Operating junction temperature –40 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range –65 150 °CHuman body model (HBM), per AEC Q100-002 (1) –2 2 kV

Corner pins (1, 5,V(ESD) Electrostatic discharge –750 7506, and 10)Charged device model (CDM), per AEC-Q100-011 VOther pins –500 500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN MAX UNITV(VIN) Supply input voltage 4.5 60 VVO Output voltage 0.8 58.8 VIO Output current 0 3.5 ATJ Junction Temperature –40 150 °C

7.4 Thermal InformationDPR

THERMAL METRIC (1) (2) UNIT(10 PINS)

RθJA Junction-to-ambient thermal resistance (standard board) 35.1ψJT Junction-to-top characterization parameter 0.3ψJB Junction-to-board characterization parameter 12.5

°C/WRθJCtop Junction-to-case(top) thermal resistance 34.1RθJCbot Junction-to-case(bottom) thermal resistance 2.2RθJB Junction-to-board thermal resistance 12.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.(2) Power rating at a specific ambient temperature TA must be determined with a junction temperature of 150°C. This is the point where

distortion starts to substantially increase. See the power dissipation estimate in the Power Dissipation Estimate section of this data sheetfor more information.




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7.5 Electrical CharacteristicsTJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

Operating input voltage 4.5 60 V

Internal undervoltage lockout threshold Rising 4.1 4.3 4.48 V

Internal undervoltage lockout threshold 325 mVhysteresis

Shutdown supply current V(EN) = 0 V, 25°C, 4.5 V ≤ V(VIN) ≤ 60 V 2.25 4.5μAOperating: nonswitching supply V(FB) = 0.9 V, TA = 25°C 152 200current

ENABLE AND UVLO (EN PIN)

V(EN)th Enable threshold voltage No voltage hysteresis, rising and falling 1.1 1.2 1.3 V

Enable threshold 50 mV –4.6II Input current μA

Enable threshold –50 mV –0.58 –1.2 -1.8

Ihys Hysteresis current –2.2 –3.4 -4.5 μA

VOLTAGE REFERENCE

Voltage reference 0.792 0.8 0.808 V

HIGH-SIDE MOSFET

On-resistance V(VIN) = 12 V, V(BOOT-SW) = 6 V 87 185 mΩ

ERROR AMPLIFIER

Input current 50 nA

Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 350 μMhos

Error amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V, V(FB) = 0.4 V 77 μMhosduring soft-start

Error amplifier dc gain V(FB) = 0.8 V 10 000 V/V

Min unity gain bandwidth 2500 kHz

Error amplifier source/sink V(COMP) = 1 V, 100-mV overdrive ±30 μA

COMP to SW current 12 A/Vtransconductance

CURRENT-LIMIT

All VIN and temperatures, open loop (1) 4.5 5.5 6.8

Current-limit threshold All temperatures, V(VIN) = 12 V, open loop (1) 4.5 5.5 6.3 A

V(VIN) = 12 V, TA = 25°C, open loop (1) 5.2 5.5 5.9

THERMAL SHUTDOWN

Thermal shutdown 176 °C

Thermal shutdown hysteresis 12 °C

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

RT/CLK high threshold 1.55 2 V

RT/CLK low threshold 0.5 1.2 V

SOFT START AND TRACKING (SS/TR PIN)

ISS Charge current V(SS/TR) = 0.4 V 1.7 µA

VSS(ofs) SS/TR-to-FB matching V(SS/TR) = 0.4 V 42 mV

SS/TR-to-reference crossover 98% nominal 1.16 V

SS/TR discharge current (overload) V(FB) = 0 V, V(SS/TR) = 0.4 V 354 µA

SS/TR discharge voltage V(FB) = 0 V 54 mV

POWER GOOD (PWRGD PIN)

FB threshold for PWRGD low FB falling 90%

FB threshold for PWRGD high FB rising 93%

FB threshold for PWRGD low FB rising 108%

FB threshold for PWRGD high FB falling 106%

Hysteresis FB falling 2.5%

Output high leakage V(PWRGD) = 5.5 V, TA = 25°C 10 nA

On resistance I(PWRGD) = 3 mA, V(FB) < 0.79 V 45 Ω

(1) Open Loop current limit measured directly at the SW pin and is independent of the inductor value and slope compensation.




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Electrical Characteristics (continued)TJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 µA 0.9 2 V

7.6 Timing RequirementsMIN TYP MAX UNIT

RT/CLKMinimum CLK input pulse width 15 ns

7.7 Switching CharacteristicsTJ = –40°C to 150°C, V(VIN) = 4.5 V to 60 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITENABLE AND UVLO (EN PIN)

Enable to COMP active V(VIN) = 12 V, TA = 25°C 540 µsCURRENT-LIMIT

Current limit threshold delay 60 nsSWton V(VIN) = 23.7 V, VO = 5 V, IO = 3.5 A, 100 nsMinimum on time R(RT) = 39.6 kΩ, TA = 25°CRT/CLK

Switching frequency range using RT mode 100 2500 kHzƒS Switching frequency R(RT) = 200 kΩ 450 500 550 kHz

Switching frequency range using CLK 160 2300 kHzmodeTIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)

RT/CLK falling edge to SW rising edge Measured at 500 kHz with an RT 55 nsdelay resistor (R(RT)) in seriesPLL lock in time Measured at 500 kHz 78 μs




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Resistance at RT/CLK (k:)

Sw

itc

hin

g F

req

ue

nc

y (

kH

z)

200 300 400 500 600 700 800 900 1000

100

150

200

250

300

350

400

450

500

D024

Junction Temperature (qC)

Sw

itc

hin

g F

req

ue

nc

y (

kH

z)

-50 -25 0 25 50 75 100 125 150

450

460

470

480

490

500

510

520

530

540

550

D025


Hig

h-S

ide

Sw

itc

h C

urr

en

t (A

)

-50 -25 0 25 50 75 100 125 150

4.5

4.7

4.9

5.1

5.3

5.5

5.7

5.9

6.1

6.3

6.5

D027Input Voltage (V)

Hig

h-S

ide

Sw

itc

h C

urr

en

t (A

)

0 10 20 30 40 50 60

4.5

4.7

4.9

5.1

5.3

5.5

5.7

5.9

6.1

6.3

6.5

D026

-40q

25q

150q


Sta

tic

Dra

in-S

ou

rce

On

-Sta

te R

es

ista

nc

e (:

)

-50 -25 0 25 50 75 100 125 150

0

0.05

0.1

0.15

0.2

0.25

D004

BOOT-SW = 3 V

BOOT-SW = 6 V


Vo

lta

ge

Re

fere

nc

e (

V)

-50 -25 0 25 50 75 100 125 150

0.784

0.789

0.794

0.799

0.804

0.809

0.814

D028


7.8 Typical Characteristics

V(VIN) = 12 V

Figure 1. On Resistance vs Junction Temperature Figure 2. Voltage Reference vs Junction Temperature

V(VIN) = 12 V

Figure 3. Switch Current-Limit vs Junction Temperature Figure 4. Switch Current-Limit vs Input Voltage

V(VIN) = 12 V R(RT) = 200 kΩ

Figure 5. Switching Frequency vs Junction Temperature Figure 6. Switching Frequency vs RT/CLK ResistanceLow Frequency Range




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Inp

ut

Cu

rre

nt

at

EN

(P

A)

-50 -25 0 25 50 75 100 125 150

-5.5

-5.3

-5.1

-4.9

-4.7

-4.5

-4.3

-4.1

-3.9

-3.7

-3.5

D019Junction Temperature (qC)

Inp

ut

Cu

rre

nt

at

EN

(P

A)

-50 -25 0 25 50 75 100 125 150

-2.5

-2.3

-2.1

-1.9

-1.7

-1.5

-1.3

-1.1

-0.9

-0.7

-0.5

D018


Tra

ns

co

nd

uc

tan

ce

(P

A/V

)

-50 -25 0 25 50 75 100 125 150

20

30

40

50

60

70

80

90

100

110

120


EN

Th

res

ho

ld (

V)

-50 -25 0 25 50 75 100 125 150

1.15

1.18

1.21

1.24

1.27

1.3

1.33

D020

Resistance at RT/CLK (k:)

Sw

itc

hin

g F

req

ue

nc

y (

kH

z)

0 50 100 150 200

0

500

1000

1500

2000

2500


Tra

ns

co

nd

uc

tan

ce

(P

A/V

)

-50 -25 0 25 50 75 100 125 150

200

250

300

350

400

450

500

D022


Typical Characteristics (continued)

V(VIN) = 12 V

Figure 7. Switching Frequency vs RT/CLK Resistance Figure 8. EA Transconductance vs Junction TemperatureHigh Frequency Range

V(VIN) = 12 V V(VIN) = 12 V

Figure 9. EA Transconductance During Soft-Start vs Figure 10. EN Pin Voltage vs Junction TemperatureJunction Temperature

V(VIN) = 12 V V(EN) = Threshold + 50 mV V(VIN) = 12 V V(EN) = Threshold – 50 mV

Figure 11. EN Pin Current vs Junction Temperature Figure 12. EN Pin Current vs Junction Temperature




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Su

pp

ly C

urr

en

t a

t V

IN (P

A)

-50 -25 0 25 50 75 100 125 150

70

90

110

130

150

170

190

210


Su

pp

ly C

urr

en

t a

t V

IN (P

A)

0 10 20 30 40 50 60

70

90

110

130

150

170

190

210

D012


Su

pp

ly C

urr

en

t a

t V

IN (P

A)

-50 -25 0 25 50 75 100 125 150

0

0.5

1

1.5

2

2.5

3


Su

pp

ly C

urr

en

t a

t V

IN (P

A)

0 10 20 30 40 50 60

0

0.5

1

1.5

2

2.5

3

D014


I (E

N)

Hy

ste

res

is (P

A)

-50 -25 0 25 50 75 100 125 150

-4.5

-4.3

-4.1

-3.9

-3.7

-3.5

-3.3

-3.1

-2.9

-2.7

-2.5

D017Voltage at FB (V)

No

min

al

Sw

itc

hin

g F

req

ue

nc

y (

%)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

0

25

50

75

100

D016

V (FB) Falling

V (FB) Rising



V(VIN) = 12 V

Figure 13. EN Pin Current Hysteresis vs Junction Figure 14. Switching Frequency vs FBTemperature

V(VIN) = 12 V TJ = 25 °C

Figure 15. Shutdown Supply Current vs Junction Figure 16. Shutdown Supply Current vs Input VoltageTemperature

V(VIN) = 12 V TJ = 25°C

Figure 17. I(VIN) Supply Current vs Junction Temperature Figure 18. I(VIN) Supply Current vs Input Voltage




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SS/TR (mV)

Off

se

t (m

V)

0 100 200 300 400 500 600 700 800

0

100

200

300

400

500

600

700

800

900


SS

/TR

to

FB

Off

se

t (m

V)

-50 -25 0 25 50 75 100 125 150

20

25

30

35

40

45

50

55

60

D006


Po

we

r-G

oo

d R

es

ista

nc

e (:

)

-50 -25 0 25 50 75 100 125 150

0

10

20

30

40

50

60

70

80


Po

we

r-G

oo

d T

hre

sh

old

(%

)

-50 -25 0 25 50 75 100 125 150

88

90

92

94

96

98

100

102

104

106

108

110

D008

FB

FB Falling

FB Rising

FB Falling


Inp

ut

Vo

lta

ge

at

BO

OT

-PH

(V

)

-50 -25 0 25 50 75 100 125 150

1.8

1.9

2

2.1

2.2

2.3

2.4

2.5

2.6

D011

BOOT-PH UVLO Falling

BOOT-PH UVLO Rising


Inp

ut

Vo

lta

ge

(V

)

-50 -25 0 25 50 75 100 125 150

3.7

3.8

3.9

4

4.1

4.2

4.3

4.4

4.5

D010

UVLO Start Switching

UVLO Stop Switching



Figure 19. BOOT-SW UVLO vs Junction Temperature Figure 20. Input Voltage UVLO vs Junction Temperature

V(VIN) = 12 V V(VIN) = 12 V

Figure 21. PWRGD On Resistance vs Junction Temperature Figure 22. PWRGD Threshold vs Junction Temperature

V(VIN) = 12 V 25°C V(VIN) = 12 V V(FB) = 0.4 V

Figure 23. SS/TR to FB Offset vs FB Figure 24. SS/TR to FB Offset vs Temperature




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Output Current (A)

Inp

ut

Vo

lta

ge

(V)

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

4.6

4.7

4.8

4.9

5

5.1

5.2

5.3

5.4

5.5

5.6

D005

Start

Stop

DropoutVoltage

DropoutVoltage



Figure 25. 5-V Start and Stop Voltage (see Low Dropout Operation and Bootstrap Voltage (BOOT))




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8 Detailed Description

8.1 OverviewThe TPS54361-Q1 device is a 60-V, 3.5-A, step-down (buck) regulator with an integrated high-side n-channelMOSFET. The device implements constant-frequency current-mode control which reduces output capacitanceand simplifies external frequency compensation. The wide switching frequency range of 100 kHz to 2500 kHzallows either efficiency or size optimization when selecting the output filter components. The switching frequencyis adjusted using a resistor to ground connected to the RT/CLK pin. The device has an internal phase-lockedloop (PLL) connected to the RT/CLK pin that synchronizes the power switch turn-on to a falling edge of anexternal clock signal.

The TPS54361-Q1 device has a default input start-up voltage of 4.3 V typical. The EN pin adjusts the inputvoltage undervoltage lockout (UVLO) threshold with two external resistors. An internal pullup current sourceenables operation when the EN pin is floating. The operating current is 152 μA under no load condition when notswitching. When the device is disabled, the supply current is 2 μA.

The integrated 87-mΩ high-side MOSFET supports high-efficiency power-supply designs capable of delivering3.5 A of continuous current to a load. The gate-drive bias voltage for the integrated high-side MOSFET issupplied by a bootstrap capacitor connected from the BOOT to SW pins. The TPS54361-Q1 device reduces theexternal component count by integrating the bootstrap recharge diode. The BOOT pin capacitor voltage ismonitored by a UVLO circuit which turns off the high-side MOSFET when the BOOT to SW voltage falls below apreset threshold. An automatic BOOT capacitor recharge circuit allows the TPS54361-Q1 device to operate athigh duty cycles approaching 100%. Therefore, the maximum output voltage is near the minimum input supplyvoltage of the application. The minimum output voltage is the internal 0.8 V feedback reference.

Output overvoltage transients are minimized by an Overvoltage Protection (OVP) comparator. When the OVPcomparator is activated, the high-side MOSFET is turned off and remains off until the output voltage is less than106% of the desired output voltage.

The SS/TR (soft-start/tracking) pin is used to minimize inrush currents or provide power supply sequencingduring power up. A small value capacitor must be connected to the pin to adjust the soft-start time. A resistordivider can be connected to the pin for critical power supply sequencing requirements. The SS/TR pin isdischarged before the output powers up. This discharging ensures a repeatable restart after an over-temperaturefault, UVLO fault or a disabled condition. When the overload condition is removed, the soft-start circuit controlsthe recovery from the fault output level to the nominal regulation voltage. A frequency foldback circuit reduces theswitching frequency during start up and overcurrent fault conditions to help maintain control of the inductorcurrent.




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ErrorAmplifier

Boot Charge

Boot UVLO

UVLO

Current Sense

Oscillator with PLL

FrequencyFoldback

Logic

Slope Compensation

PWMComparator

Minimum ClampPulse Skip

Maximum Clamp

VoltageReference

Overload Recovery

FB

COMP

RT/ CLK

SW

BOOT

VIN

GND

Thermal Shutdown

EN

EnableComparator

ShutdownLogic

Shutdown

EnableThreshold

6

10/9/2013 A0272435

Logic

Shutdown

POWERPAD

Shutdown

UV

SS/TR

PWRGD

OV


8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Fixed-Frequency PWM ControlThe TPS54361-Q1 device uses fixed-frequency peak current-mode control with adjustable switching frequency.The output voltage is compared through external resistors connected to the FB pin to an internal voltagereference by an error amplifier. An internal oscillator initiates the turn on of the high-side power switch. The erroramplifier output at the COMP pin controls the high-side power-switch current. When the high-side MOSFETswitch current reaches the threshold level set by the COMP voltage, the power switch is turned off. The COMPpin voltage increases and decreases as the output current increases and decreases. The device implementscurrent-limiting by clamping the COMP pin voltage to a maximum level. The pulse skipping Eco-mode isimplemented with a minimum voltage clamp on the COMP pin.

8.3.2 Slope Compensation Output CurrentThe TPS54361-Q1 device adds a compensating ramp to the MOSFET switch-current sense signal. This slopecompensation prevents sub-harmonic oscillations at duty cycles greater than 50%. The peak current-limit of thehigh-side switch is not affected by the slope compensation and remains constant over the full duty-cycle range.




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Feature Description (continued)8.3.3 Pulse-Skip Eco-modeThe TPS54361-Q1 device operates in a pulse-skipping Eco-mode at light load currents to improve efficiency byreducing switching and gate drive losses. The device enters Eco-mode if the output voltage is within regulationand the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold. Thepulse-skipping current threshold is the peak switch-current level corresponding to a nominal COMP voltage of600 mV.

When in Eco-mode, the COMP pin voltage is clamped at 600 mV and the high-side MOSFET is inhibited.Because the device is not switching, the output voltage begins to decay. The voltage control-loop responds tothe falling output voltage by increasing the COMP pin voltage. The high-side MOSFET is enabled and switchingresumes when the error amplifier lifts COMP above the pulse skipping threshold. The output voltage recovers tothe regulated value, and COMP eventually falls below the Eco-mode pulse-skipping threshold at which time thedevice again enters Eco-mode. The internal PLL remains operational when in Eco-mode. When operating at lightload currents in Eco-mode, the switching transitions occur synchronously with the external clock signal.

During Eco-mode operation, the TPS54361-Q1 device senses and controls the peak switch current and not theaverage load current. Therefore the load current at which the device enters Eco-mode is dependent on theoutput inductor value. The circuit in Figure 48 enters Eco-mode at about a 25-mA output current. As the loadcurrent approaches zero, the device enters a pulse-skip mode. During the time period when there is no switchingthe input current is reduced to the 152-µA quiescent current.

8.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)The TPS54361-Q1 device provides an integrated bootstrap voltage-regulator. A small capacitor between theBOOT and SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshedwhen the high-side MOSFET is off and the external low-side diode conducts. The recommended value of theBOOT capacitor is 0.1 μF. A ceramic capacitor with an X7R or X5R-grade dielectric with a voltage rating of 10 Vor higher is recommended for stable performance over temperature and voltage.

When operating with a low voltage difference from input to output, the high-side MOSFET of the TPS54361-Q1device operates at a 100% duty cycle as long as the BOOT to SW pin voltage is greater than 2.1 V. When thevoltage from BOOT to SW drops below 2.1 V, the high-side MOSFET turns off and an integrated low-sideMOSFET pulls SW low to recharge the BOOT capacitor. To reduce the losses of the small low-side MOSFET athigh output voltages, the small low-side MOSFET disables at 24-V output and re-enables when the outputreaches 21.5 V.

Because the gate-drive current sourced from the BOOT capacitor is small, the high-side MOSFET can remain onfor many switching cycles before the MOSFET is turned off to refresh the capacitor. Thus the effective duty cycleof the switching regulator can be high, approaching 100%. The effective duty cycle of the converter duringdropout is mainly influenced by the voltage drops across the power MOSFET, the inductor resistance, the low-side diode voltage and the printed circuit board (PCB) resistance.

The start and stop voltage for a typical 5-V output application is shown in Figure 25 where the input voltage isplotted versus load current. The start voltage is defined as the input voltage required to regulate the output within1% of nominal. The stop voltage is defined as the input voltage at which the output drops by 5% or whereswitching stops.

During high duty-cycle (low-dropout) conditions, inductor current ripple increases when the BOOT capacitor isbeing recharged which results in an increase in output voltage ripple. Increased ripple occurs when the off timerequired to recharge the BOOT capacitor is longer than the high-side off time associated with cycle-by-cyclePWM control.




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(EN)thUVLO2

START (EN)th

UVLO1

VR

V VI1

R

=

-

+

START STOPUVLO1

hys

V VR

I

-

=

O(HS) (LS)

V 0.8 VR R

0.8 V

-æ ö= ´ ç ÷

è ø


Feature Description (continued)At heavy loads, the minimum input voltage must be increased to ensure a monotonic startup. Equation 1calculates the minimum input voltage for this condition.

VOmax = Dmax × (V(VIN)min – IOmax × rDS(on) + Vd) – Vd + IOmax × RDC

where• Dmax ≥ 0.9• rDS(on) = 1 / (–0.3 × V(BOOT_SW)

2 + 3.577 x V(BOOT_SW) – 4.246)• I(BOOT_SW) = 100 µA• V(BOOT_SW) = V(BOOT) + Vd

• V(BOOT) = (1.41 × V(VIN) – 0.554 – Vd × ƒS × 10-6 – 1.847 × 103 × I(BOOT_SW)) / (1.41 + ƒS × 10-6)• Vd = Forward Drop of the Catch Diode (1)

8.3.5 Error AmplifierThe TPS54361-Q1 voltage-regulation loop is controlled by a transconductance error amplifier. The error amplifiercompares the FB pin voltage to the lower of the internal soft-start voltage or the internal 0.8-V voltage reference.The transconductance (gm) of the error amplifier is 350 μA/V during normal operation. During soft-startoperation, the transconductance is reduced to 78 μA/V and the error amplifier is referenced to the internal soft-start voltage.

The frequency compensation components (capacitor, series resistor, and capacitor) are connected between theerror amplifier output COMP pin and GND pin.

8.3.6 Adjusting the Output VoltageThe internal voltage reference produces a precise 0.8-V ±1% voltage reference over the operating temperatureand voltage range by scaling the output of a bandgap reference circuit. The output voltage is set by a resistordivider from the output node to the FB pin. Divider resistors with a 1%-tolerance or better are recommended.Select the low-side resistor RLS for the desired divider current and use Equation 2 to calculate RHS. To improveefficiency at light loads consider using larger value resistors. However, if the values are too high, the regulator ismore susceptible to noise and voltage errors from the FB input current may become noticeable.

(2)

8.3.7 Enable and Adjust Undervoltage LockoutThe TPS54361-Q1 device enables when the VIN pin voltage rises above 4.3 V and the EN pin voltage exceedsthe enable threshold of 1.2 V. The TPS54361-Q1 device disables when the VIN pin voltage falls below 4 V orwhen the EN pin voltage is below 1.2 V. The EN pin has an internal pullup current source, I1, of 1.2 μA thatenables operation of the TPS54361-Q1 device when the EN pin floats.

If an application requires a higher undervoltage-lockout (UVLO) threshold, use the circuit shown in Figure 26 toadjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.2 V, an additional3.4 μA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below 1.2 V, the 3.- μAIhys current is removed. This additional current facilitates the adjustable input-voltage UVLO hysteresis. UseEquation 3 to calculate RUVLO1 for the desired UVLO hysteresis voltage. Use Equation 4 to calculate RUVLO2 forthe desired VIN start voltage.

In applications designed to start at relatively low input voltages (that is, from 4.5 V to 9 V) and withstand highinput voltages (that is, from 40 V to 60 V), the EN pin experiences a voltage greater than the absolute maximumvoltage of 8.4 V during the high input voltage condition. To avoid exceeding this voltage when using the ENresistors, the EN pin is clamped internally with a 5.8-V Zener diode that sinks up to 150 μA.

(3)

(4)




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VO

V(FB)

V(SS/TR)

V(EN)

SS SSSS

ref

t (ms) I (μA)C (nF) =

V (V) 0.8

´

´

TPS54361-Q1

RUVLO1

RUVLO2

EN

V(EN)th

IhysI1

VIN V(VIN)

RUVLO1

RUVLO2

ENNode

5.8 V

10 kΩ

TPS54361-Q1


Feature Description (continued)

Figure 26. Adjustable Undervoltage Lockout Figure 27. Internal EN Pin Clamp(UVLO)

8.3.8 Soft-Start/Tracking Pin (SS/TR)The TPS54361-Q1 device effectively uses the lower voltage of the internal voltage reference or the SS/TR pinvoltage as the reference voltage of the power-supply and regulates the output accordingly. A capacitor on theSS/TR pin to ground implements a soft-start time. The TPS54361-Q1 has an internal pullup current source of 1.7μA that charges the external soft-start capacitor. The calculations for the soft-start time (10% to 90%) are shownin Equation 5. The voltage reference (Vref) is 0.8 V and the soft-start current (ISS) is 1.7 μA. The soft-startcapacitor must remain lower than 0.47 μF and greater than 0.47 nF.

(5)

At power up, the TPS54361-Q1 device does not start switching until the soft-start pin is discharged to less than54 mV to ensure a proper power up, see Figure 28.

Also, during normal operation, the TPS54361-Q1 device stops switching and the SS/TR must discharge to 54mV when one of the following occurs: the VIN UVLO is exceeded, the EN pin pulled below 1.2 V, or a thermalshutdown event occurs.

The FB voltage follows the SS/TR pin voltage with a 42 mV offset up to 85% of the internal voltage reference.When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as theeffective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23).The SS/TR voltage ramps linearly until clamped at 2.7 V typically as shown in Figure 28.

Figure 28. Operation of SS/TR Pin When Starting16 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated



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VO(2)

VO(1)

V(PWRGD)

V(EN)(1)

SS/TR

TPS54361-Q1

EN

PWRGD

SS/TR

ENPWRGD

TPS54361-Q1


Feature Description (continued)8.3.9 SequencingMany of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGDpins. The sequential method can be implemented using an open drain output of a power on reset pin of anotherdevice. The sequential method is illustrated in Figure 29 using two TPS54361-Q1 devices. The power good isconnected to the EN pin on the TPS54361-Q1 which enables the second power supply once the primary supplyreaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply provides a 1-ms start-up delay. Figure 30 shows the results of Figure 29.

Figure 29. Schematic for Sequential Start-Up Figure 30. Sequential Startup using EN andSequence PWRGD




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SS /TR

TPS54361-Q1

EN

PWRGD

SS / TR

EN

PWRGD

VO(1)

VO(2)

R(TR)1

R(TR)2

R (HS)

R(LS)

TPS54361-Q1

FB

EN

TPS54361-Q1

3

SS/TR4

PWRGD6

EN

TPS54361-Q1

3

SS/TR4

PWRGD6

V(EN)(1), V(EN)(2)

VO(1)

VO(2)



Figure 31. Schematic for Ratiometric Start-Up Figure 32. Ratio-Metric Startup Using CoupledSequence SS/TR pins

Figure 31 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. Theregulator outputs ramps up and reaches regulation at the same time. When calculating the soft-start time thepullup current source must be doubled in Equation 5. Figure 32 shows the results of Figure 31.

Figure 33. Schematic for Ratiometric and Simultaneous Start-Up Sequence




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V(EN)

VO(1)

VO(2)

V(EN)

VO(1)

VO(2)

ref (TR)1(TR)2

O(2) ref

V RR

V V V

´=

+ D -

O(2) SS(ofs)(TR)1

ref SS

V V VR

V I

+ D= ´


Feature Description (continued)Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor networkof R(TR)1 and R(TR)2 shown in Figure 33 to the output of the power supply that needs to be tracked or anothervoltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate theVO(2) slightly before, after or at the same time as VO(1). Equation 8 is the voltage difference between VO(1) andVO(2) at the 95% of nominal output regulation.

The ΔV variable is 0 V for simultaneous sequencing. To minimize the effect of the inherent SS/TR to FB offset(VSS(ofs)) in the soft-start circuit and the offset created by the pullup current source (ISS) and tracking resistors, theVSS(ofs) and ISS are included as variables in the equations.

To design a ratio-metric start up in which the VO(2) voltage is slightly greater than the VO(1) voltage when VO(2)reaches regulation, use a negative number in Equation 6 through Equation 8 for ΔV. Equation 8 results in apositive number for applications which the VO(2) is slightly lower than VO(1) when VO(2) regulation is achieved.

Because the SS/TR pin must be pulled below 54 mV before starting after an EN, UVLO or thermal shutdownfault, careful selection of the tracking resistors is needed to ensure the device restarts after a fault. Make sure thecalculated R(TR)1 value from Equation 6 is greater than the value calculated in Equation 9 to ensure the devicecan recover from a fault.

As the SS/TR voltage becomes more than 85% of the nominal reference voltage the VSS(ofs) becomes larger asthe soft-start circuits gradually handoff the regulation reference to the internal voltage reference. The SS/TR pinvoltage must be greater than 1.5 V for a complete handoff to the internal voltage reference as shown inFigure 23.

(6)

(7)ΔV = VO(1) – VO(2) (8)R(TR)1 > 2800 × VO(1) – 180 × ΔV (9)

Figure 34. Ratiometric Startup With Tracking Resistors Figure 35. Ratiometric Startup With Tracking Resistors




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S 1.008(RT)

101756ƒ (kHz)

R (k )=

W

(RT) 0.991S

92417R (k )

ƒ (kHz)W =

V(EN)

VO(1)

VO(2)



Figure 36. Simultaneous Startup With Tracking Resistor

8.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK) Pin)The switching frequency of the TPS54361-Q1 is adjustable over a wide range from 100 kHz to 2500 kHz byplacing a resistor between the RT/CLK pin and GND pin. The RT/CLK pin voltage is typically 0.5 V and musthave a resistor to ground to set the switching frequency. To determine the timing resistance for a given switchingfrequency, use Equation 10 or Equation 11 or the curves in Figure 5 and Figure 6. To reduce the solution sizeone would typically set the switching frequency as high as possible, but tradeoffs of the conversion efficiency,maximum input voltage and minimum controllable on time must be considered. The minimum controllable ontime is typically 100 ns which limits the maximum operating frequency in applications with high input to outputstep down ratios. The maximum switching frequency is also limited by the frequency foldback circuit. A moredetailed discussion of the maximum switching frequency is provided in the next section.

(10)

(11)

8.3.11 Accurate Current-Limit Operation and Maximum Switching FrequencyThe TPS54361-Q1 implements peak current mode control in which the COMP pin voltage controls the peakcurrent of the high-side MOSFET. A signal proportional to the high-side switch current and the COMP pin voltageare compared each cycle. When the peak switch current intersects the COMP control voltage, the high-sideswitch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier increasesswitch current by driving the COMP pin high. The error amplifier output is clamped internally at a level which setsthe peak switch current-limit. The TPS54361-Q1 provides an accurate current-limit threshold with a typicalcurrent-limit delay of 60 ns. With smaller inductor values, the delay results in a higher peak inductor current. Therelationship between the inductor value and the peak inductor current is shown in Figure 37.




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( )( )

O DC O dS skip

on (VIN) O dDS on

I R V V1max

t V max I r V

æ ö´ + +ç ÷= ´ç ÷- ´ +è ø

ƒ

ton

td(CL)

Inducto

r C

urr

ent (A

) ΔCL(peak)

Peak inductor current

Open-loop Current-limit

ΔCL(peak) = V / L × t(VIN) d(CL)



Figure 37. Current Limit Delay

To protect the converter in overload conditions at higher switching frequencies and input voltages, theTPS54361-Q1 implements a frequency foldback. The oscillator frequency is divided by 1, 2, 4, and 8 as the FBpin voltage falls from 0.8 V to 0 V. The TPS54361-Q1 device uses a digital frequency foldback to enablesynchronization to an external clock during normal start-up and fault conditions. During short-circuit events, theinductor current may exceed the peak current limit because of the high input voltage and the minimumcontrollable on time. When the output voltage is forced low by the shorted load, the inductor current decreasesslowly during the switch off time. The frequency foldback effectively increases the off time by increasing theperiod of the switching cycle providing more time for the inductor current to ramp down.

With a maximum frequency foldback ratio of 8, there is a maximum frequency at which the inductor current canbe controlled by frequency foldback protection. calculates the maximum switching frequency at which theinductor current remains under control when VO is forced to VO(SC). The selected operating frequency must notexceed the calculated value.

Equation 12 calculates the maximum switching frequency limitation set by the minimum controllable on time andthe input to output step down ratio. Setting the switching frequency above this value causes the regulator to skipswitching pulses to achieve the low duty cycle required to regulate the output at maximum input voltage.

where• ton = controllable on time• IO = output current• RDC = inductor resistance• V(VIN)max = maximum input voltage• VO = output voltage• Vd = diode voltage drop (12)




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RT/CLK

TPS54361-Q1

Clock

Source

PLLR(RT)

RT/CLK

TPS54361-Q1

Hi-Z

Clock

Source

PLL

R(RT)

( )

( )

CL DC dO SCdivS(shift)

on (VIN) CL dDS on

I R V V

t V I r V

æ ö´ + +ç ÷= ´ç ÷- ´ +è ø

ƒƒ



where• ƒdiv = frequency divide equals (1, 2, 4, or 8)• VO(SC) = output voltage during short• ICL = current limit• rDS(on) = switch on resistance (13)

8.3.12 Synchronization to RT/CLK PinThe RT/CLK pin can receive a frequency synchronization signal from an external system clock. To implementthis synchronization feature connect a square wave to the RT/CLK pin through either circuit network shown inFigure 38. The square wave applied to the RT/CLK pin must switch lower than 0.5 V and higher than 2 V andhave a pulse width greater than 15 ns. The synchronization frequency range is 160 kHz to 2300 kHz. The risingedge of the SW is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuitmust be designed such that the default frequency set resistor is connected from the RT/CLK pin to ground whenthe synchronization signal is off. When using a low impedance signal source, the frequency set resistor isconnected in parallel with an ac coupling capacitor to a termination resistor (for example, 50 Ω) as shown inFigure 38. The two resistors in series provide the default frequency setting resistance when the signal source isturned off. The sum of the resistance must set the switching frequency close to the external CLK frequency. ACcoupling the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin is recommended.

The first time the RT/CLK is pulled above the PLL threshold the TPS54361-Q1 switches from the RT resistorfree-running frequency mode to the PLL synchronized mode. The internal 0.5 V voltage source is removed andthe RT/CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switchingfrequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions fromthe resistor mode to the PLL mode and locks onto the external clock frequency within 78 ms. During thetransition from the PLL mode to the resistor programmed mode, the switching frequency falls to 150 kHz andthen increases or decreases to the resistor programmed frequency when the 0.5 V bias voltage is reapplied tothe RT/CLK resistor.

The switching frequency is divided by 8, 4, 2, and 1 as the FB pin voltage ramps from 0 to 0.8 V. The deviceimplements a digital frequency foldback to enable synchronizing to an external clock during normal start-up andfault conditions. Figure 39, Figure 40 and Figure 41 show the device synchronized to an external system clock incontinuous conduction mode (CCM), discontinuous conduction (DCM), and pulse skip mode (Eco-Mode).

Figure 38. Synchronizing to a System Clock




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V(SW)

EXT

IL

V(SW)

EXT

IL

V(SW)

EXT

IL



Figure 40. Plot of Synchronizing in DCMFigure 39. Plot of Synchronizing in CCM

Figure 41. Plot of Synchronizing in Eco-mode

8.3.13 Power Good (PWRGD Pin)The PWRGD pin is an open drain output. When the FB pin is between 93% and 106% of the internal voltagereference the PWRGD pin is de-asserted and the pin floats. A pull-up resistor of 1 kΩ to a voltage source that is5.5 V or less is recommended. A higher pull-up resistance reduces the amount of current drawn from the pull upvoltage source when the PWRGD pin is asserted low. A lower pull-up resistance reduces the switching noiseseen on the PWRGD signal. The PWRGD is in a defined state once the VIN input voltage is greater than 2 V butwith reduced current sinking capability. The PWRGD achieves full current-sinking capability as VIN input voltageapproaches 3 V.

The PWRGD pin is pulled low when the FB is lower than 90% or greater than 108% of the nominal internalreference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pinpulled low.




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FB

COMP

VO

R(HS)

R(COMP)

C(ZERO)

C(POLE) R(LS)

C(OEA) R(OEA)gmea

350 µA/V

0.8 V

Power Stage

gm 12 A/Vps

SW

R(ESR)

C(O)

R(L)

b

a

c


Feature Description (continued)8.3.14 Overvoltage ProtectionThe TPS54361-Q1 device incorporates an output overvoltage protection (OVP) circuit to minimize voltageovershoot when recovering from output fault conditions or strong unload transients in designs with low outputcapacitance. For example, when the power supply output is overloaded the error amplifier compares the actualoutput voltage to the internal reference voltage. If the FB pin voltage is lower than the internal reference voltagefor a considerable time, the output of the error amplifier increases to a maximum voltage corresponding to thepeak current limit threshold. When the overload condition is removed, the regulator output rises and the erroramplifier output transitions to the normal operating level. In some applications, the power supply output voltagecan increase faster than the response of the error amplifier output resulting in an output overshoot.

The OVP feature minimizes output overshoot when using a low value output capacitor by comparing the FB pinvoltage to the rising OVP threshold which is nominally 108% of the internal voltage reference. If the FB pinvoltage is greater than the rising OVP threshold, the high-side MOSFET is immediately disabled to minimizeoutput overshoot. When the FB voltage drops below the falling OVP threshold which is nominally 106% of theinternal voltage reference, the high-side MOSFET resumes normal operation.

8.3.15 Thermal ShutdownThe TPS54361-Q1 device provides an internal thermal shutdown to protect the device when the junctiontemperature exceeds 176°C. The high-side MOSFET stops switching when the junction temperature exceeds thethermal trip threshold. Once the die temperature falls below 164°C, the device reinitiates the power up sequencecontrolled by discharging the SS/TR pin.

8.3.16 Small Signal Model for Loop ResponseFigure 42 shows a simplified equivalent model for the TPS54361-Q1 control loop which can be simulated tocheck the frequency response and dynamic load response. The error amplifier is a transconductance amplifierwith a gmea of 350 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source.The resistor, R(OEA), and capacitor, C(OEA), model the open loop gain and frequency response of the amplifier.The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequencyresponse measurements. Plotting c-a provides the small signal response of the frequency compensation. Plottinga-b provides the small signal response of the overall loop. The dynamic loop response can be evaluated byreplacing the load resistor, R(L), with a current source with the appropriate load step amplitude and step rate in atime domain analysis. This equivalent model is only valid for continuous conduction mode (CCM) operation.

Figure 42. Small Signal Model for Loop Response




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Z(O) (ESR)

1ƒ

C R 2=

´ ´ p

P(O) (L)

1ƒ

C R 2=

´ ´ p

ZODC

( )

P

s1

2 ƒVA

V s1

2 ƒ

æ ö+ç ÷

p ´è ø= ´æ ö

+ç ÷p ´è ø

c

VO

R(ESR)

C(O)

R(L)

V( )c

gmps

ƒP

ADC

ƒZ


Feature Description (continued)8.3.17 Simple Small Signal Model for Peak Current Mode ControlFigure 43 describes a simple small signal model that can be used to design the frequency compensation. TheTPS54361-Q1 device power stage can be approximated by a voltage-controlled current source (duty cyclemodulator) supplying current to the output capacitor and load resistor. The control to output transfer function isshown in Equation 14 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of thechange in switch current and the change in COMP pin voltage (node c in Figure 42) is the power stagetransconductance, gmps. The gmps for the TPS54361-Q1 device is 12 A/V. The low-frequency gain of the powerstage is the product of the transconductance and the load resistance as shown in Equation 15.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. Thisvariation with the load may seem problematic at first glance, but fortunately the dominant pole moves with theload current (see Equation 16). The combined effect is highlighted by the dashed line in the right half ofFigure 43. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dBcrossover frequency the same with varying load conditions. The type of output capacitor chosen determineswhether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminumelectrolytic capacitors may reduce the number frequency compensation components needed to stabilize theoverall loop because the phase margin is increased by the ESR zero of the output capacitor (see Equation 17).

Figure 43. Simple Small Signal Model and Frequency Response for Peak Current Mode Control

(14)ADC = gmps × R(L) (15)

(16)

(17)

8.3.18 Small Signal Model for Frequency CompensationThe TPS54361-Q1 device uses a transconductance amplifier for the error amplifier and supports three of thecommonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 areshown in Figure 44. Type 2 circuits are typically implemented in high bandwidth power-supply designs using lowESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminumelectrolytic or tantalum capacitors. Equation 18 and Equation 19 relate the frequency response of the amplifier tothe small signal model in Figure 44. The open-loop gain and bandwidth are modeled using the R(OEA) and C(OEA)shown in Figure 44. See the application section for a design example using a Type 2A network with a low ESRoutput capacitor.




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(LS)ea (OEA) (COMP)

(HS) (LS)

RA1 gm R R

R R= ´ ´

+

P

(LS)ea (OEA)

(HS) (LS)

RA0 gm R

R R= ´ ´

+

Z1

P1 P2

s1

2 ƒEA A0

s s1 1

2 ƒ 2 ƒ

æ ö+ç ÷

p ´è ø= ´æ öæ ö æ ö

+ ´ +ç ÷ç ÷ ç ÷ç ÷p ´ p ´è ø è øè ø

( )ea

(OEA)

gmC

2 BW Hz=

p ´

( )(OEA)

ea

Aol V/VR

gm=

A0

A1

P1

Z1 P2

Aol

BW

Vref

VO

R(HS)

R(COMP)

C(ZERO)

C(POLE)

R(LS)

C(OEA)

gmea COMP

FBType 2A Type 2B Type 1

R(OEA)

R(COMP)

C(ZERO)

C(POLE)


Feature Description (continued)Equation 18 through Equation 27 are provided as a reference. An alternative is to use WEBENCH software toolsto create a design based on the power supply requirements.

Figure 44. Types of Frequency Compensation

Figure 45. Frequency Response of the Type 2A and Type 2B Frequency Compensation

(18)

(19)

(20)

(21)

(22)




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π (OEA) (POLE) (OEA)

1P2 = type 1

2 R (C + C )´ ´

(COMP) (OEA) (OEA)

1P2 Type 2B

2 R R C=

p ´ ´P

( )(COMP) (OEA) (POLE) (OEA)

1P2 Type 2A

2 R R C C=

p ´ ´ +P

(COMP) (ZERO)

1Z1

2 R C=

p ´ ´

(OEA) (ZERO)

1P1

2 R C=

p ´ ´



(23)

(24)

(25)

(26)

(27)

8.4 Device Functional Modes

8.4.1 Operation with V(VIN) = < 4.5 V (Minimum V(VIN))The device is recommended to operate with input voltages above 4.5 V. The typical VIN UVLO threshold is 4.3 Vand the device may operate at input voltages down to the UVLO voltage. At input voltages below the actualUVLO voltage, the device will not switch. If EN is externally pulled up to V(VIN) using an external resistor divider orleft floating, when V(VIN) passes the UVLO threshold the device will become active. Switching is enabled, andthe soft start sequence is initiated. The TPS54361-Q1 device starts at the soft start time determined by theexternal capacitance at the SS/TR pin.

8.4.2 Operation with EN ControlThe enable threshold voltage is 1.2 V typical. With EN held below that voltage the device is disabled andswitching is inhibited even if VIN is above its UVLO threshold. The IC quiescent current is reduced in this state. Ifthe EN voltage is increased above the threshold while VIN is above its UVLO threshold, the device becomesactive. Switching is enabled, and the soft start sequence is initiated. The TPS54361-Q1 device starts at the soft-start time determined by the external capacitance at the SS/TR pin.

8.4.3 Alternate Power Supply Topologies

8.4.3.1 Inverting Power SupplyThe TPS54361-Q1 can be used to convert a positive input voltage to a negative output voltage. Idea applicationsare amplifiers requiring a negative power supply. For a more detailed example see SLVA317.




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PHVIN

GND

BOOT

FB

COMP

TPS54361-Q1

EN

RT /CLK

SS /TR

C(POLE)C(ZERO)

R(COMP)

R(RT)C(SS)

CO–

LO

C(BOOT)CI

R(HS)

R(LS)

C(VIN)

VI

VO–

+

+

GND

VO+

CO+

+

PHVIN

GND

BOOT

FB

COMP

TPS54361-Q1

EN

RT /CLK

SS /TR

C(POLE)C(ZERO)

R(COMP)

R(RT)C(SS)

C(O)

LO

C(BOOT)CI

R(HS)

R(LS)

C(VIN)

VI

VO

+

+

GND


Device Functional Modes (continued)

Figure 46. TPS54361-Q1 Inverting Power Supply based on the Application Note, SLVA317

8.4.3.2 Split Rail Power SupplyThe TPS54361-Q1 device can be used to convert a positive input voltage to a split rail positive and negativeoutput voltage by using a coupled inductor. Idea applications are amplifiers requiring a split rail positive andnegative voltage power supply. For a more detailed example see SLVA369.

Figure 47. TPS54361-Q1 Split Rail Power Supply based on the Application Note, SLVA369




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VI

GND

ENGND

7 V to 60 V

2.2 µFC1

2.2 µFC2

2.2 µFC3DNP

GND

GND

GND

90.9 kΩR2

442 kΩR1

GND

TP1

TP2

12

J3

12

J4

GND

2.2 µFC10DNP

1

2

J2

21

+C11

DNP

0.01 µFC13

PWRGD

TP10

FB

BOOT1

VIN2

EN3

SS/TR4

RT/CLK5

FB6

COMP7

GND8

SW9

PWRGD10

PAD

U1

TPS54361-Q1

162 kΩR3

13 kΩR4

39 pFC8

6800 pFC5

12

J5

SS/TRGND

GND

SS/TR

GND

SS/TR

0.1 µF

C4

5 V at 3.5 A

VO

GND

147 µFC9DNP

47µFC7

47 µFC6

GND

GND

49.9 ΩR7

53.6 kΩR5

10.2 kΩR6

TP6

TP8

TP4

TP7TP5

TP3

8.2µH

L1

1

2

J1

21

+ C12

DNP

13

2

D1

FB

PWRGD PULL UP

TP91.00 kΩ

R8


9 Application and Implementation

9.1 Application InformationThe TPS54361-Q1 device is a 60-V, 3.5-A, step down regulator with an integrated high side MOSFET. Thisdevice is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available outputcurrent of 3.5 A. Example applications are: 12 V, 24 V and 48 V Industrial, Automotive and CommunicationsPower Systems. Use the following design procedure to select component values for the TPS54361-Q1 device.This procedure illustrates the design of a high frequency switching regulator using ceramic output capacitors.Calculations can be done with the excel spreadsheet (SLVC452) located on the product page. Alternately, usethe WEBENCH software to generate a complete design. The WEBENCH software uses an iterative designprocedure and accesses a comprehensive database of components when generating a design. This sectionpresents a simplified discussion of the design process.

9.2 Typical Application

Figure 48. 5-V Output TPS54361-Q1 Design Example

9.2.1 Design RequirementsA few parameters must be known in order to start the design process. These requirements are typicallydetermined at the system level. This example is designed to the following known parameters:

Table 1. Design ParametersDESIGN PARAMETER EXAMPLE VALUEOutput Voltage (VO) 5 VTransient Response 0.875-A to 2.625-A load step ΔVO = ±4 %Maximum Output Current (IO) 3.5 AInput Voltage (VI) 12 V nominal 7 V to 60 VOutput Voltage Ripple (VO(rip)) 0.5% of VO

Start Input Voltage (rising VI) 6.5 VStop Input Voltage (falling VI) 5 V

9.2.2 Detailed Design Procedure

9.2.2.1 Selecting the Switching FrequencyThe first step is to choose a switching frequency for the regulator. Typically, the designer uses the highestswitching frequency possible because the highest switching frequency produces the smallest solution size. Highswitching frequency allows for lower value inductors and smaller output capacitors compared to a power supplythat switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage and the frequency foldback protection.




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http://www.ti.com/lit/zip/slvc452



0.991

92417R3 (k ) = = 163 k

600 (kHz)W W

S(shift)8 4.7 A 25 m 0.1 V 0.7 V

1220 kHz100 ns 60 V – 4.7 A 87 m 0.7 V

´ W + +æ ö= ´ =ç ÷´ W +è ø

ƒ

S(skip)1 3.5 A 25 m 5 V 0.7 V

max 960 kHz100 ns 60 V 3.5 A 87 m 0.7 V

´ W + +æ ö= ´ =ç ÷´ W +è ø

ƒ–


Equation 12 and must be used to calculate the upper limit of the switching frequency for the regulator. Choosethe lower value result from the two equations. Switching frequencies higher than these values results in pulseskipping or the lack of overcurrent protection during a short circuit.

The typical minimum on time, ton, is 100 ns for the TPS54361-Q1 device. For this example, the output voltage is5 V and the maximum input voltage is 60 V, which allows for a maximum switch frequency up to 960 kHz toavoid pulse skipping from Equation 12. To ensure overcurrent runaway is not a concern during short circuits useto determine the maximum switching frequency for frequency foldback protection. With a maximum input voltageof 60 V, assuming a diode voltage of 0.7 V, inductor resistance of 25 mΩ, switch resistance of 87 mΩ, a currentlimit value of 4.7 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 1220 kHz.

For this design, a lower switching frequency of 600 kHz is chosen to operate comfortably below the calculatedmaximums. To determine the timing resistance for a given switching frequency, use Equation 10 or the curve inFigure 6. The switching frequency is set by resistor R3 shown in Figure 48. For 600 kHz operation, the closeststandard value resistor is 162 kΩ.

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(30)

9.2.2.2 Output Inductor Selection (LO)To calculate the minimum value of the output inductor, use Equation 31.

KIND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. Theinductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currentsimpacts the selection of the output capacitor because the output capacitor must have a ripple current rating equalto or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of thedesigner, however, the following guidelines may be used.

For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be desirable.When using higher ESR output capacitors, KIND = 0.2 yields better results. Because the inductor ripple current ispart of the current mode PWM control system, the inductor ripple current must always be greater than 150 mAfor stable PWM operation. In a wide input voltage regulator, choosing a relatively large inductor ripple current isbest to provide sufficient ripple current with the input voltage at the minimum.

For this design example, KIND = 0.3 and the minimum inductor value is calculated to be 7.3 μH. The neareststandard value is 8.2 μH. It is important that the RMS current and saturation current ratings of the inductor not beexceeded. The RMS and peak inductor current can be found from Equation 33 and Equation 34. For this design,the RMS inductor current is 3.5 A and the peak inductor current is 3.97 A. The chosen inductor has a saturationcurrent rating of 5.8 A and an RMS current rating of 5.05 A.

As the equation set demonstrates, lower ripple currents reduce the output voltage ripple of the regulator butrequire a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of theregulator but allows for a lower inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up,faults or transient load conditions, the inductor current can increase above the peak inductor current levelcalculated above. In transient conditions, the inductor current can increase up to the switch current limit of thedevice. For this reason, the most conservative design approach is to choose an inductor with a saturation currentrating equal to or greater than the switch current limit of the TPS54361-Q1 which is nominally 5.5 A.




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( )rip

OL peak

I 0.932 AI I 3.5 A 3.97 A

2 2= + = + =

( ) ( ) ( ) ( ) ( )2 22 2O I O

OL RMSI O S

V V max V 5 V 60 V – 5 V1 1I I 3.5 A 3.5 A

12 V max L 12 60 V 8.2 µH 600 kHz

æ ö æ ö´ - ´= + ´ = + ´ =ç ÷ ç ÷ç ÷ç ÷´ ´ ´ ´è øè øƒ

O I Orip

I O S

V (V max V ) 5 V (60 V 5 V)I 0.932 A

V max L ƒ 60 V 8.2 µH 600 kHz

´ - ´

= = =

´ ´ ´ ´

–

I O OO

O IND I S

V max V V 60 V 5 V 5 VL min 7.3 µH

I K V max 3.5 A 0.3 60 V 600 kHz

-

= ´ = ´ =

´ ´ ´ ´

–

ƒ


(31)

spacer

(32)

spacer

(33)

spacer

(34)

9.2.2.3 Output CapacitorThere are three primary considerations for selecting the value of the output capacitor. The output capacitordetermines the modulator pole, the output voltage ripple, and how the regulator responds to a large change inload current. The output capacitance needs to be selected based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs tosupply the increased load current until the regulator responds to the load step. The regulator does not respondimmediately to a large, fast increase in the load current such as transitioning from no load to a full load. Theregulator usually needs two or more clock cycles for the control loop to sense the change in output voltage andadjust the peak switch current in response to the higher load. The output capacitance must be large enough tosupply the difference in current for 2 clock cycles to maintain the output voltage within the specified range.Equation 35 shows the minimum output capacitance necessary, where ΔIO is the change in output current, ƒS isthe regulators switching frequency and ΔVO is the allowable change in the output voltage. For this example, thetransient load response is specified as a 4% change in VO for a load step from 0.875 A to 2.625 A. Therefore,ΔIO is 2.625 A - 0.875 A = 1.75 A and ΔVO = 0.04 × 5 = 0.2 V. Using these numbers gives a minimumcapacitance of 29.2 μF. This value does not take the ESR of the output capacitor into account in the outputvoltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolyticand tantalum capacitors have higher ESR that must be included in load step calculations.

The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high tolow load current. The catch diode of the regulator can not sink current so energy stored in the inductor canproduce an output voltage overshoot when the load current rapidly decreases. A typical load step response isshown in Figure 49. The excess energy absorbed in the output capacitor increases the voltage on the capacitor.The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 36calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where LOis the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is thepeak output voltage, and V(int) is the initial voltage. For this example, the worst case load step is from 2.625 A to0.875 A. The output voltage increases during this load transition and the stated maximum in our specification is4 % of the output voltage which makes Vf = 1.04 × 5 = 5.2. V(int) is the initial capacitor voltage which is thenominal output voltage of 5 V. Using these numbers in Equation 36 yields a minimum capacitance of 25 μF.

Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification,where ƒsw is the switching frequency, VO(rip) is the maximum allowable output voltage ripple, and Irip is theinductor ripple current. Equation 37 yields 7.8 μF.

Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripplespecification. Equation 38 indicates the ESR must be less than 27 mΩ.

The most stringent criteria for the output capacitor is 29 μF required to maintain the output voltage withinregulation tolerance during a load transient.




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( ) ( )

( )

2j S I dI O O d

DI

2

C ƒ V VV V I VP

V 2

12 V 5 V 3.5 A 0.55 V 90 pF 600 kHz (12 V 0.55 V)1.13 W

12 V 2

´ ´ +- ´ ´= + =

- ´ ´ ´ ´ ++ =

( ) ( )O I OCO(RMS)

I O S

V V min V 5 V 60 V 5 VI 269 mA

12 V min L ƒ 12 60 V 8.2 µH 600 kHz

´ - ´= = =

´ ´ ´ ´ ´ ´

–

O(rip)(ESR)

rip

V 25 mVR 27 m

I 0.932 A< = = W

(O)S O(rip)

rip

1 1 1 1C 7.8 µF

25 mV8 ƒ 8 600 kHzV

0.932 AI

> ´ = ´ =´ ´æ ö æ ö

ç ÷ç ÷ç ÷ è øè ø

( ) ( )( )( ) ( )

( )( )

2 2 2 2OH OL

(O) O 2 2 22f (int)

I I 2.625 A 0.875 AC L 8.2 µH 24.6 µF

5.2 V 5 VV V

- -> ´ = ´ =

æ ö-ç ÷è ø

–

O(O)

S O

2 I 2 1.75 AC 29.2 µF

ƒ V 600 kHz 0.2 V

´ D ´> = =

´ D ´


Capacitance de-ratings for aging, temperature and dc bias increases this minimum value. For this example, two47-μF, 10-V ceramic capacitors with 5 mΩ of ESR is used. The derated capacitance is 58 µF, well above theminimum required capacitance of 29 µF.

Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitorreliability. Some capacitor data sheets specify the root-mean-square (RMS) value of the maximum ripple current.Equation 39 can be used to calculate the RMS ripple current that the output capacitor must support. For thisexample, Equation 39 yields 269 mA.

(35)

(36)

(37)

(38)

(39)

9.2.2.4 Catch DiodeThe TPS54361-Q1 device requires an external catch diode between the SW pin and GND. The selected diodemust have a reverse voltage rating equal to or greater than VImax. The peak current rating of the diode must begreater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diodebecause of the low forward voltage of these diodes. The lower the forward voltage of the diode, the higher theefficiency of the regulator.

Typically, diodes with higher voltage and current ratings have higher forward voltages. A diode with a minimum of60 V reverse voltage is preferred to allow input voltage transients up to the rated voltage of the TPS54361-Q1device.

For the example design, the Schottky diode was selected for its lower forward voltage and good thermalcharacteristics compared to smaller devices. The typical forward voltage of the diode is 0.55 V at 3.5 A.

The diode must also be selected with an appropriate power rating. The diode conducts the output current duringthe off-time of the internal power switch. The off-time of the internal switch is a function of the maximum inputvoltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied bythe forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higherswitching frequencies, the AC losses of the diode must be taken into account. The AC losses of the diode arebecause of the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 isused to calculate the total power dissipation, including conduction losses and AC losses of the diode.

The selected diode has a junction capacitance of 90 pF. Using Equation 40 with the nominal voltage VI of 12 V,the total loss in the diode is 1.13 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using adiode which has a low leakage current and slightly higher forward voltage drop.

(40)




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( )SS SS

SSref

t (ms) I (µA) 3.5 ms 1.7 µAC (nF) 9.3 nF

V (V) 0.8 0.8 V 0.8

´ ´= = =

´ ´

(O) OSS

SS(AV)

C V 0.8t

I

´ ´

>

OI

I S

I 0.25 3.5 A 0.25V 331 mV

C ƒ 4.4 µF 600 kHz

´ ´D = = =

´ ´

( )( ) ( )I OO

OCI RMSI I

V min V 8.5 V – 5 VV 5 VI I x 3.5 A 1.72 A

V min V min 8.5 V 8.5 V

-= ´ = ´ =


9.2.2.5 Input CapacitorThe TPS54361-Q1 device requires a high quality ceramic type X5R or X7R input decoupling capacitor with atleast 3 μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effectivecapacitance includes any loss of capacitance because of DC-bias effects. The voltage rating of the inputcapacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current ratinggreater than the maximum input current ripple of the TPS54361-Q1 device. The input ripple current can becalculated using Equation 41.

The value of a ceramic capacitor varies significantly with temperature and the dc bias applied to the capacitor.The capacitance variations because of temperature can be minimized by selecting a dielectric material that ismore stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulatorcapacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. Theinput capacitor must also be selected with consideration for the dc bias. The effective value of a capacitordecreases as the dc bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 60 V voltage rating is required to support themaximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25V, 50 V or 100 V. For this example, two 2.2-μF, 100-V capacitors in parallel are used.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can becalculated using Equation 42. Using the design example values, IO = 3.5 A, CI = 4.4 μF, ƒS = 600 kHz, yields aninput voltage ripple of 331 mV and a RMS input ripple current of 1.72 A.

(41)

(42)

9.2.2.6 Slow-Start CapacitorThe slow-start capacitor determines the minimum amount of time required for the output voltage to reach itsnominal programmed value during power-up. This feature of the slow-start capacitor is useful if a load requires acontrolled voltage slew rate. This feature is also used if the output capacitance is large and would require largeamounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary tocharge the capacitor can make the TPS54361-Q1 device reach the current limit or excessive current draw fromthe input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves bothof these problems.

The slow start time must be long enough to allow the regulator to charge the output capacitor up to the outputvoltage without drawing excessive current. Equation 43 can be used to find the minimum slow start time, tSS,necessary to charge the output capacitor, C(O), from 10% to 90% of the output voltage, VO, with an average slowstart current of ISS(AV). In the example, to charge the effective output capacitance of 58 µF up to 5 V with anaverage current of 1 A requires a 0.2 ms slow start time.

Once the slow start time is known, the slow start capacitor value can be calculated using Equation 5. For theexample circuit, the slow start time is not too critical because the output capacitor value is 2 × 47 μF which doesnot require much current to charge to 5 V. The example circuit has the slow start time set to an arbitrary value of3.5 ms which requires a 9.3-nF slow start capacitor calculated by Equation 44. For this design, the next largerstandard value of 10 nF is used.

(43)

(44)

9.2.2.7 Bootstrap Capacitor SelectionA 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins for proper operation. A ceramiccapacitor with X5R or better grade dielectric is recommended. The capacitor must have a 10 V or higher voltagerating.




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CO P(mod) Z(mod) 1912 Hz 1092 kHz 45.7 kHz´

= = ´ =ƒ ƒ ƒ

( )Z mod

1 1ƒ 1092 kHz

2 R6 C4 2 2.5 m 58.3 µF= = =

´ p ´ ´ ´ p ´ W ´

( )O

P modO (O)

I max 3.5 Aƒ 1912 Hz

2 V C 2 5 V 58.3 µF= = =

´ p ´ ´ ´ p ´ ´

OV 0.8 V 5 V 0.8 VR5 R6 10.2 k 53.5 k

0.8 V 0.8 V

- -æ ö= ´ = W ´ = Wç ÷

è ø

(EN)

START (EN)

V 1.2 VR2 90.9 k

V – V 6.5 V – 1.2 V1.2 µAI1

442 kR1

= = = W

++W

START STOP

hys

V – V 6.5 V – 5 VR1 441 k

I 3.4 µA= = = W


9.2.2.8 Undervoltage Lockout Set PointThe Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of theTPS54361-Q1 device. The UVLO has two thresholds, one for power up when the input voltage is rising and onefor power down or brown outs when the input voltage is falling. For the example design, the supply must turn onand start switching once the input voltage increases above 6.5 V (UVLO start). After the regulator startsswitching, it must continue to do so until the input voltage falls below 5 V (UVLO stop).

Programmable UVLO threshold voltages are set using the resistor divider of R1 and R2 between the VIN pin andground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values necessary. For theexample application, a 442 kΩ between the VIN and EN pins (R1) and a 90.9 kΩ between EN and ground (R2)are required to produce the 6.5-V and 5-V start and stop voltages.

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(46)

9.2.2.9 Output Voltage and Feedback Resistors SelectionThe voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6.Using Equation 2, R5 is calculated as 53.5 kΩ. The nearest standard 1% resistor is 53.6 kΩ. Because of theinput current of the FB pin, the current flowing through the feedback network must be greater than 1 μA tomaintain the output voltage accuracy. This requirement is satisfied if the value of R6 is less than 800 kΩ.Choosing higher resistor values decreases quiescent current and improves efficiency at low output currents butmay also introduce noise immunity problems.

(47)

9.2.2.10 CompensationThere are several methods to design compensation for DC-DC regulators. The method presented here is easy tocalculate and ignores the effects of the slope compensation that is internal to the device. Because the slopecompensation is ignored, the actual crossover frequency is lower than the crossover frequency used in thecalculations. This method assumes the crossover frequency is between the modulator pole and the ESR zeroand the ESR zero is at least ten-times greater the modulator pole.

To get started, the modulator pole, ƒP(mod), and the ESR zero, ƒZ1 must be calculated using Equation 48 andEquation 49. For C(O), use a derated value of 58.3 μF. Use equations Equation 50 and Equation 51 to estimate astarting point for the crossover frequency, ƒCO. For the example design, ƒP(mod) is 1912 Hz and ƒZ(mod) is 1092kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean ofmodulator pole and the switching frequency. Equation 50 yields 45.7 kHz and Equation 51 gives 23.9 kHz. Usethe lower value of Equation 50 or Equation 51 for an initial crossover frequency. For this example, the target ƒcois 23.9 kHz.

Next, the compensation components are calculated. A resistor in series with a capacitor is used to create acompensating zero. A capacitor in parallel to these two components forms the compensating pole.

(48)

where• C(O) is the parallel combination of C6 and C7 Figure 48 (49)

(50)




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S

1 1C8 40.8 pF

R4 13 k 600 kHz= = =

´ ´ p W ´ ´ pƒ

C4 R6 58.3 µF 2.5 mC8 11.2 pF

R4 13 k

´ ´ W= = =

W

P(mod)

1 1C5 6404 pF

2 R4 2 13 k 1912 Hz= = =

´ p ´ ´ ´ p ´ W ´ƒ

CO O O

ps ref ea

2 C V 2 23.9 kHz 58.3 µF 5 VR4 13 k

gm V gm 12 A / V 0.8 V 350 µA / V

æ ö æ ö´ p ´ ´ æ ö´ p ´ ´æ öç ÷= ´ = ´ = Wç ÷ ç ÷ç ÷ç ÷ ´ ´è ø è øè øè ø

ƒ

SCO P(mod)

ƒ 600 kHzƒ ƒ 1912 Hz 23.9 kHz

2 2´

= = ´ =


(51)

To determine the compensation resistor, R4, use Equation 52. Assume the power stage transconductance, gmps,is 12 A/V. The output voltage, VO, reference voltage, Vref, and amplifier transconductance, gmea, are 5 V, 0.8 Vand 350 μA/V, respectively. R4 is calculated to be 13 kΩ which is a standard value. Use Equation 53 to set thecompensation zero to the modulator pole frequency. Equation 53 yields 6404 pF for compensating capacitor C5.6800 pF is used for this design.

(52)

(53)

A compensation pole can be implemented if desired by adding capacitor C8 in parallel with the seriescombination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set thecompensation pole. The selected value of C8 is 39 pF for this design example.

(54)

(55)

9.2.2.11 Discontinuous Conduction Mode and Eco-mode BoundaryWith an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output currentis less than 300 mA. The power supply enters Eco-mode when the output current is lower than 24 mA. The inputcurrent draw is 260 μA with no load.




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Time = 2 µs/div

1A

/div

10

V/d

iv2

0 m

V/d

iv C3: V AC coupledO

C1: V(SW)

C4: IL

C3

C4

C1

Time = 2 µs/div

50

0 m

A/d

iv1

0 V

/div

20

mV

/div C3: V AC coupledO

C1: V(SW)

C4: IL

C3

C4

C1

Time = 2 ms/div

2 V

/div

5 V

/div

1 V

/div C2: V(EN)

C3: VO

C2

C3

C1

C1: VI

Time = 2 ms/div

2 V

/div

2 V

/div

2 V

/div

C3: VO

C2

C3

C1

C2: V(SS/TR)

C4: V(PGOOD)

C1: V(EN)

C4

5 V

/div

Time = 100 µs/div

10

0 m

V/d

iv

C3: V AC coupledO

1A

/div

C4: IO

C4

C3

Time = 5 ms/div

20 m

V/d

iv10 V

/div

V 5-V offsetO

–

VI


9.2.3 Application Curves

Figure 50. Line Transient (8 V to 40 V)Figure 49. Load Transient

Figure 51. Startup With VIN Figure 52. Startup With EN

IO = 3.5 A IO = 100 mA

Figure 53. Output Ripple CCM Figure 54. Output Ripple DCM




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Time = 40 µs/div

2 V

/div

VI

VO

Time = 40 µs/div

2 V

/div

VI

VO

Time = 2 µs/div

50

0 m

A/d

iv1

0 V

/div

20

mV

/div

C3: V AC coupledI

C1: V(SW)

C4: IL

C3

C4

C1

Time = 20 µs/div

20

0 m

A/d

iv2

V/d

iv2

0 m

V/d

iv

C3: V AC coupledO

C1: V(SW)

C4: IL

C3

C4

Time = 2 µs/div

1A

/div

10

V/d

iv2

00

mV

/div

C3: V AC coupledI

C1: V(SW)

C4: IL

C3

C4

C1

Time = 2 ms/div

200 m

A/d

iv10 V

/div

20 m

V/d

iv

C1: V(SW)

C4: IL

C3: V AC coupledO

C3

C4

C1


No Load IO = 3.5 A

Figure 55. Output Ripple PSM Figure 56. Input Ripple CCM

IO = 100 mA VI = 5.5 V No loadVO = 5 V EN floating

Figure 57. Input Ripple DCM Figure 58. Low-Dropout Operation

IO = 100 mA EN floating IO = 1 A EN floating

Figure 59. Low-Dropout Operation Figure 60. Low-Dropout Operation




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Frequency (Hz)

Ga

in (

dB

)

Ph

as

e (q)

10 100 1000 10000 100000

-60 -180

-40 -120

-20 -60

0 0

20 60

40 120

60 180

D036

Gain

Phase

Output Current (A)

Ou

tpu

t V

olt

ag

e D

ev

iati

on

(%

)

0 0.5 1 1.5 2 2.5 3 3.5

-0.1

-0.08

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1

D033

Output Current (A)

Eff

icie

nc

y (

%)

0 0.5 1 1.5 2 2.5 3 3.5

60

65

70

75

80

85

90

95

100

D032

V I = 6 V

V I = 12 V

V I = 24 V

V I = 36 V

V I = 48 V

V I = 60 V

Output Current (A)

Eff

icie

nc

y (

%)

0.001 0.01 0.1 1

0

10

20

30

40

50

60

70

80

90

100

D034

V I = 6 V

V I = 12 V

V I = 24 V

V I = 36 V

V I = 48 V

V I = 60 V

Output Current (A)

Eff

icie

nc

y (

%)

0 0.5 1 1.5 2 2.5 3 3.5

60

65

70

75

80

85

90

95

100

D030

V I = 7 V

V I = 12 V

V I = 24 V

V I = 36 V

V I = 48 V

V I = 60 V

Output Current (A)

Eff

icie

nc

y (

%)

0.001 0.01 0.1 1

0

10

20

30

40

50

60

70

80

90

100

D031

V I = 7 V

V I = 12 V

V I = 24 V

V I = 36 V

V I = 48 V

V I = 60 V


VO = 5 V ƒS = 600 kHz VO = 5 V ƒS = 600 kHz

Figure 61. Efficiency Versus Load Current Figure 62. Light-Load Efficiency

VO = 3.3 V ƒS = 600 kHz VO = 3.3 V ƒS = 600 kHz

Figure 63. Efficiency Versus Load Current Figure 64. Light-Load Efficiency

VO = 5 V ƒS = 600 kHz IO = 3.5 A VO = 5 V ƒS = 600 kHz VI = 12 VVI = 12 V

Figure 65. Overall Loop-Frequency Response Figure 66. Regulation Versus Load Current




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Input Voltage (V)

Ou

tpu

t V

olt

ag

e D

ev

iati

on

(%

)

0 10 20 30 40 50 60

-0.1

-0.08

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1

D035


VO = 5 V ƒS = 600 kHz IO = 1.75 A

Figure 67. Regulation Versus Input Voltage

10 Power Supply Recommendation

The device is designed to operate from an input voltage supply range between 4.5 V and 60 V. This input supplyshould be well regulated. If the input supply is located more than a few inches from the TPS54361-Q1 converteradditional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolyticcapacitor with a value of 100 μF is a typical choice.

11 Layout

11.1 Layout GuidelinesLayout is a critical portion of good power supply design. There are several signal paths that conduct fastchanging currents or voltages that can interact with stray inductance or parasitic capacitance to generate noiseor degrade performance. See Figure 68 for a PCB layout example.• To reduce parasitic effects, the VIN pin should be bypassed to ground with a low ESR ceramic bypass

capacitor with X5R or X7R dielectric.• Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and

the anode of the catch diode. The SW pin should be routed to the cathode of the catch diode and to theoutput inductor. Since the SW connection is the switching node, the catch diode and output inductor shouldbe located close to the SW pins, and the area of the PCB conductor minimized to prevent excessivecapacitive coupling.

• The GND pin should be tied directly to the power pad under the IC and the PowerPAD. The PowerPADshould be connected to internal PCB ground planes using multiple vias directly under the IC.

• For operation at full rated load, the top side ground area must provide adequate heat dissipating area.• The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and

routed with minimal lengths of trace.• The additional external components can be placed approximately as shown.• It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has

been shown to produce good results and is meant as a guideline.

Boxing in the components in the design of Figure 48 the estimated printed circuit board surface area is 1.025 in2

(661 mm2). This area does not include test points or connectors. If the area needs to be reduced, this can bedone by using a two sided assembly and replacing the 0603 sized passives with a smaller sized equivalent.




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( ) ( )2 2O

CON O DS onI

V 5 VP I r 3.5 A 87 m 0.45 W

V 12 V

æ ö= ´ ´ = ´ W ´ =ç ÷

è ø


Layout Guidelines (continued)11.1.1 Power Dissipation EstimateThe following formulas show how to estimate the TPS54361-Q1 power dissipation under continuous conductionmode (CCM) operation. These equations must not be used if the device is operating in discontinuous conductionmode (DCM).

The power dissipation of the IC includes conduction loss (PCON), switching loss E, gate drive loss (Pg) and supplycurrent (PQ). Example calculations are shown with the 12-V typical input voltage of the design example.1. Conduction loss

where• IO is the output current (A)• rDS(on) is the on-resistance of the high-side MOSFET (Ω)• VO is the output voltage (V)• V(VIN) is the input voltage (V) (56)

2. Switching loss:E = VI × ƒS × IO × tr = 12 V × 600 kHz × 3.5 A × 4.9 ns = 0.123 A

where• E is the switching loss• ƒS is the switching frequency (Hz)• tr is the SW pin voltage rise time and can be estimated by trise = V(VIN) × 0.16 ns/V + 3 ns (57)

3. Gate charge loss:PG = V(VIN) × Qg × ƒS = 12 V × 3 nC × 600 kHz = 0.022 W

where• Qg is the total gate charge of the internal MOSFET (58)

4. Quiescent current loss:PQ = V(VIN) × IQ = 12 V × 152 µA = 0.0018 W

where• IQ is the operating nonswitching supply current (59)

Therefore,Ptot = PCON + E + PG + PQ = 0.45 W + 0.123 W + 0.022 W + 0.0018 W = 0.597 W (60)

For given TA:TJ = TA + Rth × Ptot

where• TA is the ambient temperature (°C)• TJ is the junction temperature (°C)• Ptot is the total device power dissipation (W)• Rth is the thermal resistance of the package (°C/W) (61)

For given TJmax = 150°C:TAmax = TJmax – Rth × Ptot

where• TJmax is maximum junction temperature (°C)• TAmax is maximum ambient temperature (°C) (62)

Additional power losses occur in the regulator circuit because of the inductor AC and DC losses, the catch diode,and PCB trace resistance impacting the overall efficiency of the regulator.




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BOOT

VIN

EN

RT/CLK

SW

GND

COMP

FB

Input

Bypass

Capacitor

UVLO

Adjust

Resistors

Frequency

Set Resistor

Compensation

NetworkResistor

Divider

Output

Inductor

Output

Capacitor

VO

VI

TopsideGround

AreaCatch

Diode

Route Boot CapacitorTrace on another layer toprovide wide path fortopside ground

Thermal VIA

Signal VIA

SS/TR

PWRGD

Soft-Start

Capacitor


11.2 Layout Example

Figure 68. PCB Layout Example




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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development SupportFor the TPS54360 and TPS54361 Family Design Excel Tool, see SLVC452

12.2 Documentation Support

12.2.1 Related DocumentationFor related documentation see the following:• Create an Inverting Power Supply From a Step-Down Regulator, SLVA317• Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, SLVA369• Evaluation Module for the TPS54361 Step-Down Converter, SLVU922

12.3 TrademarksEco-mode, PowerPAD, WEBENCH are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.




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PACKAGE OPTION ADDENDUM

www.ti.com 17-May-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS54361QDPRRQ1 ACTIVE WSON DPR 10 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54361Q

TPS54361QDPRTQ1 ACTIVE WSON DPR 10 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS54361Q

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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PACKAGE OPTION ADDENDUM

www.ti.com 17-May-2014

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS54361-Q1 :

• Catalog: TPS54361

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS54361QDPRRQ1 WSON DPR 10 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

TPS54361QDPRTQ1 WSON DPR 10 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2014

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS54361QDPRRQ1 WSON DPR 10 3000 367.0 367.0 35.0

TPS54361QDPRTQ1 WSON DPR 10 250 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.Products ApplicationsAudio www.ti.com/audio Automotive and Transportation www.ti.com/automotiveAmplifiers amplifier.ti.com Communications and Telecom www.ti.com/communicationsData Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computersDLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-appsDSP dsp.ti.com Energy and Lighting www.ti.com/energyClocks and Timers www.ti.com/clocks Industrial www.ti.com/industrialInterface interface.ti.com Medical www.ti.com/medicalLogic logic.ti.com Security www.ti.com/securityPower Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defenseMicrocontrollers microcontroller.ti.com Video and Imaging www.ti.com/videoRFID www.ti-rfid.comOMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.comWireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2014, Texas Instruments Incorporated

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tps54361-q1

Documents

v industrial

khz36 v

v input

range device information1

pin son

device temperature grade

high efficiency

shutdown supply current