tpg_PRESTO.docx

Topic: Design and implementation of low power Deterministic Random bit generator with high throughput compression

capabilities using BIST.

ABSTRACT:

This paper deals with the design of the low power deterministic random bit generator capable of producing pseudo random patterns with desired toggling levels and enhanced fault coverage gradient using BIST based DSBG. We introduce a method automatically select several controls of the generator allowing for easy precise tuning. Similar Techniques subsequently are employed to reduce the overhead control points are shared when possible and a condensation network is used with the observation points. The Prosed design aims at to design and implement a TPG for Memory applications. The Experimental results are presented which indicate that pseudo-random testability can be achieved with small area overheads using simple techniques also how the test pattern scan will affect the read and write cycle of the memory have been presented.

Proposed Design Features:

The main aim of the design is to use the generated DSBG for memory applications In this design we utilize the existing designed systems for purpose of specific

application based oriented design as memories. This design comprises of the TPG unit and also the Memory module i.e. controller as

well as memory units for the correct response of the real time parameters such as (Speed, Power, Delay… etc…).

We have proposed a FSM model based Controller design for the memory unit, which controls the both the test pattern generator as well.

Figure1: Representing Existing Test Pattern

Figure2: The Simplest Design of the Memory (64 bit)

Software Used:

HDL designer Series Model Simulator Precision synthesis

Literature Survey:

Introduction:

Various forms of embedded test are increasingly viewed as essential to reduce test cost. Among them, scan testing has gained broad acceptance as a reliable solution. However, due to the high data activity associated with scan-based test operations, a circuit under test can dissipate much more power than it was designed to function under. With overstressing devices beyond the mission mode, reductions in the operating power of ICs in a test mode have been of concern for years. A full-toggle scan pattern may draw several times the typical functional mode power, and this trend continues to rise, particularly over the mission mode’s peak power. This power-induced over-test may result in thermal issues, voltage noise, power droop, or excessive peak power over multiple cycles which, in turn, cause a yield loss due to instant device damage, severe decrease in chip reliability, shorter product lifetime, or a device malfunction because of timing failures following a significant circuit delay increase, for example. Abnormal switching activity may also cause fully functional chips to fail during testing because of phenomena such as IR-drop, crosstalk, or di/dt problem. Numerous schemes for power reduction during scan testing have been devised [8]. Among them there are solutions specifically proposed for built-in self-test (BIST) to keep the average and peak power below a given threshold. For example, the test power can be reduced by preventing transitions at memory elements from propagating to combinational logic during scan shift. This is achieved by inserting gating logic between scan cell outputs and logic they drive [4], [9]. During normal operations and capture, this logic remains transparent. Gated scan cells are also proposed in [2] and [20]. A synergistic test power reduction method of [21] uses

available on-chip clock gating circuitry to selectively block scan chains while employing test scheduling and planning to further decrease BIST power in the Cell processor. A test vector inhibiting scheme of [5] masks test patterns generated by an LFSR as not all produced vectors, often very lengthy, detect faults. Elimination of such tests can reduce switching activity with no impact on fault coverage. The advent of low-transition test pattern generators has added a new dimension to power aware BIST solutions [3], [11], [15]. A device presented in [19] is comprised of an LFSR feeding scan chains through biasing logic and T-type flip-flop. Since this flip-flop holds the previous value until its input is asserted, the same value is repeatedly scanned into scan chains until the value at the output of biasing logic (e.g., a k-input AND gate) becomes 1. Depending on k, one can significantly reduce the number of transitions occurring at the scan chain inputs. A dual-speed LFSR of [18] consists of two LFSRs driven by normal and slow clocks, respectively. The switching activity is reduced at the circuit inputs connected to the slow-speed LFSR, while the whole scheme still ensures satisfactory fault coverage. Mask patterns are used in [14] to mitigate the switching activity in LFSRproduced patterns, whereas a bit swapping of [1] achieves the same goal at the primary inputs of CUT. A gated LFSR clock of [6] allows one to activate only half of LFSR stages at a time, thus reducing power consumption, as only half of the circuit inputs change every cycle. A scheme that combines the low transition generator of [19] (handling easy-todetect faults) with a 3-weight PRPG (deployed to detect random pattern resistant faults) can also be used to reduce switching activity during BIST, as demonstrated in [17]. The schemes of [10], [13], and [16] suppress transitions in LFSR generated sequences by either statistical monitoring or injecting intermediate and highly correlated patterns. Finally, a random single-input change generator can produce low power patterns in a parallel BIST environment, as shown in [7]. As the BIST power consumption can easily exceed the maximum ratings when testing at speed, scan patterns must be shifted at a programmable low speed, and only the last few cycles and the capture cycle are applied at the maximum frequency. In the burst-mode approach presented in [12], typically five consecutive clock cycles are used. The first

four cycles serve shifting purposes, whereas the last one is designated for capture. The objective is to stabilize the power supply before the last shift and capture pulses are applied, which are critical for at-speed tests. To reduce the voltage droop related to a higher circuit activity, a burst clock controller slows down some of the shift cycles. It allows a gradual increase of the circuit activity, thereby reducing the di/dt effect. The controller can gate the shift clocks, depending on the needs for gradual warming up of the circuit. In this paper, we propose a new pseudorandom test pattern generator (PRPG) for low power BIST applications. The generator is aimed at reducing the switching activity during scan loading due to its preselected toggling (PRESTO) levels. It can assume a variety of configurations that allow a given scan chain to be driven either by PRPG itself or by a constant value fixed for a given period of time. The PRESTO generator allows loading scan chains with patterns having low transition counts, and thus significantly reduced power dissipation.

II. BASIC ARCHITECTURE

Figure 1 illustrates the basic structure of a PRESTO generator. It consists of an n-bit conventional PRPG connected with a phase shifter feeding scan chains. Linear feedback shift register or a ring generator can implement PRPG. More importantly, however, n hold latches are placed between the PRPG and the phase shifter. Each hold latch is individually controlled through a corresponding stage of an n-bit shift register. As long as its enable input is asserted, the given latch is transparent for data going from the PRPG to the phase shifter, and it is said to be in the toggle mode. When the latch is disabled, it captures and saves, for a number of clock cycles, the corresponding bit of PRPG, thus feeding the phase shifter (and possibly certain scan chains) with a constant value. Now, it is in the hold mode. It is worth notingthat each phase shifter output is obtained by XOR-ing outputs of three different hold registers. Thus, every scan chain remains in a low-power mode provided only disabled hold latches drive the corresponding phase shifter output. As mentioned above, the shift register controls the hold latches. Its content comprises 0s and 1s shifted-in one bit per test pattern. The 1s indicate latches in the toggle mode and thus transparent for data arriving from the PRPG. Their fraction determines a scan switching activity. Yet one should recall that only scan chains driven exclusively through disabled hold latches will receive constant values. The enable signals stored in the shift register are produced in a probabilistic fashion. The scheme of Fig. 1 uses the PRPG with a programmable set of weights to output weighted pseudorandom samples. The weights are determined by four AND gates producing a logical 1 with the probability of 0.5, 0.25, 0.125, and 0.0625, respectively. The OR gate allows choosing probabilities beyond simple powers of 2. A 4-bit register Switching is employed to activate AND gates, and allows selecting a user-defined level of desired switching activity.

For example, if one enters the switching code 0100, then, on the average, 25% of the shift register stages will be set to 1, and thus 25% of hold latches will be enabled. Given the phase shifter architecture, one can assess then the amount of scan chains receiving constant values, and thus the expected toggling ratio. An additional 4-input NOR gate (in gray) detects the switching code 0000, which is used to switch the low power functionality off. The content of the shift register can also be selected in a deterministic manner due to a multiplexer placed in the front of the serial input of the register. It is worth noting that when working in the weighted random mode, the switching level selector ensures statistically stable content of the shift register in terms of the amount of 1s it carries. As a result, roughly the same fraction of scan chains will stay in the low power mode, though a set of actual low toggling chains will keep changing from one test pattern to another. It will correspond to a certain level of toggling in the scan chains. With only 15 different switching codes, however, the available toggling granularity may render this solution too coarse to be always acceptable. The next section presents additional features that make the PRESTO generator fully operational in a wide range of desired switching rates.

III. FULLY OPERATIONAL GENERATOR

Much higher flexibility in forming low-toggling test patterns can be achieved by deploying a scheme presented in Fig. 2. Essentially, while preserving the operational principles of the basic solution, this approach splits up a shifting period of every test pattern into a sequence of alternating hold and toggle intervals. To move the generator back and forth between these two states, we use a basic T-type flipflop that switches whenever there is a 1 on its data input. If it is set to 0, the generator enters the hold period with all latches temporarily disabled regardless of the shift register content. This property can be crucial in SoC designs where only a single scan chain crosses a given core, and its abnormal toggling may cause locally unacceptable heat dissipation that can only be reduced due to temporary hold periods. To make it work, it first requires placing AND gates on the shift register outputs to allow freezing of all phase shifter inputs. If the T flip-flop is set to 1 (the toggle period), then the latches enabled through the shift register can pass test data moving from the PRPG to the scan chains. How long it takes to stay either in the hold mode or in the toggle mode is decided by two additional user-defined parameters kept in 3-bit Hold and Toggle registers, respectively. In order to terminate either mode, a 1 must occur on the T flip-flop input.

This weighted pseudorandom signal is produced by a module Encoder H/T based on the content of seven different stages of the original PRPG, as shown in Fig. 3. Depending on the control code provided by either the Toggle register or the Hold register, the encoder output can be asserted with the probability ranging from 2–1 to 2–7. Moreover, the control code 000 causes the encoder to assume the high output unconditionally. This property can be used to terminate deterministically a given period (hold or toggle) within a single clock cycle.

ABOUT VERILOG HDL

Verilog HDL is a hardware description language that can be used to model a digital

system at many levels of abstraction ranging from the algorithmic-level to the gate-level to

the switch-level. The complexity of the digital system being modeled could vary from that of

a simple gate to a complete electronic digital system, or anything in between. The digital

system can be described hierarchically and timing can be explicitly modeled within the same

description.

Verilog capabilities

The Verilog HDL language includes capabilities to describe the behavior-al nature of a

design, the dataflow nature of a design, a design's structural composition, delays and a

waveform generation mechanism including aspects of response monitoring and verification,

all modeled using one single language. In addition, the language provides a programming

language interface through which the internals of a design can be accessed during simulation

including the control of a simulation run.

The language not only defines the syntax but also defines very clear simulation

semantics for each language construct. Therefore, models written in this language can be

verified using a Verilog simulator. The language inherits many of its operator symbols and

constructs from the C programming language. Verilog HDL provides an extensive range of

modeling capabilities, some of which are quite difficult to comprehend initially. However, a

core subset of the language is quite easy to leam and use. This is sufficient to model most

applications. The complete language, however, has sufficient capabilities to capture the

descriptions from the most complex chips to a complete electronic system.

HISTORY

The verilog HDL language was first developed by Gateway Design Automation in

1983 as hardware are modleling language for their simulator product, At that time ,twas a

propnetary language. Because of the popularity of the,simulator product, Verilog HDL gained

acceptance as a usable and practical language by a number of designers. In an effort to

increase the popularity of the language, the language was placed in the public domain in

1990. Open verilog International (OVI) was formed to promote Verilog. In 1992 OVI

decided to pursue standardization of verilog HDL as an IEEE standard. This effort was

succeful and the language became an IEEE standard in 1995. The complete standard is

described in the verilog hardware description language reference manual. The standard is

called std 1364-1995.

MAJOR CAPABILITIES

Listed below are the majort capabilities of the verilog hardware description

Primitive logic gates, such as and, or and nand, are built-in into the language.

Flexibility of creating a user-defined primitive (UDP). Such a primitive could either

be a combinational logic primitive or a sequential logic primitive.

Switch-level modeling primitive gates, such as pmos and nmos, are also built-in into

the language.

Explicit language constructs are provided for specifying pin-to-pin delays, path delays

and timing checks of a design.

A design can be modeled in three different styles or in a mixed style. These styles are:

behavioral style - modeled using procedur-al constructs; dataflow style - modeled

using continuous assign-ments; and structural style - modeled using gate and module

instantiations.

There are two data types in Verilog HDL; the net data type and the register data type.

The net type represents a physical connection between structural elements while a

register type represents an abstract data storage element.

Hierarchical designs can be described, up to any level, using the module instantiation

construct.

A design can be of arbitrary size; the language does not impose a limit.

Verilog HDL is non-proprietary and is an IEEE standard.

It is human and machine readable. Thus it can be used as an ex-change language

between tools and designers.

The capabilities of the Verilog HDL language can be further extended by using the

programming language interface (PLI) mechanism. PLI is a collection of routines that

allow foreign functions to access information within a Verilog module and allows for

de-signer interaction with the simulator.

A design can be described in a wide range of levels, ranging from switch-level, gate-

level, register-transfer-level (RTL) to algorithmic-level, including process and

queuing-level.

A design can be modeled entirely at the switch-level using the built-in switch-level

primitives.

The same single language can be used to generate stimulus for the design and for

specifying test constraints, such as specifying the values of inputs.

Verilog HDL can be used to perform response monitoring of the design under test,

that is, the values of a design under test can be monitored and displayed. These values

can also be compared with expected values, and in case of a mismatch, a report

message can be printed.

At the behavioral-level, Verilog HDL can be used to describe a design not only at the

RTL-level, but also at the architectural-level and its algorithmic-level behavior.

At the structural-level, gate and module instantiations can be used.

Figure 5.1 shows the mixed-level modeling capability of Verilog HDL, that is, in one

design, each module may be modeled at a different level.

Verilog HDL also has built-in logic functions such as & (bitwise-and) and I (bitwise-

or).

High-level programming language constructs such as condition- als, case statements,

and loops are available in the language.

Notion of concurrency and time can be explicitly modeled.

Powerful file read and write capabilities fare provided.

Fig 5.1 Mixed level modelling

The language is non-deterministic under certain situations, that is, a model may

produce different results on different simulators; for example, the ordering of events

on an event queue is not defined by the standard.

ABOUT SYNTHESIS

Synthesis is the process of constructing a gate level netlist from a register-transfer

level model of a circuit described in Verilog HDL. Figure 5.2 shows such a process. A

synthesis system may as an intermediate step, generate a netlist that is comprised of register-

transfer level blocks such as flip-flops, arithmetic-logic-units, and multiplexers,

interconnected

by wires. In such a case, a second program called the RTL module builder is

necessary. The purpose of this builder is to build, or acquire from a library of predefined

components, each of the required RTL blocks in the user-specified target technology.

Having produced a gate level netlist, a logic optimizer reads in the netlist and

optimizes the circuit for the user-specified area and timing constraints. These area and timing

Fig 5.2 The Synthesis Process

constraints may also be used by the module builder for appropriate selection or generation of

RTL blocks. In this book, we assume that the target netlist is at the gate level. The logic gates

used in the synthesized netlists are described in Appendix B. The module building, and logic

optimization phases are not described in this book.

Figure 5.2 shows the basic elements of Verilog HDL and the elements used in hardware. A

mapping mechanism or a construction mechanism has to be provided that translates the

Verilog HDL elements into their corresponding hardware elements.

Fig 5.3 Two words of Synthesis

SYNTHESIS IN A DESIGN PROCESS

Verilog HDL is a hardware description language that allows a designer to model a

circuit at different levels of abstraction, ranging from the gate level, register-transfer level,

behavioral level to the algorithmic level. Thus a circuit can be described in many different

ways, not all of which may be synthesizable/Compounding this is the fact that Verilog HDL

was designed primarily as a simulation language and not as a language for synthesis.

Consequently, there are many constructs in Verilog HDL that have no hardware counterpart,

for example, the $display system call. Also there is no standardized subset of Verilog HDL

for register-transfer level synthesis.

Because of these problems, different synthesis systems support different Verilog HDL

subsets for synthesis. Since there is no single object in Verilog HDL that means a latch or a

flip-flop, each synthesis system may provide different mechanisms to model a flip-flop or a

latch. Each synthesis system therefore defines its own subset of Verilog HDL including its

own modeling style.

Figure 5.4 shows a circuit that is described in many different ways using Verilog

HDL. A synthesis system that supports synthesis of styles A and B may not support that of

style C. This implies that typically synthesis models are non-portable across different

synthesis models are non-portable across different synthesis systems. Style D may not be

synth & sizable at all.

Fig 5.5Typical design process

This limitation creates a severe handicap because now the designer not only has to

understand Verilog HDL, but also has to understand the synthesis-specific modeling style

before a synihcsizable model can be written. The typical design process shown in Figure 5.4

can not always be followed for Veri!og HDL synthesis.

Fig 5.4 Same behavior, Different styles