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TPD4E6B06SLVSCK3 MAY 2014

TPD4E6B06 4-CH Bidirectional Low Capacitance ESD Protection Device With 15 kVContact and Ultra Low Clamping Voltage

1 Features 3 DescriptionThe TPD4E6B06 is a four channel Electrostatic

1 IEC 61000-4-2 Level 4Discharge (ESD) Protection device in an ultra small 15 kV (Contact Discharge) DPW package. It is the industrys smallest 4-CH

15 kV (Air Gap Discharge) Transient Voltage Suppressor (TVS) diode with a0.48-mm pitch. This larger pitch helps save on printed IEC 61000-4-5 (Surge): 3 A (8/20 s)circuit board (PCB) manufacturing costs. The device IO Capacitance: 4.8 pF (Typ) provides IEC61000-4-2 compliance up to 15kV

RDYN: 0.75 (Typ) contact discharge. It has an ESD clamp circuit withback-to-back diodes for bipolar/bidirectional signal DC Breakdown Voltage: 6 V (Min)support. The 4.8-pF (Typ) line capacitance is suitable Ultra Low Leakage Current: 100 nA (Max)for a wide range of applications supporting data rates

Clamping Voltage: 10 V (Max at IPP = 1 A) up to 700 MHz. Industrial Temperature Range: 40C to 125C

Device Information(1) Space Saving DPW Package (0.8 mm x 0.8 mm)PART NUMBER PACKAGE BODY SIZE (NOM)

2 Applications TPD4E6B06 X2SON (4) 0.80 mm 0.80 mm(1) For all available packages, see the orderable addendum at Audio Lines

the end of the datasheet. Microphone Earphone Speakerphone

SD Interface SIM Interface Mobile Keyboard or Other Buttons Cell Phones eBook Portable Media Players Digital Camera Tablet PC Wearables

4 Simplified Schematic

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPD4E6B06SLVSCK3 MAY 2014 www.ti.com

Table of Contents8.2 Functional Block Diagram ......................................... 71 Features .................................................................. 18.3 Feature Description................................................... 72 Applications ........................................................... 18.4 Device Functional Modes.......................................... 83 Description ............................................................. 1

9 Application and Implementation .......................... 84 Simplified Schematic............................................. 19.1 Application Information.............................................. 85 Revision History..................................................... 29.2 Typical Application ................................................... 86 Pin Configuration and Functions ......................... 3

10 Layout................................................................... 107 Specifications......................................................... 310.1 Layout Guidelines ................................................. 107.1 Absolute Maximum Ratings ...................................... 310.2 Layout Examples................................................... 107.2 Handling Ratings....................................................... 3

11 Device and Documentation Support ................. 117.3 Recommended Operating Conditions....................... 411.1 Trademarks ........................................................... 117.4 Thermal Information .................................................. 411.2 Electrostatic Discharge Caution............................ 117.5 Electrical Characteristics........................................... 411.3 Glossary ................................................................ 117.6 Typical Characteristics .............................................. 5

12 Mechanical, Packaging, and Orderable8 Detailed Description .............................................. 7 Information ........................................................... 118.1 Overview ................................................................... 7

5 Revision History

DATE REVISION NOTESMay 2014 * Initial release.

2 Submit Documentation Feedback Copyright 2014, Texas Instruments Incorporated

Product Folder Links: TPD4E6B06

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TPD4E6B06www.ti.com SLVSCK3 MAY 2014

6 Pin Configuration and Functions

5 Terminal X2SON (DPW) Package0.8 mm 0.8 mm(Bottom View)

Pin FunctionsPIN TYPE DESCRIPTION

NAME NOIO1 1 IO ESD protected lineIO2 2 IO ESD protected lineIO3 3 IO ESD protected lineIO4 4 IO ESD protected lineGND 5 G Ground

7 Specifications

7.1 Absolute Maximum Ratings (1) (2)over operating free-air temperature range (unless otherwise noted)

MIN MAX UNITOperating Temperature -40 125 C

IEC 61000-4-5 Current (tp 8/20 s) (3) 3 APeak Pulse

IEC 61000-4-5 Power (tp 8/20 s) (3) 40 W

(1) Absolute maximum ratings apply over recommended junction temperature range.(2) Voltages are with respect to GND unless otherwise noted.(3) Measured at 25C

7.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range 65 155 CHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2 2 kVpins (1)

V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification 500 500 VJESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as 2 kVmay actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 500 Vmay actually have higher performance.

Copyright 2014, Texas Instruments Incorporated Submit Documentation Feedback 3



7.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN MAX UNITVIO Input pin voltage 5.5 5.5 VTA Operating free-air temperature 40 125 C

7.4 Thermal InformationTPD4E6B06

THERMAL METRIC (1) DPW UNIT5 PINS

RJA Junction-to-ambient thermal resistance 291.8RJC(top) Junction-to-case (top) thermal resistance 224.2RJB Junction-to-board thermal resistance 245.8 C/WJT Junction-to-top characterization parameter 31.4JB Junction-to-board characterization parameter 245.6RJC(bot) Junction-to-case (bottom) thermal resistance 195.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical CharacteristicsTA = 40C to 125C (unless otherwise specified)

PARAMETER TEST CONDITION MIN TYP MAX UNITVRWM Reverse stand-off voltage IIO = 10 A 5.5 5.5 VVBRF Break-down voltage IIO to GND = 1 mA 6 VVBRR Break-down voltage IGND to IO = 1 mA 6 VILEAK Leakage current VIO = 5 V 100 nA

I = 1 A, IO to GND, 8/20 s (1) 10 VI = 5 A, IO to GND, 8/20 s (1) 13 V

VCLAMP Clamp voltage with ESD strike I = 1 A, IO to GND, 8/20 ss (1) 9 VI = 5 A, IO to GND, 8/20 s (1) 13 VAny IO to GND Pin (2) 0.75

RDYN Dynamic resistance GND to any IO Pin (2) 0.65 CL IO Capacitance VIO = 2.5 V 4.8 7 pF

(1) Non-repetitive current pulse 8/20 us exponentially decaying waveform according to IEC61000-4-5(2) Extraction of RDYN using least squares fit of TLP characteristics between I = 10 A and I =20 A



0.00100.00080.00060.00040.0002

0.00000.00020.00040.00060.00080.0010

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7.6 Typical Characteristics

Figure 1. IEC 61000-4-2 Clamping Voltage, +8kV Contact Figure 2. IEC 61000-4-2 Clamping Voltage, -8kV Contact

Figure 3. TLP, tPW = 100nS, tRISE = 10nS, IO to GND Figure 4. TLP, tPW = 100nS, tRISE = 10nS, GND to IO

Figure 6. Surge Curves, IO to GNDFigure 5. IV Curve



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Typical Characteristics (continued)

Figure 7. Surge Curves, GND to IO Figure 8. Capacitance

Figure 9. Insertion Loss



IO1 IO2 IO3 IO4

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8 Detailed Description

8.1 OverviewThe TPD4E6B06 is a four channel ESD Protection device in an ultra small DPW package. It is the industryssmallest 4-CH ESD protection device with 0.48-mm pitch. This larger pitch helps save on PCB manufacturingcosts. The device provides IEC61000-4-2 compliance up to 15-kV contact discharge. It has an ESD clamp circuitwith back-to-back diodes for bipolar/bidirectional signal support. The 4.8-pF (Typ) line capacitance is suitable fora wide range of applications supporting frequencies up to 700 MHz.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 IEC 61000-4-2 Level 2 ESD ProtectionThe IO pins can withstand ESD events up to 15 kV contact and 15 kV air. An ESD/surge clamp diverts thecurrent to ground.

8.3.2 IEC 61000-4-5 Surge ProtectionThe IO pins can withstand surge events up to 3 A and 40 W (8/20 s waveform). An ESD/surge clamp divertsthis current to ground.

8.3.3 IO CapacitanceThe capacitance between any IO pin to ground is 4.8 pF (Typ). This capacitance supports frequencies up to 700MHz.

8.3.4 RDYNThe low RDYN of 0.75 (Typ) allows for lower clamping voltages.

8.3.5 DC Breakdown VoltageThe DC breakdown voltage of any IO pin is a minimum of 6 V. This ensures that sensitive equipment isprotected from surges above the reverse standoff voltage of 5.5 V (Min).

8.3.6 Ultra Low Leakage CurrentThe IO pins feature an ultra-low leakage current of 100 nA (Max) with a bias of 2.5 V.



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Feature Description (continued)8.3.7 Clamping VoltageThe IO pins feature an ESD clamp capable of clamping the voltage to 10 V (IO to GND) or 9 V (GND to IO) ofIEC61000-4-5 surge when IPP = 1 A.

8.3.8 Industrial Temperature RangeThis device features an industrial operating range of 40 C to 125 C.

8.3.9 Space Saving DPW PackageThe small 0.8 mm x 0.8 mm package size saves board space and makes it easy to add ESD protection.

8.4 Device Functional ModesTPD4E6B06 is a passive integrated circuit that triggers when voltages are above VBRF or VBRR. During ESDevents, voltages as high as 15 kV (air) can be directed to ground via the internal diode network. Once thevoltages on the protected line fall below the trigger levels of TPD4E6B06 (usually within 10s of nano-seconds)the device reverts to passive.

9 Application and Implementation

9.1 Application InformationTPD4E6B06 is a diode array type TVS. These low capacitance types of TVSs are typically used to provide apath to ground for dissipating ESD events on hi speed signal lines between a human interface connector and asystem. During high voltage ESD strikes, the device clamps to a safe voltage level to protect the system.

The typical application of the TPD4E6B06 is to be placed in between the connector and the system. The lowcapacitance of the TPD4E6B06 gives flexibility in the end application, as it can be used on many different highspeed interfaces.

9.2 Typical Application

Figure 10. Protecting Data Lines

9.2.1 Design Requirements

Table 1. Design ParametersDESIGN PARAMETER EXAMPLE VALUE

Signal range on Data Lines 5.5 V to 5.5 VOperating Frequency Up to 700 MHz



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9.2.2 Detailed Design ProcedureThe designer needs to know the following:

Signal range on all the protected lines Operating frequency

9.2.2.1 Signal RangeTPD4E6B06 has 4 protection channels for signal lines. Any I/O will support a signal range of 5.5 V to 5.5 V.

9.2.2.2 Operating FrequencyThe TPD4E6B06 has 4.8 pF of capacitance (Typ), supporting up to 700 MHz frequencies.

9.2.3 Application Curves

Figure 11. Insertion Loss (Any IO to GND)



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10 Layout

10.1 Layout Guidelines Place the device as close to the connector as possible.

EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,resulting in early system failures.

The PCB designer should minimize the possibility of EMI coupling by keeping any unprotected tracesaway from the protected traces which are between the TVS and the connector.

Route the protected traces as straight as possible. Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded

corners with the largest radii possible. Electric fields tend to build up on corners, increasing EMI coupling.

10.2 Layout Examples

Figure 12. Single Layer Routing

Figure 13. Double Layer Routing




11 Device and Documentation Support

11.1 TrademarksAll trademarks are the property of their respective owners.

11.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.3 GlossarySLYZ022 TI Glossary.

This glossary lists and explains terms, acronyms and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.



PACKAGE OPTION ADDENDUM

www.ti.com 21-Apr-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (C) Device Marking(4/5)

Samples

TPD4E6B06DPWR ACTIVE X2SON DPW 4 3000 Green (RoHS& no Sb/Br)

CU NIPDAU | Call TI Level-1-260C-UNLIM -40 to 125 B1

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 21-Apr-2015

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominalDevice Package

TypePackageDrawing

Pins SPQ ReelDiameter

(mm)Reel

WidthW1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPD4E6B06DPWR X2SON DPW 4 3000 180.0 9.5 0.94 0.94 0.5 2.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Sep-2014

Pack Materials-Page 1

*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPD4E6B06DPWR X2SON DPW 4 3000 184.0 184.0 19.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Sep-2014

Pack Materials-Page 2

IMPORTANT NOTICE

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright 2015, Texas Instruments Incorporated

1Features2Applications3Description4Simplified SchematicTable of Contents5Revision History6Pin Configuration and Functions7Specifications7.1Absolute Maximum Ratings7.2Handling Ratings7.3Recommended Operating Conditions7.4Thermal Information7.5Electrical Characteristics7.6Typical Characteristics

8Detailed Description8.1Overview8.2Functional Block Diagram8.3Feature Description8.3.1IEC 61000-4-2 Level 2 ESD Protection8.3.2IEC 61000-4-5 Surge Protection8.3.3IO Capacitance8.3.4RDYN8.3.5DC Breakdown Voltage8.3.6Ultra Low Leakage Current8.3.7Clamping Voltage8.3.8Industrial Temperature Range8.3.9Space Saving DPW Package

8.4Device Functional Modes

9Application and Implementation9.1Application Information9.2Typical Application9.2.1Design Requirements9.2.2Detailed Design Procedure9.2.3Application Curves

10Layout10.1Layout Guidelines10.2Layout Examples

11Device and Documentation Support11.1Trademarks11.2Electrostatic Discharge Caution11.3Glossary

12Mechanical, Packaging, and Orderable Information