Torino analogue Front-End - Agenda INFN

Torino analogue Front-End: IP integration and analogue top-level considerations for the demonstrator

CHIPIX General Meeting

Luca Pacher

August 31, 2015

Outline

- Integration of the analogue front-end as an IP macro into a DoT flow (Verilog description, top-level power and bias distribution, abstract generation, power and timing characterization)

- 35um x 35um floorplan and top-level considerations for the CHIPIX demonstrator

- Refresh on Torino synchronous front-end architecture

- Open issues and question marks: substrate biasing, isolation strategy between analogue and digital domains, common interfaces

[email protected] 2 / 46 August 31, 2015

Torino Front-End Architecture /1


- CSA with Krummenacher feedback → triangular signal shaping and sensor leakage compensation assured by the same feedback network

- 'digital' test charge injection circuit → DC level with digital control signal

- discrete-time voltage comparator → dynamic track-and-latch architecture

- local threshold adjustment by means of autozeroing (not shown)

- AC coupling between charge integrator/shaper and hit discriminator

- 25fF, 50fF and 100fF shunt capacitors to emulate different sensor capacitances

- asynchronous digital control logic to support latch operations as a local oscillator

Synchronous Front-End approach /1Implemented latch control logic /1

- use some multiplexing logic to switch between 'slow' operations, 'fast' operations and idle/reset states

- register a single-ended hit pulse from VoutP and VoutN complementary transitions

- insert a variable-delay element in the latch strobe loop to tune the oscillation

Latch/ToT control logic (conceptual schematic)

Torino Front-End Architecture /2


Performance summary

● compact design (no local D/A for threshold adjustement)

- most of area occupied by AC/autozeroing capacitors and test input capacitances

- 26um x 50um total PNR boundary (including test features)

● leakage compensation OK up to 50nA/pixel

● low-power dissipation

- 3.5uA static current (2.5uA CSA + 1uA DISC) and 0.8uA dynamic current (latch)

- 4.5uA/pixel average current consumption, corresponding to 5.2uW/pixel at 1.2V supply

● test results and details extensively presented to RD53 analogue design WG meetings, RD53 general meeting and CMS Phase2 Pixel Electronics meetings

- https://indico.cern.ch/event/382278/- https://indico.cern.ch/event/378099/- https://indico.cern.ch/event/406394/

● fast charge encoding (turn the latch into a voltage-controlled oscillator)

- 8-bit ToT for 30ke in less than 300ns with tunable self-generated clock signals up to 800-900 MHz

● initially underestimated latch offset now fixed in new submitted versions (May 2015)

● low noise

- ENC ~90-100e RMS @ 100fF input capacitance with 20nA feedback current


Synchronous Front-End approach /1New submitted layouts (May 2015)

MOM/MIM/varactors MOM/varactors

- explored different physical implementations for AC-coupling and autozeroing capacitors

- same front-end architecture and 26um x 50um total boundary area

- test results will determine the most promising choice (e.g. radiation tolerance)

- two different schemes to apply discriminator threshold and baseline voltages

MOM-only


Synchronous Front-End approach /1The analogue front-end as an IP macro


- at least a Verilog module with the complete I/O interface → Verilog abstract

● Verilog

- Verilog-AMS model useful, but not indispensable for the moment

● LEF

- physical abstract of the cell layout indispensable for the place-and-route tool

- define all bias and power/ground pins as inout

- define all digital inputs (i.e. configuration bits) as input

- define all digital outputs i.e. DISC output(s) as output

- hit generator (behavioural description) already implemented into the verification environment

- for simulation purposes only, add a real input for the front-end input node

- I/O description must be consistent with Verilog information !

● gds and post-layout extracted netlist

- required to build a detailed power-grid of the macro using Voltus engine for full-chip rail and IR drop analysis on AVDD

● liberty model

- timing information not indispensable... in liberty a front-end is no more than a big inverter !

- static and dynamic power consumption

Synchronous Front-End approach /1Verilog model /1

module AFE( … … … ) ;

`ifdef BEHAVIOURAL // Latch reset and decision, including the strobe-to-VoutP // and strobe-to-VoutN delays (~500 ps from SPICE simulations) // The resulting internal hit is synchronized with the strobe // activity

reg VoutP, VoutN ;

always @(strobe) begin : latch if(strobe == 1'b0) begin VoutP <= #0.5 1'b1 ; VoutN <= #0.5 1'b1 ; end else begin case (pixel_in) 1'b0 : begin VoutP <= #0.5 1'b1 ; VoutN <= #0.5 1'b0 ; end 1'b1 : begin VoutP <= #0.5 1'b0 ; VoutN <= #0.5 1'b1 ; end default : begin VoutP <= #0.5 1'b1 ; VoutN <= #0.5 1'b1 ; end endcase end //if end //always `endif

endmodule : AFE

- latch reset/decision at each strobe cycle modeled in a non- synthesizable portion of code for HDL simulation purposes

- for synthesis and place-and-route purposes a simple Verilog abstract is enough for us

- liberty timing models not yet available but for the moment not indispensable to synthesis (see later)

- latch/ToT control logic already iplemented in both Verilog/VHDL, simulated and synthesized


Synchronous Front-End approach /1Verilog model /2


- fast ToT counting with programmable, self-generated high-frequency clock (BINARY_ONLY = 0, FAST_EN = 1)

- the leading-edge (LE) of the registered hit pulse is always synchronized with strobe

- asynchronous behaviour properly reproduced in HDL simulations

Synthesis (9-tracks STD cells)


syn. latch/ToT controller

Leave the synthesizer to optimize the combinational multiplexing logic from HDL code


Timing validation

Due the asynchronous behaviour of the logic feedback loop built around the latch proper timing must be validated with full-analogue simulations !

Synchronous Front-End approach /1

test-only features now removed (MOM-only version)

26um x 50um 26um x 41um

Abstract generation (LEF) /1Abstract generation /1


Synchronous Front-End approach /1Synchronous Front-End approach /1Abstract generation (LEF) /2

● make a clear separation between top-level routing and local routing

- assume M1-M5 for internal routing

- M7(H) - M8(V) - M9(V) entirely dedicated to analogue power/ground distribution

- reserve M6(V) for bias distribution

● top-level routing and necessary shieldings... then performed by Encounter !!!

Abstract generation /2


● route all input/output digital pins to the edge of the digital interface with easy access to Encounter

- preferably, use M2 - M3 for pins

● top-level routing redesigned, bottom layout unchanged

Synchronous Front-End approach /1Abstract generation (LEF) /3

M8

(V

) 5

um

M

8 (V

) 5

um

A

VD

D

A

VS

S

M

6 (

V)

0.5

um

M7 (H) 0.52um

AVDD

...

AVSS

AVDDAVSS

...



MACRO AFE CLASS BLOCK ; FOREIGN AFE 0.000 0.000 ; ORIGIN 0.000 0.000 ; SIZE 26.000 BY 41.000 ; SYMMETRY X Y R90 ;

PIN AVDD DIRECTION INOUT ; USE POWER ; PORT LAYER M7 ; RECT 0.000 1.350 5.000 1.870 ; RECT 0.000 4.600 5.000 5.120 ; RECT 0.000 7.850 5.000 8.370 ; RECT 0.000 11.100 5.000 11.620 ; … … END END AVDD

PIN AVSS DIRECTION INOUT ; USE GROUND ; SHAPE ABUTMENT ; PORT LAYER M7 ; RECT 7.000 2.370 12.000 2.890 ; RECT 7.000 5.620 12.000 6.140 ; RECT 7.000 8.870 12.000 9.390 ; RECT 7.000 12.120 12.000 12.640 ; … … END END AVSS

……

- multiple power/ground pins (5um x 0.52um) extracted from the top-level power grid of 0.52um-width M7(H) stripes (*)

- 26um x 41um PNR boundary

(*) 0.52um-width stripes to accomodate the default 1x1 M7-M8 via (no min. rules)

- 5um-width M8 (V) power/ground stripes for AVDD/AVSS NOT included in the LEF file !

- LEF file created by hand (Tcl/SKILL script for the Abstract Generator under preparation)

- additional M6 stripes for DIGITAL power/ground (latch and delay line)



- assume to use 0.5um-width M6 (V) stripes for all bias signals

…

PIN VREF_KRUM DIRECTION INOUT ; USE ANALOG ; PORT LAYER M6 ; RECT 1.215 40.500 1.715 41.000 ; END END VREF_KRUM

PIN VCAS_KRUM DIRECTION INOUT ; USE ANALOG ; PORT LAYER M6 ; RECT 5.655 40.500 6.155 41.000 ; END END VCAS_KRUM

… …

OBS LAYER M1 ; RECT 0.000 0.000 26.000 41.000 ; LAYER M2 ; RECT 0.000 0.000 26.000 41.000 ; LAYER M3 ; RECT 0.000 0.000 26.000 41.000 ; LAYER M4 ; RECT 0.000 0.000 26.000 41.000 ; LAYER M5 ; RECT 0.000 0.000 26.000 41.000 ;

END

END AFE

END LIBRARY

- obstruction stack limited to M1-M5 only

- power and bias routing performed by Encounter ! (see later)

- necessary routing blockages added later, before digital routing (limited to M2-M5 or M2-M4 between islands)



VS

S

VD

D

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSS

AVSSAVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

AVDD

Ibias / Vbias pins (M6)

sig

na

l p

ins

(M

2-M

4)



latch / delay line supplied at digital VDD/VSS

MACRO bump CLASS COVER BUMP ; ORIGIN 0.000 0.000 ; SIZE 22.000 BY 22.000 ; SYMMETRY X Y ; PIN BUMP DIRECTION INPUT ; USE SIGNAL ; PORT CLASS CORE ; LAYER AP ; POLYGON 15.590 0.000 22.000 6.410 22.000 15.595 15.595 22.000 6.390 22.000 0.000 15.610 0.000 6.395 6.395 0.000 ; END END BUMP

END bump

- bump pattern generated by Encounter at top-leve/partition level but...

- NO routing performed in the PNR tool between bumps and analogue macros !!!

- any extra connections to the bump must be 'hidden' in the abstract of the analogue block

Bump pad /1


AP22um x 22um

Synchronous Front-End approach /1Two available options for AP-M9 interconnection !

AP/CB2

AP / RV / M9

Bump pad /2

AP/CBD

M9


Synchronous Front-End approach /14x4 Placement floorplan

- 200um x 200um PNR boundary

- 26um x 41um analogue macros

- analogue-islands arrangement

- assume a 4x4 digital regional architecture

- 50um x 50um pixels

- 50um pitch bump pattern

4x4 Pixel Region (PR) floorplan


Synchronous Front-End approach /14x4 Placement floorplanPartition-level power routing (Encounter) /1


M8

(V)

5u

mV

DD

M8

(V)

5u

mV

SS

AV

DD

AV

SS

VD

DV

SS

AV

DD

AV

SS

VS

S

AV

SS

VS

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DD

M8

(V)

10u

mM

8 (V

)

5um

M8

(V)

5u

m

M8

(V)

10u

mM

8 (V

)

5um

M8

(V)

5u

m

M8

(V)

10u

mM

8 (V

) 5

um

M8

(V)

5u

m

M8

(V)

5u

mM

8 (V

) 5

um

- M8 power/ground stripes retained at the partition level (in parallel with M9 at the top-level)

- AVDD/AVSS connections to macros performed by Encounter during power routing !

AV

SS

M8

(V

) 5

um

M8

(V

) 1

0um

M8

(V

) 5

um

AV

SS

AV

DD

AV

SS

Partition-level power routing (Encounter) /2


5x VIA7



# Left Bottom Right Top PixeladdHaloToBlock $halo_x 0.0 0.0 $halo_y analogue_0addHaloToBlock 0.0 0.0 $halo_x $halo_y analogue_1…

1um-width placement halos added around analogue macros



VS

S

M6

(V)

1u

mV

DD

M

6 (V

)

1um

VS

S

M8

(V)

1u

m

VD

D M

8 (V

)

1um

VS

S

M6

(V)

1u

mV

DD

M

6 (V

)

1um

VS

S

M6

(V)

1u

mV

DD

M

6 (V

)

1um

VS

S

M8

(V)

1u

m

VD

D

M8

(V)

1u

m

- digital power/ground stripes for latch/delay line exploited to build a secondary power grid for STD cells (avoid just a direct connections between M1 rails and M8 top-level stripes!!! )

- M6(V) - M7(H) - M8(V) dedicated to the local digital power distribution

f

rom

A. M

ekka

oui tal

k

Vertical bias stripes necessary routed between analogue islands

- use M5 and M7 for bottom/top shielding between islands (see later)

- bottom digital routing constrained to M2-M4 only (mainly quiet configuration logic)

- already performed in FE65_P2 demonstrator

Bias distribution /1


module PixelRegion( … …

// analogue bias lines inout [3:0] VREF_KRUM, inout [3:0] IBIASP2, inout [3:0] IBIASP1, inout [3:0] VCASP1, inout [3:0] VCAS_KRUM, inout [3:0] VCASN, inout [3:0] IBIAS_FEED, inout [3:0] IBIAS_SF, inout [3:0] VCASN_DISC, inout [3:0] CAL_LEVEL, inout [3:0] IBIAS_DISC, inout [3:0] ICTRL_TOT, inout [3:0] VBL_DISC, inout [3:0] VTH_DISC, … );

AFE analogue_0 ( .VREF_KRUM ( VREF_KRUM[0] ), .IBIASP2 ( IBIASP2[0] ), .IBIASP1 ( IBIASP1[0] ), .VCASP1 ( VCASP1[0] ), .VCAS_KRUM ( VCAS_KRUM[0] ), .VCASN ( VCASN[0] ), .IBIAS_FEED ( IBIAS_FEED[0] ), .IBIAS_SF ( IBIAS_SF[0] ), .VCASN_DISC ( VCASN_DISC[0] ), .CAL_LEVEL ( CAL_LEVEL[0] ), .IBIAS_DISC ( IBIAS_DISC[0] ), .ICTRL_TOT ( ICTRL_TOT[0] ), .VBL_DISC ( VBL_DISC[0] ), .VTH_DISC ( VTH_DISC[0] ), .AVDD(AVDD), .AVSS(AVSS), … … ); …

endmodule : PixelRegion



All bias connections included in the pixel-region Verilog wrapper

Synchronous Front-End approach /1Bias distribution /3

[

0]

[

1]

[

2]

[

3]



- automatically-generated schematic for the PR, LVS OK back into Virtuoso

- 0.5um-width M5(V) bias stripes generated by Encounter !!!

- pins-independent stripes generation (ref. to code snippet if interested in)

- 'dangling wire' warnings if connectivity is checked in Encounter using the built-in verify_connectivity

set count 0foreach instName {analogue_0 analogue_1 analogue_8 analogue_9} { set ptr [dbGetInstByName $instName]

foreach pin [dbGet $ptr.cell.terms] { if { [dbGet $pin.type] == "analogTerm"} {

set biasName [dbGet $pin.name]\[$count] set pinPosition [dbGet $pin.pt] set pt_start [list [lindex [join [dbTransform -inst $ptr -localPt $pinPosition]] 0] 0.000] set pt_stop [list [lindex [join [dbTransform -inst $ptr -localPt $pinPosition]] 0] 200.000]

add_shape -net $biasName -status fixed -layer M6 -width 0.5 -pathSeg [concat $pt_start $pt_stop]

set x_start [lindex $pt_start 0] puts $fileName " (pin name=$biasName layer=6 width=0.5 depth=0.5 place_sttus=fixed offset=$x_start )" } } set count [expr $count + 1]}……loadIoFile ./scripts/abias.io

M6

(V)

0.

5u

m



Synchronous Front-End approach /1Bias distribution /5A few comments and open questions/issues :

- for the moment, just draw through Tcl commands (e.g. add_shape) all stripes and required shieldings, as one would perform 'by hand' in the full-custom design environment

- by default, all nets are considered just as 'signals' in OA sch.

- are there any other techniques ? Can Encounter itself take into account of necessary shielding for bias lines? How to perform IR drop analysis on bias lines ? Do we need to define them as power nets in the design-import phase?

- don't forget to define all bias pins as ANALOG in the LEF file as well as in schematic pin properties !!!

PIN VREF_KRUM DIRECTION INOUT ; USE ANALOG ; PORT LAYER M6 ; RECT 1.215 40.500 1.715 41.000 ; ENDEND VREF_KRUM

- when performing digital routing later, constrain the engine to skip analogue signals from routing

setNanoRouteMode […] -dbSkipAnalog […]



Back to Virtuoso


In case you don't trust Encounter...

- LVS OK !

- DRC OK !

Synchronous Front-End approach /1Synchronous Front-End approach /1Power-grid for the AFE /1Generate a power-grid for the analogue Front-End using the Voltus engine to improve the accuracy of ERA and subsequent sign-off power analysis

- requires the QRC technology file, abstract (LEF) , gds , SPICE foundry models and post-layout extracted netlist- Tcl based flow (ref. to Cadence official RAK for Voltus)

set QRC_TECHFILE /eda/kits/tsmc/CERN_PDK/Base_PDK/V1.7A_1/1p9m6x1z1u/Assura/lvs_rcx/qrcTechFileset LEFDIR /eda/kits/tsmc/CERN_PDK/Base_PDK/digital/Back_End/lefset MACRODIR /users/pacher/scratch/devel/tsmcN65/dfII/macrosset GDSDIR /users/pacher/scratch/devel/tsmcN65/dfII/gdsset LEF_FILES [list $LEFDIR/tcbn65lp_200a/lef/tcbn65lp_9lmT2.lef \ $MACRODIR/AFE/lef/AFE.lef ]

read_lib -lef $LEF_FILES

set_pg_library_mode -celltype macros \ -extraction_tech_file $QRC_TECHFILE \ -power_pins {AVDD 1.2} \ -ground_pins AVSS \ -temperature 25.0 \ -current_distribution propagation \ -gds_files $GDSDIR/AFE.gds \ -gds_layermap ./gds.layermap \ -lef_layermap ./lefdef.layermap \ -stop@via polyCont \ -cell_list_file ./macro.list \ -spice_models ./models.scs \ -spice_subckts ./netlist/AFE_av_extracted.spice

generate_pg_library -output ./results/AFE_pgv/

Voltus power-grid for the AFE /1


Synchronous Front-End approach /1Power-grid for the AFE /2

Encounter Virtuoso (M1-M2)

Voltus power-grid for the AFE /2


Synchronous Front-End approach /1Full-chip ERA on AVDD (1.2V @1%)Full-chip ERA on AVDD (1.2V @ 1%) /1


Full-chip ERA on AVDD (1.2V @ 1%) /2


……

if { ![file exists ./scripts/AFE.pwr ] } { set fileName [open "./scripts/AFE.pwr" "w"] for {set i 0} {$i < 16} {incr i} { for {set j 0} {$j < 16} {incr j} { for {set k 0} {$k < 16} {incr k} { puts $fileName \ "CORE_CHIP/i_PixelMatrix/quadcol[$i].i_QuadColumn/row[$j].i_PixelRegion/pixel$k/PixelAnalogue 0.000005 AVDD" } } }}

……

analyze_early_rail -net AVDD \ -method static \ -type net_based \ -net_voltage $AVDD_nominal \ -volt_limit $AVDD_limit \ -bias_voltage $AVDD_bias \ -temperature $Temp \ -check_connectivity \ -display_IR \ -view MMMC_TYPICAL \ -pad_location_file $VSRC_FILE \ -output_dir ./reports/power/ERA/prePlace \ -instance_ascii_power_file ./scripts/AFE.pwr \ -current_region_file ./scripts/AVDD_static_current_region \ -power_grid_library $MACRODIR/AFE/char/power_grid/results/AFE_pgv/macros_AFE.cl

For the ERA on AVDD rails an ASCII instance power file is generated assuming 5uW/pixel analogue power consumption

Synchronous Front-End approach /1Full-chip ERA on AVDD (1.2V @1%)Liberty characterization


● timing and static/dynamic power dissipation for the analogue front-end described in Liberty standard

● Liberty file (.lib) obtained using the Liberate AMS fully-automated library characterization tool

- Tcl based flow (ref. to Cadence official RAK for Liberate)

- only requires foundry models and Spectre netlists of DUT and testbenches !

● design flow tested in Torino, but up to now... no charaterization data are written on the generated liberty file after processing ! :-(

- pin capacitances

- total DC current/power (aka 'leakage power' in STD cells)

- dynamic power for a given stimulus

- no idea about what's wrong in our customized scripts from templates

- actually not clear also how to apply the flow on our block with multiple power domains !

Synchronous Front-End approach /1Motivations for a new layout floorplan

- continuous-time front-end channel designed in 65nm CMOS technology to fit ~50% of the total pixel size in a 35um x 35um square area (A. Mekkaoui)

- seamless integration of two different front-end flavors into the same digital-on-top flow

- common usage of routing metal layers, same top-level power, bias distribution and shielding

- very likely the same floorplan/constraint will be assumed as a baseline choice in the definition/competition of front-end flavors that will be integrated in the RD53A prototype

- adopt the same charge-injection circuit scheme (different transistor sizing OK)

● take advatage of a top-down design methodology !

- bottom layout 'driven' by top-level arrangement and constraints

- easier interconnections to the main power grid and common usage of bias lines

Motivations for a new layout floorplan

● comparison with what already done in RD53

● mutually agree on and define NOW common area, aspect ratio, top-level routing constraints and same basic digital interfaces for both Torino a Pavia analogue macros

● a 35um x 35um square floorplan ensure the bump-pad to stay within the analogue part


35um x 35um analogue PNR boundary

'digital sea'

- 50um-pitch bump pattern

- 22um bonding pad (AP)

- 35um x 35um analogue area (PNR boundary! )

- 5um-width M8 (V) power/ground stripes (partition level) in parallel with M9(V) (top-level)

35um x 35um analogue floorplan /1

- 'analogue islands' arrangement

M8

(V)

5u

m

- 50um x 50um pixel size


AV

DD

AV

SS

VD

D

VS

S

M8

(V)

5u

m

M8

(V)

5u

m

M8

(V

) 5

um

22um x 22um bump pad

35um x 35um analogue floorplan /2


AV

DD

AV

SS

AV

SS

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SV

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VS

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DD

Shielding for bias lines /1A

VS

S

Ibia

s /

Vb

ias

0.5u

m M

6 (V

) 0.52um M7 (V)

Shielding for bias lines /1

3 / 27 August 31, [email protected] 39 / 46 August 31, 2015

AVDD

AVSS AVDD

Ibia

s /

Vb

ias

Ibia

s /

Vb

ias

Ibia

s /

Vb

ias

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DD

Ibia

s /

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ias

Ibia

s /

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Ibia

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Vb

ias

Ibia

s /

Vb

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Ibia

s /

Vb

ias

Ibia

s /

Vb

ias

Ibia

s /

Vb

ias

Ibia

s /

Vb

ias

AV

SS

- bias lines routed between M5 and M7 shielding plates to safely traverse the 'digital sea'

- M5-M7 shielding plates tied either to AVDD or AVSS depending on the desired coupling



6um M5/M7 plates

M5 M5 M5

AVDD

AVDD AVSS

AVSS

- 12um max. width for any Mx/z/u (from DRC)

- 1.5um min. spacing between two adjacent M5/M7 plates (from DRC)

- 1.5um min. spacing between M7(H) and M7 top plates

6um M5/M7 plates

6um M5/M7 plates

Synchronous Front-End approach /1Shielding for bias lines /2

- empty space under the bump pad for AP-M4

- max. 16 bias lines available for the AFE with this scheme

- 4x bias lines M6(V) per group with 2x AVDD/ASS M6(V) lateral stripes

- digital routing limited to M2-M4 between islands



- 8 bias lines coupled to AVDD and 8 coupled to AVSS



3 / 27 August 31, 2015

CSAKrum

charge inj

PREAMP DISC

phi SWs

latch/delayAC/AZ caps

Placement floorplan (preliminary!)


- for the moment no more than some LEGO gaming

- space not an issue (the original layout occupies ~43% pixel size )

- clear advantage of bump pad placement within analogue area

Substrate biasing


● no chance to distribute a low-impedance metal path (i.e. M9) along columns just dedicated to substrate biasing

● the analogue substrate necessary will be tied to the analogue ground at the pixel level !

● somewhere in the analogue pixel ASUB = AVSS

- STD cell-like approach or ...

- star connection by keeping ASUB and AVSS separated up to the M7(H) top-level power grid ?

Isolation strategy between A/D domains● definition of a common isolation strategy between analogue and digital mandatory

● different options offered by the chosen 65nm CMOS process

- analogue-only pixel in DNW

- digital-only pixel (region) in DNW

- analogue and digital put in two different DNWs (as performed in FE65_P2)

● if STD cells will be put in DNW, a new dedicated library is required for sign-off LVS

- not a limiting issue, recoursive replacement of all nch devices with nch_dnw in STD cells can be easily achieved with a SKILL script

● take into account of min. spacing design rules for DNW !!!


- requires 1x global DAC to generate a precise DC level CAL_LEVEL

- requires 1x switching digital pulse TestP distributed to all pixels

- CAL_EN configuration bit from configuration logic (SEU-protected)

Charge injection circuit


● direct propagation of a calibration step in analogue form not suitable for a large chip !

● assume instead a local generation of the analogue test pulse starting from a DC voltage distributed to all pixels

Torino analogue Front-End - Agenda INFN

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