topologii de circuite

Analog & Digital VLSI Design Analog AssignmentMarch 10, 2011

1. OBJECTIVE: To get you over the real world Analog Design. To give you an exposure on Layout. To develop your intuition for designing, i.e. selection of topology, biasing scheme, simulation techniques, interpretation of results/ graphs etc.. You should be able to determine how and which of the transistors sizes (W/L) in the circuit will affect which parameters (specs). Using EDA tools efficiently in system design

2. COMMON INSTRUCTIONThe instructions given here will need to be followed by all students. Please note that failure to do the same will result in a penalty of marks. The assignment has to be done in a group of two students. A total of 26 assignments are listed below so every group has to pick up one assignment. You have to use Cadence Schematic editor to draw your circuit. For simulation you are free to use any of the two simulators: Spectre and Eldo. Everyone has to draw the layout (OpAmp only), extract the netlist and again simulate it to verify the performance. Your design should meet all the specifications, both before drawing layout and post layout. It is generally advised to overestimate your specs by around 25% at the schematic level to account for parasitic that result after the layout. If you are not able to meet your specs, you can go ahead, but you need to explain why it has happened at the time of demonstration and in report. You have to design your circuit using gm/Id methodology only. Validate your design for all process corners and temperatures 0, 27 and 100 :C.

Library for circuit simulation; edatools/dk/tsmcmm018/6m/models/spectre/rf018.scs with Sections TT_3V, FF_3V, SS_3V , SF_3V , FS_3V edatools/dk/tsmcmm018/6m/models/eldo/rf018.eldo TT_3V, FF_3V, SS_3V Use Model names pch3 for PMOS and nch3 for NMOS, unless otherwise specified. Min. channel length that can be used is 0.35u For models nch/pch used TT, FF, SS, SF and FS sections in place of TT_3v, etc. All device dimensions (Ws and Ls) used must be whole number microns. Use Supply voltage of 3.3 V +/- 10% with a series resistance of 50 ohms (why?), unlessotherwise stated.

Power dissipation must be less than or equal to 3mW unless stated otherwise. Unless otherwise specified, load cap for all the systems is 200f F. You can use capacitors ranging from 50f F to 10n F in your design. Capacitors used within the OpAmp must be simulated and laid out using MOSFETs. All current sources have a temperature coefficient () of 0.003/ :C. Current sink means that one of the nodes is connected to ground and current sourcemeans that one of the nodes is connected to the supply.

The suggested topologies are to be used unless there is a valid reason not to do the same. OTA stands for Operational Transconductance Amplifier, which is basically an OpAmpwith high output resistance.

All OpAmps/OTAs used feedback must be compensated for a phase margin of about50: to 60:, unless your application requires it to be some other value.

The worst case analysis (.WCASE) and the Monte Carlo analysis (.MC) must be performed to verify practicality of the design.

1. RC Phase-Shift Oscillator Generate a 1 MHz signal Settling time = 50us for sustained oscillations THD