Top DownDesignMethodologyforEnhanced EBG Structures

8/13/2019 Top DownDesignMethodologyforEnhanced EBG Structures

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DesignCon 2014

Top-Down Design Methodology

for Enhanced Electromagnetic

Band-Gap Structures

Jai Narayan Tripathi, STMicroelectronics Pvt. Ltd., INDIA.

[[email protected], +91-120-667-7044]

Raj Kumar Nagpal, STMicroelectronics Pvt. Ltd., INDIA.[[email protected], +91-120-667-7267]

Nitin Kumar Chhabra, STMicroelectronics Pvt. Ltd,

INDIA. [[email protected], +91-120-667-7044]

Rakesh Malik, STMicroelectronics Pvt. Ltd., INDIA.

[[email protected], +91-120-667-7003]

Jayanta Mukherjee, IIT Bombay, Mumbai, INDIA.

[[email protected], +91-22-2576 7479]


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AbstractThis paper presents a top-down design methodology for the design of EBG structures

meeting design targets identified in terms of S/Z parameters. The design of EBGstructures are based on multiple design considerations of central cell structures as well ascell to cell interconnect structures. Possible iterations of cell structures and cell to cell

interconnects are captured in libraries for design trade-offs. The RLGC first order basedapproach followed by precise s-parameter models extraction (2.5D/3D) is proposed in

this paper. RLC libraries created are generic and reusable for top-down designmethodology. This methodology is generic and has high value add in terms of systematic

EBG design, cost consideration and design trade-offs. Further library augmentation, flow

automation can be applied and this flow can be offered as a design tool. Methodology

validation is carried out by one real design case wherein fabricated structure results (S 21,Z11) are correlated with the mentioned design flow. The real design case EBG structure is

having stop-band from 750 MHz to 5.10 GHz with isolation better than -30 dB. A close

correlation is achieved with s-parameter using the top-down design methodology andmeasured results.


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Author(s) BiographyJai Narayan Tripathi is currently a Ph.D. research scholar at IIT Bombay, Mumbai. He

received his Bachelor of Engineering (ECE) in 2007 from University of Rajasthan,

Jaipur, and Master of Technology (ICT) from DA-IICT, Gandhinagar in 2009. His areasof interest are Signal/Power Integrity and RF Circuits Optimization. He is author of one

research monograph and has served as reviewer for many journals like PIER, IEEE

TEMC, Microelectronics Journal etc. He has 30 international research publications to hiscredit. Apart from academics, his hobbies are Creative Writing and Music.

Raj Kumar Nagpal received Bachelor of Engineering (EC) from Nagpur University, India

in 1989 and Master of Technology (ME) from University of Delhi in 1995. He has

around 24 years of industrial experience in electronics, instrumentation, Antenna and RFdesign, signal integrity and Power Integrity, High speed serial link architecture

considerations. Currently he is Principal Engineer at STMicroelectronics Greater Noida,

India. He is also acting as Vice Chair of MIPI (Mobile Industry Processor Interface)PHY Work Group and Chair of D-PHY Sub Group. Previously he worked in Central

Electronics Limited, a public sector unit under Department of Science and Industrial

research and Defense Research and Development Organization DRDO, India. He haspublished around 15 papers in various IEEE conferences.

Nitin Kumar Chhabra received Bachelor of Engineering (EE) from Indian Institute of

Technology Roorkee, India in 2004. He is staff engineer in TRnD, STMicroelectronicsIndia, where he has been working on Signal Integrity and Power Integrity issues in High

Speed Serial Links, for more than 5 years. His research interests are Jitter Analysis, SI/PI

correlation, and System level Simulation. He has secured positions in U.P. Board meritlists both for high school and intermediate examinations. He has 10 research papers in

various IEEE publications.

Rakesh Malik received his Bachelor of Engineering (EEC) from Punjab Engineering

College, Chandigarh, India in1986. He has an industrial R&D experience of over 27

years. Currently he is a senior group manager in TR&D, STMicroelectronics, India, and

is the chair of IEEE SSCS Delhi chapter. He has experience in semiconductor domaininvolving mixed signal IPs design involving Analog to Digital, Digital to Analog

Converters of various speed/precisions/architectures, Serial links designs, Digital signal

processing, basic analog blocks and signal/power integrity. He has 8 patents grant in

US/Europe and has 20 IEEE publications.

Jayanta Mukherjee is currently an Associate Professor at the Indian Institute ofTechnology Bombay. His research interests include RFIC design and testing, antennasand biomedical VLSI circuits. Previously he was a Texas Instruments Fellow during his

Ph.D. 2001-2004. He was also awarded the gold medal at Birla Institute of Technology

during his Bachelor of Engineering. He has interned at Thomson Multimedia, Princeton,New Jersey during 2002-2003. He is the author of one book.


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IntroductionNoise in power delivery network for higher frequency operation is detrimental for robust

operation of complex system on chip. The impedance profile of a rectangular board has

many resonance and anti-resonance points depending on its dimensions and dielectricmaterial [1][2]. The magnitude of the maximum impedance over the frequency range of

interest can be in hundreds of Ohm. Electromagnetic Band Gap (EBG) structures

effectively reduce the resonance/anti-resonance patterns in high speed boards by damping

them [3][4]. EBG structures are the alternative of embedded capacitors and are cost-

effective in comparison to them [5]. They are used in power delivery network design to

isolate RF noise coupling from one region of PDN (power delivery network) to other and

are heuristically designed generally [6][7].

EBG structures in the industry are useful to confine the noise propagation in the power

planes between the different sections of application boards. In highly complex boards

holding multiple active devices, it is desirable to isolate the power plane noise coupling

between different sections of boards [5]. In real case implementations, generally there are

some conflicting requirements coming from lower target impedance of Power Delivery

networks.

In todaysenvironment, the design of EBG structures is generally manual and iterative in

practice. This approach may not lead to optimal EBG structure solution. The present

work provides a solution to this problem by a systematic library based approach. The

proposed top-down design methodology along with optimization engine is eliminating

the manual approach. This makes the design of EBG structure automated and optimized

for given constraints.

Top-Down Design Methodology for EBG structure designThe novel top-down synthesis methodology provides a systematic approach to design a

desired EBG structure meeting and exceeding the design targets. It is based on thegeneration and optimization of library components, modeling the behavior of cell and

interconnects between the cells. EBG structure is assumed to be consisting of number of

uniform or non-uniform unit cells. This decision on choice for uniform or non-uniform

unit cell is based on the PDN constraints.

Input requirement and number of cell calculationInputs to EBG structure design methodology has four componentsi) Desired isolation (S21) for the given physical space (Pd)ii) Self-impedance requirement Z11iii) Typical board size for which EBG structures should be designed.iv) Stack-up choicev) Cost


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The given physical space considerations are derived from physical distance (Pd) between

two neighboring points for which S21 parameters should be met. This information will

determine the typical cell size along with interconnect which satisfy the design targets.The self-impedance requirement is coming from target impedance considerations for the

given PDN.

As first step, the 3x3 EBG structure is assumed for board design. In subsequent iterations,this will be reduced or increased depending upon S21, Z11criterion.

Estimation of basic cell size and interconnect size

From the given S21and Z11parameters, the effective cell capacitance and interconnectinductance is determined by first order approximation. In this approximation, a basic

RLC network values are estimated or optimized meeting the S21and Z11targets.

In the next step, the unit cell is created (having patch and interconnect RLC model).

Linterconnect

Figure 1 : RLC equivalent circuit of patch and interconnect


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Further, board structure is created using these 9 unit cells. Then, RLC values are

optimized to meet targeted S21, Z11. Using capacitance of patch, its area can calculated(C= A/d). Assuming shape of the patch to be square, the side of patch is known. The

width of patch should be less than 1/3 of board size. In case this criterion is not met,

either repeat an iteration to change number of cells or a decoupling capacitor is required.

This will fix the number of cells and the cell size. Also, the Linterconnect

calculated through

optimization will be used to calculate the effective length of the interconnect using the

following formula for microstrip line

LMSL = ( ).

where K1 = 0.2 nH/mm, d= dielectric width of microstrip line, w is width of microstripline. The effective length is calculated as following

Leffective = Linterconnect/LMSLThe interconnect shapes are available as libraries of interconnects. Various shapes can beused to meet criterion of Leffective

Creation of geometry in 3D solver

As a next step, the patch geometry and interconnects are drawn in a 3D solver. A Scriptis used in 3D extractor to generate cell and interconnect geometry around the estimated

values.

Figure 2: RLC equivalent of one cell


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Validation of S-parameter concatenation

In this step, the patch and interconnects (a,b,c as shown in figure 4) s- parameters areextracted in 3D solver. The individual parameter of interconnect b) and patch a) are

concatenated in schematic (figure 5) so as to form structure equivalent to c)

a) b) c)

Figure 4: Patch and interconnect in 3D solver

Figure 3 : Geometries of interconnect and basic cell


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Figure 6 shows close match between the S21and Z11profile extracted from 3D solver and

the same achieved from concatenation of s-parameters of the patch and the interconnect.

The reason for small differences in matching is due to the fact that the mutual coupling isnot considered in s-parameter approach. Still the closeness shows that the individual s-

parameter components could be concatenated for simulation of complete EBG structure

on board.

A design example using the proposed methodologyA board of dimension 90 mm x 90 mm with 9 cells is chosen. The S 21target specification

is to achieve stop band of atleast 4 GHz. However the Z11target specs are relaxed. The

RLC equivalent model of patch and interconnect from existing library is chosen. RLC

model of complete board is created by using the 9 cell model (Figure 7). Next step is

Figure 5: S- parameter concatenation

Figure 6: Comparison of S-parameter concatenation vs. 3D solver


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optimization of RLC values to get the desired stop band of more than 4 GHz. After

optimization, the values of R, L, C for patch are found as R = 2.53 m, L =21.10 pH, C =

57.32 pF. For horizontal interconnect, the values are R = 692.80 m, L = 1.92 nH, C =2.60 pF. Whereas for vertical interconnect, the values are R = 0.001 m, L = 95.0 pH,

and C =3.10 pF. (Patch with interconnect are shown in figure 8)

With these values of RLC, single cell dimensions are calculated, a = 30mm, b = 26 mm,c = 2 mm, d = 0.5 mm, e = 0.5 mm. The structure is patch with interconnects. Patch issquare cell with a dimension b, a is complete length of the cell (patch & interconnects), c

is the difference between a and b. while d and e are the width of interconnects. All

interconnects are 0.5 mm wide.

Figure 7 : RLC concatenation of unit cell to form equivalent circuit of complete board


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Using the dimension of this cell a complete board is fabricated (figure 9)

Measurement setupThe s-parameter measurement is done using network analyzer with port 1 at (46 mm, 45

mm) and port 2 is at (74mm, 74 mm). There is a stop-band of 4.35 GHz ranging from700 MHz to 5.1 GHz. (figure 10)

Figure 8: Single cell of EBG structure : A patch with vertical & horizontalinterconnects

Figure 9: Complete EBG structure and its fabricated board


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CAD vs. Measurement correlationThe S-parameters obtained forms the RLC equivalent model can be seen in fig. 11. This

provides first approximation.

The S parameters are concatenated to form the complete board structure. The CAD

results are in close correlation with measured fabricated EBG structure

Figure 10: Measurement setup

Figure 11: RLC vs. measurement


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The EBG structure designed in the above example by the proposed methodology was

fabricated for validation and is correlated with measurement results. A close correlationbetween these two results is shown which validates a stop-band of 4.35 GHz, from 750

MHz to 5.10 GHz.

Figure 12 : EBG structure by S-parameters concatenation

Figure 13: S-parameter vs measurement correlations


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ConclusionThis paper presents a novel top-down methodology for designing of EBG structures. The

methodology is based on RLC equivalent model creation and optimizations to get thephysical dimension of cell based on S21, Z11requirement. The structures are created in 3Dsolver to extract s-parameters of individual components. This is concatenated to form the

complete board structure. This paper shows designing of an EBG structure using themethodology with given dimensions (90 mm x 90 mm x 0.4 mm). The minimum

bandwidth requirement was 4 GHz using FR4 as a dielectric material. The design wasvalidated both in CAD (by a 3D solver) and in fabrication. There is a close correlation in

s-parameters from all three results RLC model, 3D extraction from physical structure

libraries and lab measurements using VNA. The stop-band achieved is 4.35 GHz, ranging

from 750 MHz to 5.10 GHz. The methodology is generic and is a systematic approach toEBG design.


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Top DownDesignMethodologyforEnhanced EBG Structures

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