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Source: Rysavy ResearchNote: Throughput rates are peak network rates. Radio channel bandwidths indicated. Dates refer to initial network deployment except 2006 which shows available technologies that year.
LTE Layer 1 Software Components► Application Layer: Integration and
application scheduler functionality.► LTE Library: The OS independent
implementation of the LTE Layer1 functionality.
► Multicore Framework: Responsible for memory management, multicore communication and low level resource scheduling.
► MAPLE Abstraction Layer: Thin layer to abstract OS implementation details for controling the MAPLE HW accelerator. (Multi Accelerator Platform for BaseBand, details in next slides)
► Coherency Abstraction Layer: Function library with services to handle the coherency management.
► IF1 and IF4 interfaces: Cover the protocol and LTE specific aspects of the interface with PQ and FPGA.
► Operating System: Operating system services and driver level support for device peripheral access.
(1) SPM_PRB_DYNAMIC_T•pointers to the buffers specific to the current manager call instance.
(2) SPM_PRB_STATIC_T•pointers to the buffers common to all the instances of this manager.
(3) SPM_PRB_CTRL_DYNAMIC_T•control parameters that are specific to the current manager call instance (the number of allocations, number of codeblocks…)
(4) SYS_CONFIG_T•system configuration parameter information, setup at system initiation (sector bandwidth, the number of antennas, etc.)
(5) SWC_T•pointers to the software coherency functions (cache flush and cache invalidate).
(6) type_dftpe_mal•pointers to the Maple abstraction function for IDFT / DFT / TurboDecoder / ViterbiDecoder
MAPLE Abstraction Layer► MAPLE Abstraction Layer (MAL) is responsible
for the encapsulation of the MAPLE interaction based on SDOS drivers.
► The goal is to keep the SP Lib independent of the underlaying OS while allowing a close integration of the MAPLE accelerator in the processing chains
► MAL API covers:• MAPLE init functionality for LTE mode• FFTPE, DFTPE and TVPE drivers
MSC8156E – Broadband Wireless DSP • 6 SC3850 Cores Subsystems (up to 6GHz/48GMACS) each
with:• SC3850 DSP core at up to 1GHz (8GMACs 16b or 8b)• 512 Kbyte unified L2 cache / M2 memory. • 32 Kbyte I-cache, 32Kbyte D-cache, WBB, WTB, MMU, PIC
• Internal/External Memories/Caches• 1056 KByte M3 shared memory (SRAM)• Two DDR 2/3 64-bit SDRAM interfaces at up to 800 MHz
• CLASS – Chip-Level Arbitration & Switching Fabric• Non-Blocking, fully pipelined, low latency• Full fabric 12 masters to 8 slaves, up to 512 Gbps throughput
• MAPLE-B – Baseband Accelerator• Turbo/Viterbi Decoder up to 160/115 Mbps, supporting: 3G-
LTE, 802.16, 3G, CDMA2K standards• FFT/DFT accelerator up to 280/180 Msps DFT
• Security Engine (Talitos 3.1)• Data and Code Protection (AES, SHA, Kasumi, SNOW3G)
• High Speed Interconnects• Dual 4x/1x Serial RapidIO at 1.25/2.5/3.125 Gbaud• PCI-e 4x/1x
• Dual RISC QUICCEngine® supporting• Dual SGMII/RGMII Gigabit Ethernet ports • Eth. L1 Protocols, Talitos control and sRIO offload
• TDM Highway• 1024 ch., 400Mbps, divided into 4 ports of 256
MSC8156 MAPLE-B Throughput & Compliance DataTechnology Accel. Standard Compliance Data Rates Comments3G-LTE, TDD-LTE
Turbo 3G-LTE (Evolved UTRA) turbo decoding as specified in 3GPP TS 36.212, section 5.1.2.2
up to 160 Mbps (8 iterations)up to 200 Mbps (6 iterations)
Max Log Map or Linear Log Map (MAX*)Support Rate-De-Matching (sub-block de-interleaving and de-interlacing)CRC calculation
Viterbi 3G-LTE (Evolved UTRA) channel decoding as specified in 3GPP TS 36.212, section 5.1.2.1
up to 100 Mbps (K=7 with tail biting) Multi-iteration decoding
FFT/DFT FFT sizes - 128, 256, 512, 1024, 2048 pointsDFT sizes - Variable lengths DFT/IDFT processing of the form 2k·3m·5n·12, up to 1536 points
FFT – up to 280 Mega samples/secDFT – up to 175 Mega samples/sec
Advanced scaling optionsGuard bands insertion in iFFT
CRC Transport and Code Block CRC for UL and DL up to 12 Gbps CRC check or insertion
WiMAX Turbo WiMAX OFDMA turbo decoding as specified in IEEE® 802.16™-2005 standard
up to 156 Mbps (8 iterations)up to 195 Mbps (6 iterations)
Max Log Map or Linear Log Map (MAX*)Support Rate-De-Matching (sub-block de-interleaving and de-interlacing)
Viterbi WiMAX OFDMA turbo decoding as specified in IEEE® 802.16™-2005 standard
up to 100 Mbps (K=7 with tail biting) Multi-iteration decoding
FFT FFT sizes - 128, 256, 512, 1024, 2048 points FFT2048 – up to 280 Mega samples/secFFT1024 – up to 350 Mega samples/sec
Advanced scaling optionsGuard bands insertion in iFFT
CRC PHY Burst CRC for UL and DL up to 12 Gbps CRC check or insertion
HSPA+ Turbo 3GPP turbo decoding as specified in 3GPP TS 25.212, section 4.2.3.2.
up to 131 Mbps (8 iterations)up to 165 Mbps (6 iterations)
Max Log Map or Linear Log Map (MAX*)Support EDCH Rate De-Matching
Viterbi 3GPP viterbi decoding as specified in 3GPP TS 25.212, section 4.2.3.1.
up to 115 Mbps (K=9 zero tail)
ProgrammingModel
ALL Buffer descriptors paradigm for allocation of data and control parametersSharing of MAPLE-B modules in multiple devices using SRIO‘GO’ command activation, no DSP core pre-processing or intervention are required
• Validation of full LTE chain functionality, uplink and downlink• Research, development and performance validation of algorithms (Channel Estimation,
MIMO Equalizer, RACH, HARQ Combining)3. StarCore C code implementation
• Code generation• Fixed point validation, feeding code back in Matlab with mexfiles• Target cycles measurements on MSC8156 simulator and ADS boards • Code optimization
4. Real time integration• Integration of all LTE Layer 1 Software Components• Validation of real time throughput and latency
LTE - FDD: • 20 MHz• 4x4 MIMO DL, up to 300 Mbps • 2x4 MIMO UL, MMSE MIMO Equalizer, up to 150 Mbps• 1 device DL, 1 device UL (+remote TVPE of DL device)• 1 master core per device for I/O and application scheduling
LTE - FDD: • 20 MHz• 4x4 MIMO DL, up to 300 Mbps • 2x4 MIMO UL, MMSE MIMO Equalizer, up to 150 Mbps• 1 device DL, 1 device UL (+remote TVPE of DL device)• 1 master core per device for I/O and application scheduling
DL Device:Cores: From transport block encoding down to
LTE - FDD: • 20 MHz• 4x4 MIMO DL, up to 300 Mbps • 2x4 MIMO UL, MMSE MIMO Equalizer, up to 150 Mbps• 1 device DL, 1 device UL (+remote TVPE of DL device)• 1 master core per device for I/O and application scheduling
►LTE standard designed for high throughput with 4x4 MIMO OFDMA in Downlink and 2x4 MIMO SC-FDMA in Uplink. Real challenge for:
• High signal processing complexity for advanced algorithms• Complex system SW architecture in multicore environment• Very high data rates and low latency systems
►Freescale LTE Layer1 enablement software components include • Advanced Signal Processing library with key algorithms• a Multicore Framework• all needed application & abstraction layers for a smooth integration
►Freescale DSP MSC8156: The MAPLE-B baseband accelerator together with the advanced StarCore cores provides key factor for current and future BaseBand systems design with very high data throughput and low latency requirements
►Thank you for attending this presentation. We’ll now take a few moments to review the audience questions, and then we’ll begin the question and answer session.