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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Big Endian - Most Significant Byte
Big Endian – Least Significant Byte
0 31 32 63
0x0 A B C D E F G H
0x8
0x10
MSb0
LSb31
General Purpose Register (GPR)
► All MPC560xB instructions are either 16 or 32 bits wide.► Power architecture is naturally Big Endian, but has switch for Little Endian► Examples:
Data Organization in Memory
Load word from address 0x0 loads the word “ABCD”Load half word from address 0x6 loads the half word “GH”
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Start-Up Sequence1. POR monitors internal voltage
and de-asserts itself
2. Default clock is the 16MHz IRC
3. Boot configuration pins are sampled by the hardware - possiblity to go into e.g. serial boot mode
4. Hardware checks reset configuration half word (RCHW)
5. If hardware finds a valid RCHW (0x5A) it reads the 32-bit word at offset 0x04 = address where Start-Up code is located (reset boot vector).
• Device is put in static mode if no RCHW is found!
• User transparent ECC encoding and decoding for byte, half word, and word accesses
• 32-bit ECC with single-bit correction (and visibility), double bit detection for data integrity
• ECC is checked on reads, calculated on writes
• CAUTION: ECC requires SRAM must be initialized by executing 32-bit write operations (32-bit word aligned) prior any read accesses
• Done in initialization code before main
FLASH features:
• Up to 1.5MB Code Flash (MPC5607B)
• Up to 64k Data Flash on MPC560xB; same emulated EEPROM concept for most products of the MPC560xB family (sectorization; software compatibility; memory mapping)
• 64-bit programming granularity (can change value from 10 only)
• Read-while-write with Code and Data Flash or by RWW feature
• Erase granularity is Sector size
• 64-bit ECC with single-bit correction (and visibility), double bit detection for data integrity
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Debug, Software & Tools RAppID: Rapid Application Initialization and Documentation
►RAppID PinWizard:• Wizard workflow to allocate pins to peripherals• Generates spreadsheet• Inputs to RAppID Init• Free utility
►RAppID Init:• Generates initialization code for startup from CRT0• Generates interrupt handler code & framework• Has ability to define section map and place code into any desired section
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
PeripheralsSIUL Introduction►Pad Control and IOMux configuration:
• Intended to configure the electrical parameters and I/O signal multiplexing of each pad;
• may simplify PCB design by multiple alternate input / output functions
►General Purpose I/O (GPIO) ports:• Can write to GPIO data output pin or port• Can read GPIO data input pin or port
►External interrupt management• Allows the enabling and configuration (such as
filtering window, edge and mask setting) of digital glitch filters on each external interrupt pin
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Peripherals SIUL Pad Control and IOMux configuration overview
►Pad Control is managed through Pad Configuration Registers (PCRs)
►GPIO pads can be managed two ways:• On individual base (R/W access to a single GPIO);
Access is done on a byte basis• On port base (parallel access).
►Ports accesses can be:• Data Read: 32-bit, 16-bit or 8-bit accesses• Data Write: 32-bit, 16-bit or 8-bit (only if not masked access)• Masked Access: This mechanism allows support for port accesses or
for bit manipulation without the need to use read-modify-write operations
Code example for writing to individual GPIO pin:SIU.PCR[68].B.PA = 0; /* Port E4 pin: Pad Assignment is GPIO */SIU.PCR[68].B.OBE = 1; /* Port E4 pin: Output Buffer Enabled */SIU.GPDO[68].R = 1; /* Port E4 pin: write 1 to Data Output */
• PLL clock monitoring : detect if PLL leaves an upper or lower frequency boundary
• Crystal clock monitoring : monitors the external crystal oscillator clock which must be greater than the internal RC clock divided by a division factor given by RCDIV[1:0] of CMU_CSR register.
• Frequency meter : measure the frequency of one clock source versus a reference clock.
• CMU “event” (failure) will cause reset, SAFE mode request or interrupt request
►The first task of the CMU is to permanently supervise the integrity of the various product’s clock sources, e.g. FXOSC or FMPLL, if either • FXOSC clock frequency lower than FIRC / 2n
• PLL clock frequency upper or lower frequency boundaries defined in CMU registers
►If an integrity problem occurs, the Mode Entry module is notified in order to switch to SAFE mode with FIRC as clock source.
►The second task is frequency measurement. It allows to measure the deviation of a clock (FIRC, SIRC or SXOSC ) by measuring its frequency versus FXOSC as reference clock. • Can be used to improve IRC calibration • Can be used for Real Time Counter precision
►Crystal clock monitor is active only when ME provides the info that FXOSC is valid
►If FXOSC < FIRC / 2RCDIV (CMU_CSR[RCDIV] bits), then• an event pending bit CMU_ISR[OLRI] is set.• a failure event is signaled to the RGM which in turn can generate a
RESET, transition to SAFE mode, or generate an interrupt request
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
CMU Ref.: Crystal Clock Monitor Event Behavior
►Oscillator Less than Reference event occurs when the FXOSC appears too slow and sets:► CMU_ISR[OLRI]
• No interrupt or other automatic action can be generated – just sets the bit
► RGM_FES[F_CMU_OLR]• Action taken is per table below:
Functional Event Reset Disable: FXOSC
freq. lower than reference
Functional Event Alternate Request:
Alternate Request for FXOSC freq. lower than reference
Use Case: Conserving Power While Software Runs (1 of 2)
►Software runs one of the three following tasks:• Analog Monitor
Uses ADC to look for particular voltages on inputs Only requires 16 MHz FIRC, which is also sysclk If analog input measurements meet a criteria, software transitions to the
communication task• Communication
Uses FlexCAN_0, FlexCAN_1 to transmit analog data and receive response Only requires FXOSC, which is also sysclk If response is positive, software transitions to the whole chip task
• Whole Chip Requires all peripherals active Sysclk = 64MHz FMPLL, which also requires FXOSC
►The Mode Entry Module (MC_ME) provides SYSTEM modes and USER modes :• SYSTEM: RESET, DRUN (Default RUN), SAFE and TEST• USER: RUN(0..3), HALT, STOP and STANDBY
►For each mode the following parameters are configured/controlled• System clock sources (ON/OFF)• System clock source selection• Flash power mode (ON, low power, power down)• Pad output driver state (For low power modes - can disable Pad Output
drivers, enabling high impedance mode)• Peripherals’ clock (gated/clocked)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
MC_ME Peripheral Configuration RegistersRUN Modes
Defines a selection of 8 possible RUN mode configurations for a peripheral
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Device Start-up: MC_ME Peripheral Control Registers
For each peripheral, there is a ME_PCTLx register to control clock gating to that peripheral:
- selects one of the 8 Run peripheral set configurations - selects one of the 8 Low Power peripheral set configurations- enables/disables freezing the clock during debug
►Software handled transition• A transition is requested writing a key protected sequence in ME_MCTL• Mode Entry configures the modules according to the ME_xxx_MC
register of the target mode• Once all modules are ready the new mode is entered• Transition completion signalling: status bit/interrupt• Note: Modification of a ME_xxx_MC register (even the current one) is
taken into account on next mode “xxx” entry
►Hardware triggered transition• Exit from low power mode• SAFE transition caused by HW failure• RESET transition caused by HW failure
Exercise: Initialize PLL & RUN Mode, Write GPIO Output
1. Open existing CodeWarrior Project, “PLL-sysclk”1. Navigate to the PLL-sysclk project for MPC560xB. Example path:
C: \ Program Files \ Freescale \ CW for MPC55xx and MPC56xx 2.7 \ (CodeWarrior_Examples) \ 560xB-CW \ PLL-sysclk
2. Double click on the project file “PLL-sysclk.mcp” to open it in CodeWarrior2. Compile and link RAM project
1. Either a) click: Project – Make – or-- b) click on the make icon3. Download to target
1. Connect EVB to PC with USB cable2. Either click: Project – Debug, or, click on the Debug icon3. Click the “Connect” button4. Type “gotil main” in the Status Window
4. Initialize registers to turn on LED1 on target board1. Click the “REG” button at the top2. Click “SIUL System Integration Unit Lite”3. Set bit fields for a GPIO output (PCR68: PA=1, OBE=1; GPDO68: PDO=1)4. Exit register windows then open again to validate the register was altered
Are registers still shown as modified? Execute thru initModesAndClock &re-try.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Programmable Interrupt Timer (PIT) Features
► Clocked by system clock► 32-bit counter ► Independent timeout periods for each timer► Timer can generate interrupt/DMA request, ADC conversion
► A and B data registers are double buffered to provide a mechanism for safe update of the A and B register values• This also enables very small pulse / period generation or measurement since updates can
happen in current period
► The channel A user registers are an address mapped link to either the A1 or A2 register (determined automatically by the mode of the unified channel).• For output modes, data is typically written to the A2 register• For input capture modes, data is latched into either A1 or A2 depending on mode.• All of this is transparent to the user
►The MPC560xB family has 5 shared counter busses allowing common counter bus timing across multiple channels• Counter Bus A is shared with all channels and
driven from channel 23• Counter bus B is shared with channels
0 to 7 and driven from channel 0• Counter bus C is shared with channels
8 to 15 and driven from channel 8• Counter bus D is shared with channels 16 to 23
and driven from channel 16• Counter bus E is shared with channels 24 to 27
Returns the value of the counter bus on an edge match of an input signal .‑ Can use Internal or Modulus counter‑ Can match on Rising, Falling or Toggle determined by state of EDPOL, EDSEL
Notes:• When edge is detected, flag is set and counter bus value is captured in register A2. User reads this
value from UCA[n] register.• UCB[n] = Cleared and cannot be written
Peripherals EMIOS - Modulus Counter Buffer Mode – UP Counter
Generates a time base which can be shared with other channels through the internal counter buses
‑ Can use Internal or External (input channel pin) counter
Notes:• On a comparator A match, FLAG is set and the internal counter is set to value $1.• Allowing smooth transitions, a change of the A2 register makes the A1 register be updated when the
internal counter reaches the value $1.• Caution – If when entering MCB mode the internal counter value is upper than register UCA[n] value,
then it will wrap at the maximum counter value ($FFFFFF) before matching A1.
Notes:• Duty Cycle = UCA[n] (A1) + 1, Period = UCB[n] (B1) + 1• On Comparator A1 match, Output pin is set to value of EDPOL• On Comparator B1 match, Output pin is set to complement of EDPOL and Internal counter is reset• The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle.• FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit.
$001000
$000200
$001000
B1 match
$001000
B1 match
0x0010000x000800
$000200
0x000200
B1 value
A1 value
Selected counter bus
A2 value
output flip-flopEDPOL=1
output flip-flopEDPOL=0
A1 match
$000200 $000800
update of A1
write into A2
$000800$000800
A1 match
$000200
A1 match
$000800
B1 match
$001000
Generates a simple output PWM signal‑ Requires INTERNAL Counter‑ EDPOL allows selection between active HIGH or active LOW duty cycle.
Generates a simple output PWM signal‑ Can use Internal or Modulus counter‑ EDPOL allows selection between active HIGH or active LOW duty cycle.
Notes:• Write UCA[n] (A1) with Leading Edge. Write UCB[n] (B1) with trailing edge• On Comparator A1 match, Output pin is set to value of EDPOL• On Comparator B1 match, Output pin is set to complement of EDPOL• The transfers from register B2[n] to B1[n] and from register A2[n] to A1[n] are performed at the first clock of the next cycle.• FLAGS can be generated only on B1 matches or on both A1 and B1 matches depending on MODE[5] bit.
Generates a PWM signal with a fixed offset and a trigger signal‑ Intended to be used with other channels in the same mode with shared common time base‑ This mode is particularly useful in the generation of lighting PWM control signals.
Notes:• A1[n] defines the Leading Edge, B1[n] the trailing edge, A2[n] the generation of a FLAG event• On Comparator A1 match, Output pin is set to value of EDPOL• On comparator A2 match, FLAG is set (and can allow to synchronize with other events, ie. AD conversion)• On Comparator B1 match, Output pin is set to complement of EDPOL• The transfers from register B2[n] to B1[n] is performed at every match of register A1
• Filter Consists of a 5 bit programmable up-counter, clocked by either the channel or peripheral set clock (defined by FCK)
• Input signal is synchronised to system clock.
• When the synchroniser output changes state, the counter starts counting up
• If the synchroniser state remains stable for the desired number of selected clocks, the counter overflows on next high clock edge, counter resets and filter output changes
5-Bit Up Counter
IF3 IF2 IF1 IF0FCK
Prescaled Channel CLK
Peripheral Set CLK
CLK
SynchroniserPIN
Filter Out
Filter can be set to trigger after 2,4,8 or 16 clocks (or bypassed)
Hardware context switch:1. Stores address of next instruction or instruction causing interrupt
• Stored into special purpose reg. Save & Restore Reg 0 (SRR0)2. Stores Machine State (MSR bits 16:31):
• Stored into special purpose reg. Save & Restore Reg 1 (SRR1)3. Alters Machine State: All bits are cleared in MSR except ME4. Alters Instruction Pointer: points to unique interrupt vector
Software Interrupt handler (at interrupt vector)• Execute your handler code, including save/restore registers• Last instruction, rfi*, (return from interrupt):
- Restores MSR bits 16:31 from SRR1- Restores instruction pointer from SRR0
* “Critical” and “debug” interrupts use rcfi and rdfi instruction instead of rfi.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
e200z0 Core Interrupts
►External input Exception (EE)► enables/disables all interrupts from the interrupt controller.
►Each exception type can normally be individually enabled or disabled in the Machine State Register (MSR)
• The interrupt vector address is composed of two components: Vector base address used as a prefix (special purpose register IVPR bits 0:19) A fixed offset base on the IVOR #
• Each interrupt vector address would contain your branch instruction to that handler.
► Interrupt sources are assigned 1 of 16 priority levels
• 15 is highest priority, 0 is lowest
• Each interrupt source’s priority is specified in its Priority Select Register (8 bits wide), INTC_PSRx
► The Interrupt Controller records the current interrupt’s priority.- The current priority is in the Current Priority Register, INTC_CPR- Only interrupts with a priority higher than current priority can be recognized, allowing preemption.
► Preempted priorities are automatically pushed/popped to/from a LIFO in the interrupt controller.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
ADC: Programmable Analog Watchdog
►4 to 6 Analog Watchdogs can monitor any ADC channel► Number depends on device implementation►Programmable UPPER and LOWER threshold►Dedicated ADC (WD) Interrupt on UPPER and/or LOWER threshold violation►Can be used in a lighting application to trim SMARTMOS devices to prolong LED life
• Use EMIOS (OPWMT mode) -> CTU -> ADC to continually monitor LED voltage• 0% CPU loading• Only use CPU in event of ADC watchdog interrupt
►Each channel has a data register containing:►VALID indication of new value written (cleared when read)►OVERWrite data indication that previous conversion data is
overwritten by a new conversion►RESULT indication of conversion mode: normal, injected, CTU►CDATA with channel’s converted data value
►Each ADC converter has two interrupt vectors to the INTC:►ADC_EOC: ADC End of conversion
• End of (normal) chain conversion• End of (normal) channel conversion (channels selected separately)• End of injected chain conversion• End of injected channel conversion• End of CTU conversion
►ADC_WD: ADC watchdog• Watchdog0:3 or 5 high thresholds exceeded • Watchdog0:3 or 5 low thresholds exceeded
Definitions:PWM 200Hz (0.35% resolution, xybit)MDDC: 8% (Min Diag Duty Cycle: For Duty cycles <8% no diagnosis is required)tchd: 1ms (Channel Delay to control inrush current as well as EMC on ECU level)tirsd: 300us (Inrush Delay to ensure ADC measurement takes place once current is stable)tdwmin: 100us (Diagnosis Window = Min. Diag. Duty Cycle – Inrush Delay)
Calculations:200Hz 5ms Period MDDC = 8% of 5ms = 400us tdwmin = MDDC – tirsdtdwmin = 400us -300us = 100us
Period: the period of the PWM is defined by a Modulus Counter channel.
A1 Value: define the leading edge (or shift) of the PWM channel. Buffering is not needed as the value of the shift must not changed on the fly.B1 Value: define the trailing edge (or duty cycle) of the PWM channelB2 Value: buffered value of trailing edgeB1 update: transfer from B2 to B1 takes place at A1 matchEDPOL: define the output polarityA2 Value: define the sampling point for the analog diagnostic. It can be configured anywhere within the PWM period.
• Software selects which DMA sources connect to the 16 DMA channels• DMA request for channels can be initiated by:
• A peripheral (example: ADC conversion result ready to be put into queue)• Software (example: set a bit to initiate a block move)• Periodic Interval Timer (example: enable periodic transmit of latest pending SPI data)
• Periodic Interval Timer available to 4 of the 16 channels (DMA channel 0 to 3)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
eDMA Mux: Channel Mux Source Options
DMA MuxSource Input #
#sources
DMA Source
0 1 Channel Disabled
1 – 12 12 6x DSPIs : transmit, receive
13 – 24 12 6x eMIOS_A / 6x eMIOS_B channels
25 1 ADC_0 10-bit converion complete
26 1 ADC_1 12-bit conversion complete
27-28 2 IIC_A receive, transmit
29 - 32 4 Always Enabled - with PIT to generate periodic DMA - w/o PIT for continuous DMA transfer
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
eDMA: Transfer Control Descriptor (TCD) Introduction ► One Transfer Control Descriptor (TCD) for each channel:
• Source, Destination addresses• Separate Size for each read and write access• Number of transfers per DMA request• Total number of DMA requests serviced before stop or restart.• Signed restart address adjustment• Last Source Address Adjustment and Last Destination Address Adjustment• Scatter/Gather support
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
eDMA: Modulo Feature► Provides the ability to easily implement a circular data queue
• Size of queue is a power of 2► mod, a 5-bit bit field, specifies which lower address bits are allowed to increment from
their original value after the address + offset calculation• all upper address bits remain the same as in the original value. • If mod = 0 disables modulo feature
► Example: source address = 0x12345670; offset is 4 bytes so mod=4, allowing for a 24 byte (16-byte) size queue
► Allows a DMA channel to use multiple TCDs• Enables a DMA channel to scatter the DMA data to multiple destinations or
gather it from multiple sources• Example use: linked list of LIN messages
Example: TCD A(in flash or SRAM)
sga (Scatter Gather Address)
TCD B(in flash or SRAM)
sga
Sequence:1. Initialization: Load TCD A from flash to DMA channel x’s TCD2. 1st DMA request or START=1: Executes TCD A; TCD B loads automatically3. 2nd DMA request or START=1: Executes TCD B; TCD A loads automaticallyOption: TCD B could automatically execute with the 1st DMA request if the TCD’s start bit is
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
eDMA: Channel Linking
► A DMA channel can “link” to another DMA channel, i.e, set the start bit of a 2nd TCD• At the end of every minor loop (except the last one)• And/or, at the end of the major loop
► Also enables linked lists
Desired Link Behavior
TCD Control Field Name
Description
Link at end of Minor Loop
citer.e_link Enable channel-to-channel linking on minor loop completion (current iteration)
citer.linkch Link channel number when linking at end of minor loop (current iteration)
Link at end of Major Loop
major.e_link Enable channel-to-channel linking on major loop completion
major.linkch Link channel number when linking at end of major loop
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
eDMA: Other Control & Status Fields (1 of 2)
TCD Control Field Name
Description
start Control bit to explicitly start channel when using a software initiated DMA service. (Automatically cleared by hardware after service begins.)(Note: Do not set START if DMA request comes from HW)
active Status bit indicating the channel is currently in execution.
done Status bit indicating major loop completion. (Set by hardware as CITER reaches 0. Cleared by software if using software initiated DMA service request.)
d_req Control bit to disable DMA request at end of major loop completion.• Clears channel enable bit, DMAERQ, at major loop completion so no additional DMA requests are recognized until channel is enabled again (Important for FIFOs – later)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
eDMA: Other Control & Status Fields (2 of 2)
TCD Control Field Name
Description
BWC[0:1] Control bits for “throttling” bandwidth control of a channel.
e_sg Control bit to enable scatter-gather feature.
int_half Control bit to enable interrupt when major loop is half complete (DONE = 0)
int_major Control bit to enable interrupt when major loop completes (DONE = 1)
BWC - Bandwidth ControlForces the eDMA to stall after the completion of each read/write access to control the bus request bandwidth seen by the crossbar.
00 No DMA_Engine stalls (for inner loop)01 reserved10 DMA_Engine stalls for 4 cycles after each R/W11 DMA_Engine stalls for 8 cycles after each R/W
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
eDMA: Summary
• Transfer Control Descriptor - 32-bytes of local memory.
• 32-bit Source and Destination addresses
• Transfer attributes selects the size increment/decrement options.
• Iteration (minor loop) counter – runs to zero every activation.
0 0 0 00 0 0 0
SSTRTQ[6:0]
A write value of 15, sets correspondingStart bit in TCD_15 descriptor
DMASSTRT – DMA Set Start Request
0 0 0 00 0 0 0
CDONE[6:0]
A write value of 15, clears correspondingDone bit in TCD_15 descriptor
DMACDONE – DMA Clear Done Status
A value greater than 63 written willSet or clear Start and Done Bits, respectively
Source Address (saddr)
Signed Source Address Offset(soff)
Transfer Attributes(smod, ssize, dmod, dsize)
Inner “Minor” Byte Count (nbytes)
Last Source Address Adjustment (slast)
Destination Address (daddr)
Current Iteration Count (citer) and optional channel link
Channel Linking Note: When the DMA executes a channel link, it sets the START bit of the target (link) channel. Then, the arbitration pipeline is flushed. At this point, the target channel is in the arbitration pool with all other channels requesting service. Arbitration occurs and the highest priority channel requesting service is selected to execute. Thus higher priority channels will not be starved.
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
• DMA is triggered on falling edges at CADR capture) • DMA stores timing values (timebase is i.e internal counter) from CADR/CBDR into RAM• Interrupt generation at the end of major loop
• DMA is triggered on falling edges at CADR capture) • DMA stores timing values (timebase is i.e internal counter) from CADR/CBDR into RAM• Interrupt generation at the end of major loop
.
.
.
INT_MAJEnable an interrupt when major iteration count completes.
Capture waveforms using eMIOS and DMA
saddr (source address) = eMIOS CADR register
daddr (destination addr.) = start of memory queue
nbytes = 4 bytes (minor loop size; # bytes per request) biter = citer = 8 (# minor loops in major loop) d_req = 0 (keep channel enabled after major loop)
ssize = 16 bits (read 1 halfword per transfer)soff = 4 bytes (src. addr. increment after transfer)slast = 0 (no src. addr. adjustment when done)smod = 3 (wrap address after each minor loop)
dsize = 16 bits (write 1 half word per transfer)doff = 2 bytes (add 4 to dest. addr after each transfer)dlast = -32 bytes (restart daddr to start when done)dmod = 0 (disbaled)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently arenot available from Freescale for import or sale in the United States prior to September 2010: MPC560xB products in 208 MAPBGA packages
PWM C1 Rising
PWM C1 Falling
PWM C2 Rising
PWM C2 Falling
PWM C3 Rising
PWM C3 Falling
PWM C4 Rising
PWM C4 Falling
PWM C5 Rising
PWM C5 Falling
PWM C6 Rising
PWM C6 Falling
PWM C7 Rising
PWM C7 Falling
PWM C8 Rising
PWM C8 Falling
Destination16 bit register
eMIOSCADR register
eMIOSCBDR register
• Waveform Period is defined by timebase – Unified Channel in MCB period• eMIOS is working in Double Action Output Compare Mode (DAOC) – CADR is programmed to trigger
rising edge on timebase match, CBDR is programmed to trigger falling edge on timebase match • FLAG is set on second match and triggers DMA to write next waveform falling & rising edges to
CADR/CBDR • Interrupt generation at the end of major loop
• Waveform Period is defined by timebase – Unified Channel in MCB period• eMIOS is working in Double Action Output Compare Mode (DAOC) – CADR is programmed to trigger
rising edge on timebase match, CBDR is programmed to trigger falling edge on timebase match • FLAG is set on second match and triggers DMA to write next waveform falling & rising edges to
CADR/CBDR • Interrupt generation at the end of major loop
.
.
.
INT_MAJEnable an interrupt when major iteration count completes.
Generate waveforms using eMIOS and DMA
saddr (source address) = start of memory queue
daddr (destination addr.) = eMIOS CADR register
nbytes = 4 bytes (minor loop size; # bytes per request) biter = citer = 8 (# minor loops in major loop) d_req = 0 (keep channel enabled after major loop)
ssize = 16 bits (read 1 halfword per transfer)soff = 2 bytes (src. addr. increment after transfer)slast = -32 (restart saddr to start when done)smod = 0 (disbaled)
dsize = 16 bits (write 1 half word per transfer)doff = 4 bytes (add 4 to dest. addr after each transfer)dlast = 0 bytes (disable)dmod = 3 (wrap address after each minor loop)