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� Controlled Baseline− One Assembly/Test Site, One Fabrication
Site
� Extended Temperature Performance of−40°C to 125°C
� Also Available in −55°C to 125°C� Enhanced Diminishing Manufacturing
Sources (DMS) Support
� Enhanced Product-Change Notification
� Qualification Pedigree†
� Supply Current . . . 300 μA Max† Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extendedtemperature range. This includes, but is not limited to, HighlyAccelerated Stress Test (HAST) or biased 85/85, temperaturecycle, autoclave or unbiased HAST, electromigration, bondintermetallic life, and mold compound life. Such qualificationtesting should not be viewed as justifying use of this componentbeyond specified performance and environmental limits.
� High Unity-Gain Bandwidth . . . 2 MHz Typ
� High Slew Rate . . . 0.45 V/μs Min
� Supply-Current Change Over Full TempRange . . . 10 μA Typ at VCC ± = ± 15 V
� Specified for Both 5-V Single-Supply and±15-V Operation
� Phase-Reversal Protection
� High Open-Loop Gain . . . 6.5 V/μV(136 dB) Typ
� Low Offset Voltage . . . 100 μV Max
� Offset Voltage Drift With Time0.005 μV/mo Typ
� Low Input Bias Current . . . 50 nA Max
� Low Noise Voltage . . . 19 nV/√Hz Typ
description
The TLE202x and TLE202xA devices are precision, high-speed, low-power operational amplifiers using a newTexas Instruments Excalibur process. These devices combine the best features of the OP21 with highlyimproved slew rate and unity-gain bandwidth.
The complementary bipolar Excalibur process utilizes isolated vertical pnp transistors that yield dramaticimprovement in unity-gain bandwidth and slew rate over similar devices.
The addition of a bias circuit in conjunction with this process results in extremely stable parameters with bothtime and temperature. This means that a precision device remains a precision device even with changes intemperature and over years of use.
This combination of excellent dc performance with a common-mode input voltage range that includes thenegative rail makes these devices the ideal choice for low-level signal conditioning applications in eithersingle-supply or split-supply configurations. In addition, these devices offer phase-reversal protection circuitrythat eliminates an unexpected change in output states when one of the inputs goes below the negative supplyrail.
A variety of options are available in small-outline packaging for high-density systems applications.
The Q-suffix devices are characterized for operation over the full automotive temperature range of −40°C to125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
300 μV SOIC (D) Tape and reel TLE2021AQDREP 2021AE
500 μV SOIC (D) Tape and reel TLE2021QDREP 2021QE
40°C to 125°C300 μV SOIC (D) Tape and reel TLE2022AQDREP 2022AE
−40°C to 125°C500 μV SOIC (D) Tape and reel TLE2022QDREP 2022QE
750 μV SOP (DW) Tape and reel TLE2024AQDWREP 2024AE
1000 μV SOP (DW) Tape and reel TLE2024QDWREP 2024QE
−55°C to 125°C 500 μV SOIC (D) Tape and reel TLE2021MDREP 2021ME† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC +, and VCC− .2. Differential voltages are at IN+ with respect to IN−. Excessive current flows if a differential input voltage in excess of approximately
±600 mV is applied between the inputs unless some limiting resistance is used.3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.4. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Selecting the maximum of 150°C can affect reliability.5. The package thermal impedance is calculated in accordance with JESD 51-7.
Supply currentchange over operatingtemperature range
VO = 2.5 V, No load
Full range 9 9 μA
† Full range is −40°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
TLE2021 electrical characteristics at specified free-air temperature, VCC = 5 V (unless otherwisenoted)
PARAMETER TEST CONDITIONS T †TLE2021MDREP
UNITPARAMETER TEST CONDITIONS TA†
MIN TYP MAXUNIT
25°C 120 600V I t ff t lt
25°C 120 600VVIO Input offset voltage
25 C 120 600μVVIO Input offset voltage
Full range 850μV
αVIO Temperature coefficient of input offset voltage Full range 2 μV/°C
Input offset voltage long-term drift (see Note 4)VIC = 0 RS = 50 Ω 25°C 0.005 μV/mo
I Input offset current
VIC = 0, RS = 50 Ω25°C 0.2 6
nAIIO Input offset currentFull range 10
nA
I Input bias current25°C 25 70
nAIIB Input bias currentFull range 90
nA
V Common mode input voltage range R 50 Ω
25°C0to
3.5
−0.3to4
VVICR Common-mode input voltage range RS = 50 Ω
Full range0to
3.2
V
V High level output voltage25°C 4 4.3
VVOH High-level output voltage
R 10 kΩFull range 3.8
V
V Low level output voltage
RL = 10 kΩ25°C 0.7 0.8
VVOL Low-level output voltageFull range 0.95
V
A Large signal differential voltage amplification V 1 4 V to 4 V R 10 kΩ25°C 0.3 1.5
V/ VAVD Large-signal differential voltage amplification VO = 1.4 V to 4 V, RL = 10 kΩFull range 0.1
V/μV
CMRR Common mode rejection ratio V V min R 50 Ω25°C 85 110
dBCMRR Common-mode rejection ratio VIC = VICRmin, RS = 50 ΩFull range 80
dB
k Supply voltage rejection ratio (ΔV /ΔV ) V 5 V to 30 V25°C 105 120
dBkSVR Supply-voltage rejection ratio (ΔVCC ± /ΔVIO) VCC = 5 V to 30 VFull range 100
dB
I Supply current25°C 170 300
AICC Supply currentVO = 2 5 V No load
Full range 300μA
ΔICCSupply current change over operatingtemperature range
VO = 2.5 V, No load
Full range 9 μA
† Full range is −55°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
kSupply-voltage rejection ratio V ± 2 5 V to ±15 V
25°C 105 120 105 120dBkSVR rejection ratio
(ΔVCC ± /ΔVIO)VCC ± = ± 2.5 V to ±15 V
Full range 100 100dB
I Supply current25°C 200 350 200 350
AICC Supply currentFull range 350 350
μA
ΔICC
Supply currentchange over operating temperaturerange
VO = 0, No load
Full range 10 10 μA
† Full range is −40°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
TLE2021 electrical characteristics at specified free-air temperature, VCC = ±15 V (unless otherwisenoted)
PARAMETER TEST CONDITIONS T †TLE2021MDREP
PARAMETER TEST CONDITIONS TA†
MIN TYP MAX UNIT
25°C 120 500V I t ff t lt
25°C 120 500VVIO Input offset voltage
25 C 120 500μVVIO Input offset voltage
Full range 800μV
αVIO Temperature coefficient of input offset voltage Full range 2 μV/°C
Input offset voltage long-term drift (see Note 4)VIC = 0 RS = 50 Ω 25°C 0.006 μV/mo
I Input offset current
VIC = 0, RS = 50 Ω25°C 0.2 6
nAIIO Input offset currentFull range 10
nA
I Input bias current25°C 25 70
nAIIB Input bias currentFull range 90
nA
V Common mode input voltage range R 50 Ω
25°C−15
to13.5
−15.3to14
VVICR Common-mode input voltage range RS = 50 Ω
Full range−15
to13.5
V
V Maximum positive peak output voltage swing25°C 14 14.3
VVOM+ Maximum positive peak output voltage swing
R 10 kΩFull range 13.8
V
V Maximum negative peak output voltage swing
RL = 10 kΩ25°C −13.7 −14.1
VVOM− Maximum negative peak output voltage swingFull range −13.6
V
A Large signal differential voltage amplification V ±0 V R 10 kΩ25°C 1 6.5
V/ VAVD Large-signal differential voltage amplification VO = ±0 V, RL = 10 kΩFull range 0.5
V/μV
CMRR Common mode rejection ratio V V min R 50 Ω25°C 100 115
dBCMRR Common-mode rejection ratio VIC = VICRmin, RS = 50 ΩFull range 96
dB
k Supply voltage rejection ratio (ΔV /ΔV ) V ± 2 5 V to ±ℑ° V25°C 105 120
dBkSVR Supply-voltage rejection ratio (ΔVCC ± /ΔVIO) VCC± = 2.5 V to ±ℑ° VFull range 100
dB
I Supply current25°C 200 350
AICC Supply currentVO = 0 No load
Full range 350μA
ΔICCSupply current change over operatingtemperature range
VO = 0, No load
Full range 10 μA
† Full range is −55°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
dBkSVRSupply voltage rejection ratio (ΔVCC ± /ΔVIO) VCC = 5 V to 30 V
Full range 95 98dB
I Supply current25°C 450 600 450 600
AICC Supply currentFull range 600 600
μA
ΔISupply current change overoperating temperature
VO = 2.5 V, No load
Full range 37 37 μAΔICC operating temperaturerange
Full range 37 37 μA
† Full range is −40°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
dBkSVRSupply voltage rejectionratio (ΔVCC ± /ΔVIO) VCC ± = ±2.5 V to ±15 V
Full range 95 98dB
I Supply current25°C 550 700 550 700
AICC Supply currentFull range 700 700
μA
ΔISupply current changeover operating
VO = 0, No load
Full range 60 60 μAΔICC over operating temperature range
Full range 60 60 μA
† Full range is −40°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
dBkSVRSupply voltage rejectionratio (ΔVCC± /ΔVIO) VCC ± = ±2.5 V to ±15 V
Full range 93 95dB
I Supply current25°C 800 1200 800 1200
AICC Supply currentFull range 1200 1200
μA
ΔICC
Supply current changeover operating temperature range
VO = 0, No load
Full range 50 50 μA
† Full range is −40°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
dBkSVRSupply voltage rejectionratio (ΔVCC ± /ΔVIO) VCC ± = ±2.5 V to ±15 V
Full range 93 95dB
I Supply current25°C 1050 1400 1050 1400
AICC Supply currentFull range 1400 1400
μA
ΔISupply current changeover operating
VO = 0, No load
Full range 85 85 μAΔICC over operating temperature range
Full range 85 85 μA
† Full range is −40°C to 125°C.NOTE 4: Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
to TA = 25°C using the Arrhenius equation and assuming an activation energy of 0.96 eV.
The TLE202x circuitry includes input-protection diodes to limit the voltage across the input transistors; however,no provision is made in the circuit to limit the current if these diodes are forward biased. This condition can occurwhen the device is operated in the voltage-follower configuration and driven with a fast, large-signal pulse. Itis recommended that a feedback resistor be used to limit the current to a maximum of 1 mA to preventdegradation of the device. This feedback resistor forms a pole with the input capacitance of the device. Forfeedback resistor values greater than 10 kΩ, this pole degrades the amplifier phase margin. This problem canbe alleviated by adding a capacitor (20 pF to 50 pF) in parallel with the feedback resistor (see Figure 71).
CF = 20 pF to 50 pF
IF ≤ 1 mA
RF
VCC +
VCC−
VO
VI
−
+
Figure 71. Voltage Follower
Input offset voltage nulling
The TLE202x series offers external null pins that further reduce the input offset voltage. The circuit inFigure 72 can be connected as shown if this feature is desired. When external nulling is not needed, the nullpins may be left disconnected.
Macromodel information provided was derived using Microsim Parts™, the model generation software usedwith Microsim PSpice™. The Boyle macromodel (see Note 5) and subcircuit in Figure 73, Figure 74, andFigure 75 were generated using the TLE202x typical electrical and operating characteristics at 25°C. Using thisinformation, output simulations of the following key parameters can be generated to a tolerance of 20% (in mostcases):
� Unity-gain frequency� Common-mode rejection ratio� Phase margin� DC output resistance� AC output resistance� Short-circuit output current limit
� Maximum positive output voltage swing� Maximum negative output voltage swing� Slew rate� Quiescent power dissipation� Input bias current� Open-loop voltage amplification
NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”, IEEE Journalof Solid-State Circuits, SC-9, 353 (1974).
OUT
+
−
+
−
+
−
+
−+
−
+
− +
−
+−
VCC +
rp
IN−
2IN+
1
VCC−
rc1
11
Q1 Q2
13
cee Iee
3
12
rc2
ve
54de
dp
vc
dc
4
C1
53
r2
6
9
egnd
vb
fb
C2
gcm gavlim
8
5ro1
ro2
hlim
90
dip
91
din92
vinvip
99
7
ree
14
re1 re2
Figure 73. Boyle Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
rc1 4 11 2.842E3rc2 4 12 2.842E3ge1 13 10 (10,13) 31.299E−3ge2 14 10 (10,14) 31.299E−3ree 10 99 11.07E6ro1 8 5 250ro2 7 99 250rp 3 4 137.2E3vb 9 0 dc 0vc 3 53 dc 1.300ve 54 4 dc 1.500vlim 7 8 dc 0vlp 91 0 dc 3vln 0 92 dc 3
.model dx d(is=800.0E−18)
.model qx pnp(is=800.0E−18 bf=257.1)
.ends
Figure 75. Boyle Macromodel for the TLE2022
PACKAGE OPTION ADDENDUM
www.ti.com 31-May-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
TLE2021AQDREP ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2021AE
TLE2021MDREP ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 2021ME
TLE2021QDREP ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2021QE
TLE2022AQDREP ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2022AE
TLE2022QDREP ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2022QE
TLE2024AQDWREP ACTIVE SOIC DW 16 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2024AE
TLE2024QDWREP ACTIVE SOIC DW 16 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2024QE
V62/04755-01XE ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2021AE
V62/04755-02XE ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2021QE
V62/04755-03XE ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2022AE
V62/04755-04XE ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2022QE
V62/04755-05YE ACTIVE SOIC DW 16 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2024AE
V62/04755-06YE ACTIVE SOIC DW 16 2000 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2024QE
V62/04755-07XE ACTIVE SOIC D 8 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -55 to 125 2021ME
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLE2021-EP, TLE2021A-EP, TLE2022-EP, TLE2022A-EP, TLE2024-EP, TLE2024A-EP :
Images above are just a representation of the package family, actual package may vary.Refer to the product data sheet for package details.
DW 16 SOIC - 2.65 mm max heightSMALL OUTLINE INTEGRATED CIRCUIT
4040000-2/H
www.ti.com
PACKAGE OUTLINE
C
TYP10.639.97
2.65 MAX
14X 1.27
16X 0.510.31
2X8.89
TYP0.330.10
0 - 80.30.1
(1.4)
0.25GAGE PLANE
1.270.40
A
NOTE 3
10.510.1
BNOTE 4
7.67.4
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016ASOIC
NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.5. Reference JEDEC registration MS-013.
1 16
0.25 C A B
98
PIN 1 IDAREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL ATYPICAL
SCALE 1.500
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAXALL AROUND
0.07 MINALL AROUND
(9.3)
14X (1.27)
R0.05 TYP
16X (2)
16X (0.6)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016ASOIC
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASKOPENING
NON SOLDER MASKDEFINED
SOLDER MASK DETAILS
OPENINGSOLDER MASK METAL
SOLDER MASKDEFINED
LAND PATTERN EXAMPLESCALE:7X
SYMM
1
8 9
16
SEEDETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
R0.05 TYP
16X (2)
16X (0.6)
14X (1.27)
(9.3)
4220721/A 07/2016
SOIC - 2.65 mm max heightDW0016ASOIC
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
SCALE:7X
SYMM
SYMM
1
8 9
16
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TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OFPRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.