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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.
1 Features1• Low Power Consumption• Wide Common-Mode and Differential Voltage
Ranges• Low Input Bias and Offset Currents• Output Short-Circuit Protection• Low Total Harmonic Distortion: 0.003% (Typical)• Low Noise
Vn = 18 nV/√Hz (Typical) at f = 1 kHz• High-Input Impedance: JFET Input Stage• Internal Frequency Compensation• Latch-Up-Free Operation• High Slew Rate: 13 V/μs (Typical)• Common-Mode Input Voltage Range
Includes VCC+
2 Applications• Motor Integrated Systems: UPS• Drives and Control Solutions: AC Inverter and VF
Drives• Renewables: Solar Inverters• Pro Audio Mixers• DLP Front Projection System• Oscilloscopes
3 DescriptionThe TL07xx JFET-input operational amplifiersincorporate well-matched, high-voltage JFET andbipolar transistors in a monolithic integrated circuit.The devices feature high slew rates, low-input biasand offset currents, and low offset-voltagetemperature coefficient. The low harmonic distortionand low noise make the TL07x series ideally suitedfor high-fidelity and audio pre-amplifier applications.The TL071 device has offset pins to support externalinput offset correction.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TL07xxDSOIC (14) 8.65 mm × 3.91 mmSOIC (8) 4.90 mm x 3.90 mm
TL07xxJG CDIP (8) 9.59 mm x 6.67 mmTL074xJ CDIP (14) 19.56 mm × 6.92 mmTL07xxP PDIP (8) 9.59 mm x 6.35 mmTL07xxPS SO (8) 6.20 mm x 5.30 mmTL074xN PDIP (14) 19.3 mm × 6.35 mmTL074xNS SO (14) 10.30 mm × 5.30 mmTL07xxPW TSSOP (8) 4.40 mm x 3.00 mmTL074xPW TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum atthe end of the data sheet.
8 Application and Implementation ........................ 288.1 Application Information............................................ 288.2 Typical Application .................................................. 288.3 Unity Gain Buffer..................................................... 298.4 System Examples ................................................... 30
9 Power Supply Recommendations ...................... 3210 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 3210.2 Layout Example .................................................... 33
11 Device and Documentation Support ................. 3411.1 Documentation Support ........................................ 3411.2 Related Links ........................................................ 3411.3 Community Resources.......................................... 3411.4 Trademarks ........................................................... 3411.5 Electrostatic Discharge Caution............................ 3411.6 Glossary ................................................................ 34
12 Mechanical, Packaging, and OrderableInformation ........................................................... 35
4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (February 2014) to Revision N Page
• Updated data sheet text to latest documentation and translation standards ......................................................................... 1• Added TL072M and TL074M devices to data sheet ............................................................................................................. 1• Rewrote text in Description section ....................................................................................................................................... 1• Changed TL07x 8-pin PDIP package to 8-pin CDIP package in Device Information table .................................................. 1• Deleted 20-pin LCCC package from Device Information table ............................................................................................. 1• Added 2017 copyright statement to front page schematic ..................................................................................................... 1• Deleted TL071x FK (LCCC) pinout drawing and pinout table in Pin Configurations and Functions section ........................ 4• Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................................... 5• Deleted differential input voltage parameter from Absolute Maximum Ratings table ......................................................... 10• Deleted table notes from Absolute Maximum Ratings table ............................................................................................... 10• Added new table note to Absolute Maximum Ratings table ................................................................................................ 10• Changed minimum supply voltage value from –18 V to –0.3 V in Absolute Maximum Ratings table ................................. 10• Changed maximum supply voltage from 18 V to 36 V in Absolute Maximum Ratings table ............................................... 10• Changed minimum input voltage value from –15 V to VCC– – 0.3 V in Absolute Maximum Ratings table........................... 10• Changed maximum input voltage from 15 V to VCC– + 36 V in Absolute Maximum Ratings table....................................... 10• Added input clamp current parameter to Absolute Maximum Ratings table ....................................................................... 10• Changed common-mode voltage maximum value from VCC+ – 4 V to VCC+ in the Recommended Operating
Revision History (continued)• Changed devices in Recommended Operating Conditions table from TL07xA and TL07xB to TL07xAC and
TL07xBC .............................................................................................................................................................................. 10• Added TL07xI operating free-air temperature minimum value of –40°C to Recommended Operating Conditions table ... 10• Added U (CFP) package thermal values to Thermal Information: TL072x (cont.) table ...................................................... 11• Added W (CFP) package thermal values to Thermal Information: TL074x (cont.) table ..................................................... 12• Added Figure 20 to Table 1 ................................................................................................................................................. 20• Added Figure 20 to Typical Characteristics section ............................................................................................................. 24• Added second Typical Application section application curves ............................................................................................ 29• Reformatted document references in Layout Guidelines section ........................................................................................ 32• Updated formatting of document reference in Related Documentation section .................................................................. 34
Changes from Revision L (February 2014) to Revision M Page
• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature Descriptionsection, Device Functional Modes, Application and Implementation section, Power Supply Recommendationssection, Layout section ........................................................................................................................................................... 1
• Moved Typical Characteristics into Specifications section. ................................................................................................. 20
Changes from Revision K (January 2014) to Revision L Page
• Moved Tstg to Handling Ratings table .................................................................................................................................. 10• Added Device and Documentation Support section............................................................................................................. 34• Added Mechanical, Packaging, and Orderable Information section..................................................................................... 34
Changes from Revision J (March 2005) to Revision K Page
• Updated document to new TI datasheet format - no specification changes. ......................................................................... 1• Added ESD warning ............................................................................................................................................................. 34
TL072x D, JG, P, PS and PW Package8-Pin SOIC, CDIP, PDIP, SO
Top View
Pin Functions: TL072xPIN
I/O DESCRIPTIONNAME NO.1IN– 2 I Inverting input1IN+ 3 I Noninverting input1OUT 1 O Output2IN– 6 I Inverting input2IN+ 5 I Noninverting input2OUT 7 O OutputVCC– 4 — Power supplyVCC+ 8 — Power supply
I/O DESCRIPTIONNAME NO.1IN– 3 I Inverting input1IN+ 4 I Noninverting input1OUT 2 O Output2IN– 7 I Inverting input2IN+ 6 I Noninverting input2OUT 8 O OutputNC 1, 10 — Do not connectVCC– 5 — Power supplyVCC+ 9 — Power supply
I/O DESCRIPTIONNAME NO.1IN– 5 I Inverting input1IN+ 7 I Noninverting input1OUT 2 O Output2IN– 15 I Inverting input2IN+ 12 I Noninverting input2OUT 17 O Output
TL074 D, N, NS, PW, J, and W Packages14-Pin SOIC, PDIP, SO, TSSOP, CDIP and CFP
Top View
Pin Functions: TL074xPIN
I/O DESCRIPTIONNAME NO.1IN– 2 I Inverting input1IN+ 3 I Noninverting input1OUT 1 O Output2IN– 6 I Inverting input2IN+ 5 I Noninverting input2OUT 7 O Output3IN– 9 I Inverting input3IN+ 10 I Noninverting input3OUT 8 O Output4IN– 13 I Inverting input4IN+ 12 I Noninverting input4OUT 14 O OutputVCC– 11 — Power supplyVCC+ 4 — Power supply
I/O DESCRIPTIONNAME NO.1IN– 3 I Inverting input1IN+ 4 I Noninverting input1OUT 2 O Output2IN– 9 I Inverting input2IN+ 8 I Noninverting input2OUT 10 O Output3IN– 13 I Inverting input3IN+ 14 I Noninverting input3OUT 12 O Output4IN– 19 I Inverting input4IN+ 18 I Noninverting input4OUT 20 O Output
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under Recommended OperatingConditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Differential voltage only limited by input voltage.(3) The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the dissipation
rating is not exceeded.
6 Specifications
6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITVCC+ - VCC– Supply voltage –0.3 36 VVI Input voltage (2) VCC– – 0.3 VCC– + 36 VIIK Input clamp current –50 mA
Duration of output short circuit (3) UnlimitedTJ Operating virtual junction temperature 150 °C
Case temperature for 60 seconds - FK package 260 °CLead temperature 1.8 mm (1/16 inch) from case for 10 seconds 300 °C
Tstg Storage temperature –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD RatingsVALUE UNIT
V(ESD) Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) VCC+ and VCC– are not required to be of equal magnitude, provided that the total VCC (VCC+ – VCC–) is between 10 V and 30 V.
6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)
MIN MAX UNITVCC+ Supply voltage (1) 5 15 VVCC– Supply voltage (1) –5 –15 VVCM Common-mode voltage VCC– + 4 VCC+ V
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.(2) Full range is TA = 0°C to 70°C.(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature aspossible.
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.(2) Full range is TA = 0°C to 70°C.(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature aspossible.
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.(2) Full range is TA = 0°C to 70°C.(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature aspossible.
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.(2) TA = –40°C to 85°C.(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 1. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature aspossible.
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, asshown in Figure 1. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must beused.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range isTA = –55°C to +125°C.
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, asshown in Figure 1. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must beused .
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range isTA = –55°C to +125°C.
6.15 Electrical Characteristics: TL074MVCC± = ±15 V (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) (2) MIN TYP MAX UNIT
VIO Input offset voltage VO = 0RS = 50 Ω
TA = 25°C 3 9mV
TA = Full range 15
αVIOTemperature coefficientof input offset voltage VO = 0, RS = 50 Ω TA = Full range 18 μV/°C
IIO Input offset current VO = 0TA = 25°C 5 100 pATA = Full range 20 nA
IIB Input bias current VO = 0TA = 25°C 65 200 pATA = Full range 20 nA
VICRCommon-mode inputvoltage range TA = 25°C ±11 –12 to 15 V
VOMMaximum peak outputvoltage swing
RL = 10 kΩ TA = 25°C ±12 ±13.5VRL ≥ 10 kΩ
TA = Full range±12
RL ≥ 2 kΩ ±10
AVDLarge-signal differentialvoltage amplification
VO = ±10 VRL ≥ 2 kΩ
TA = 25°C 35 200V/mV
TA = Full range 15B1 Unity-gain bandwidth 3 MHzri Input resistance 1012 Ω
CMRR Common-mode rejectionratio
VIC = VICR(min)VO = 0RS = 50 Ω
TA = 25°C 80 86 dB
kSVRSupply-voltage rejectionratio (ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 VVO = 0RS = 50 Ω
TA = 25°C 80 86 dB
ICCSupply current(each amplifier) VO = 0; no load TA = 25°C 1.4 2.5 mA
VO1 / VO2 Crosstalk attenuation AVD = 100 TA = 25°C 120 dB
6.18 Typical CharacteristicsData at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the variousdevices.
Table 1. Typical Characteristics: Table of GraphsFIGURE
IIB Input bias current versus free-air temperature Figure 1
VOM Maximum peak output voltage
versus frequencyFigure 2Figure 3Figure 4
versus free-air temperature Figure 5versus load resistance Figure 6versus supply voltage Figure 7
AVDLarge signal differential voltageamplification
versus free-air temperature Figure 8versus load resistance Figure 9
Phase shift versus frequency Figure 9Normalized unity-gain bandwidth versus free-air temperature Figure 10Normalized phase shift versus free-air temperature Figure 10
CMRR Common-mode rejection ratio versus free-air temperature Figure 11Input offset voltage change versus common-mode voltage Figure 20
ICC Supply currentversus free-air temperature Figure 13versus supply voltage Figure 12
PD Total power dissipation versus free-air temperature Figure 14Normalized slew rate versus free-air temperature Figure 15
Vn Equivalent input noise voltage versus frequency Figure 16THD Total harmonic distortion versus frequency Figure 17
Large-signal pulse response versus time Figure 18VO Output voltage versus elapsed time Figure 19
7.1 OverviewThe JFET-input operational amplifiers in the TL07xx series are similar to the TL08x series, with low input biasand offset currents, and a fast slew rate. The low harmonic distortion and low noise make the TL07xx seriesideally suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for highinput impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized foroperation from −40°C to +85°C. The M-suffix devices are characterized for operation over the full militarytemperature range of −55°C to +125°C.
7.3.1 Total Harmonic DistortionHarmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonicdistortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These deviceshave a very low THD of 0.003% meaning that the TL07x device adds little harmonic distortion when used inaudio signal applications.
7.3.2 Slew RateThe slew rate is the rate at which an operational amplifier can change the output when there is a change on theinput. These devices have a 13-V/μs slew rate.
7.4 Device Functional ModesThese devices are powered on when the supply is connected. These devices can be operated as a single-supplyoperational amplifier or dual-supply amplifier depending on the application.
NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.
8.1 Application InformationA typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage onthe input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative voltagespositive.
8.2 Typical Application
Figure 24. Inverting Amplifier
8.2.1 Design RequirementsThe supply voltage must be selected so the supply voltage is larger than the input voltage range and outputrange. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficientto accommodate this application.
8.2.2 Detailed Design ProcedureDetermine the gain required by the inverting amplifier:
(1)
(2)
Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range isdesirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not drawtoo much current. This example uses 10 kΩ for RI which means 36 kΩ is used for RF. This is determined byEquation 3.
Figure 25. Input and Output Voltages of the Inverting Amplifier
8.3 Unity Gain Buffer
Figure 26. Single-Supply Unity Gain Amplifier
8.3.1 Design Requirements• VCC must be within valid range per Recommended Operating Conditions. This example uses a value of 12 V
for VCC.• Input voltage must be within the recommended common-mode range, as shown in Recommended Operating
Conditions. The valid common-mode range is 4 V to 12 V ( VCC– + 4 V to VCC+.• Output is limited by output range, which is typically 1.5 V to 10.5 V, or VCC– + 1.5 V to VCC+ – 1.5 V.
8.3.2 Detailed Design Procedure• Avoid input voltage values below 1 V to prevent phase reversal where output goes high.• Avoid input values below 4 V to prevent degraded VIO that results in an apparent gain greater than 1. This
may cause instability in some second-order filter designs.
CAUTIONSupply voltages larger than 36 V for a single-supply or outside the range of ±18 V for adual-supply can permanently damage the device (see the Absolute Maximum Ratings).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
10 Layout
10.1 Layout GuidelinesFor best operational performance of the device, use good PCB layout practices, including:• Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedancepower sources local to the analog circuitry.– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effectivemethods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digitaland analog grounds, paying attention to the flow of the ground current. For more detailed information, seeCircuit Board Layout Techniques.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. Ifit is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular asopposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keeping RF and RG close to the invertinginput minimizes parasitic capacitance, as shown in Layout Example.
• Keep the length of input traces as short as possible. Always remember that the input traces are the mostsensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduceleakage currents from nearby traces that are at different potentials.
11.1.1 Related DocumentationFor related documentation, see the following:
Circuit Board Layout Techniques (SLOA089)
11.2 Related LinksThe table below lists quick access links. Categories include technical documents, support and communityresources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICALDOCUMENTS
TOOLS &SOFTWARE
SUPPORT &COMMUNITY
TL071 Click here Click here Click here Click here Click hereTL071A Click here Click here Click here Click here Click hereTL071B Click here Click here Click here Click here Click hereTL072 Click here Click here Click here Click here Click here
TL072A Click here Click here Click here Click here Click hereTL072B Click here Click here Click here Click here Click hereTL072M Click here Click here Click here Click here Click hereTL074 Click here Click here Click here Click here Click here
TL074A Click here Click here Click here Click here Click hereTL074B Click here Click here Click here Click here Click hereTL074M Click here Click here Click here Click here Click here
11.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.
11.4 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
11.6 GlossarySLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical packaging and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser based versions of this data sheet, refer to the left hand navigation.
TL074IDG4 ACTIVE SOIC D 14 50 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IDR ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IDRE4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 TL074I
TL074IN ACTIVE PDIP N 14 25 Pb-Free(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 TL074IN
TL074INE4 ACTIVE PDIP N 14 25 Pb-Free(RoHS)
CU NIPDAU N / A for Pkg Type -40 to 85 TL074IN
TL074MFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 TL074MFK
TL074MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 81023062ATL074MFKB
TL074MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TL074MJ
TL074MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306CATL074MJB
TL074MWB ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8102306DATL074MWB
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M :
CDIP - 5.08 mm max heightJ0014ACERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit.4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.5. Falls within MIL-STD-1835 and GDIP1-T14.
7 8
141
PIN 1 ID(OPTIONAL)
SCALE 0.900
SEATING PLANE
.010 [0.25] C A B
www.ti.com
EXAMPLE BOARD LAYOUT
ALL AROUND[0.05]
MAX.002
.002 MAX[0.05]ALL AROUND
SOLDER MASKOPENING
METAL
(.063)[1.6]
(R.002 ) TYP[0.05]
14X ( .039)[1]
( .063)[1.6]
12X (.100 )[2.54]
(.300 ) TYP[7.62]
CDIP - 5.08 mm max heightJ0014ACERAMIC DUAL IN LINE PACKAGE
4214771/A 05/2017
LAND PATTERN EXAMPLENON-SOLDER MASK DEFINED
SCALE: 5X
SEE DETAIL A SEE DETAIL B
SYMM
SYMM
1
7 8
14
DETAIL ASCALE: 15X
SOLDER MASKOPENING
METAL
DETAIL B13X, SCALE: 15X
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)0.290 (7,37)
0.014 (0,36)0.008 (0,20)
Seating Plane
4040107/C 08/96
5
40.065 (1,65)0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)0.355 (9,00)
0.015 (0,38)0.023 (0,58)
0.063 (1,60)0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).B. This drawing is subject to change without notice.C. This package can be hermetically sealed with a ceramic lid using glass frit.D. Index point is provided on cap for terminal identification.E. Falls within MIL STD 1835 GDIP1-T8
www.ti.com
PACKAGE OUTLINE
C
TYP6.66.2
1.2 MAX
6X 0.65
8X 0.300.19
2X1.95
0.150.05
(0.15) TYP
0 - 8
0.25GAGE PLANE
0.750.50
A
NOTE 3
3.12.9
BNOTE 4
4.54.3
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGE
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.5. Reference JEDEC registration MO-153, variation AA.
18
0.1 C A B
54
PIN 1 IDAREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL ATYPICAL
SCALE 2.800
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EXAMPLE BOARD LAYOUT
(5.8)
0.05 MAXALL AROUND
0.05 MINALL AROUND
8X (1.5)8X (0.45)
6X (0.65)
(R )TYP
0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLESCALE:10X
1
45
8
NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METALSOLDER MASKOPENING
NON SOLDER MASKDEFINED
SOLDER MASK DETAILSNOT TO SCALE
SOLDER MASKOPENING
METAL UNDERSOLDER MASK
SOLDER MASKDEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(5.8)
6X (0.65)
8X (0.45)8X (1.5)
(R ) TYP0.05
4221848/A 02/2015
TSSOP - 1.2 mm max heightPW0008ASMALL OUTLINE PACKAGE
NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
45
8
SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL
SCALE:10X
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