Assessment of EUV resist readiness for 32-nm hp manufacturing and extendibility study of EUV ADT using state-of-the-art resist

Assessment of EUV resist readiness for 32nm hp manufacturing, and extendibility study of EUV ADT using state-of-the-art resist.

Chawon Koha*, Liping Rena, Jacque Georgera, Frank Goodwina, Stefan Wurma, Bill Piersonb,

Joo-on Parkc, Tom Wallowd, Todd R. Younkine, and Patrick Naulleauf

aInternational SEMATECH, 257 Fuller Road, Albany, NY 12203 USA; bASML, 25 Corporate Circle, Albany, NY 12203 USA;

cSamsung Electronics, San #16, Banwol-Dong, Hwasung-city, Gyeonggi-Do, Korea 445-701; dAdvanced Micro Devices, Sunnyvale, CA 94088 USA;

eIntel Corporation, 2501 NW 229th Avenue, Hillsboro, OR 97124 USA; fCenter for X-Ray Optics, Lawrence Berkeley National Laboratory, Berkeley, CA 94720 USA

ABSTRACT

Extreme ultraviolet lithography (EUVL) is the most effective way to print sub-32 nm features. We have assessed EUVL resist readiness for 32 nm half-pitch (HP) manufacturing, presenting process feasibility data such as resolution, depth of focus (DOF), line edge roughness/line width roughness (LER/LWR), mask error enhancement factor (MEEF), resist collapse, critical dimension (CD) uniformity, post-exposure delay (PED) stability, and post-exposure bake (PEB) sensitivity. Using the alpha demo tool (ADT), a full field ASML EUV scanner, we demonstrate the feasibility of a k1 ~0.593 resist process for 32 nm HP line/space (L/S) patterning. Exposure latitude (EL) was 13% at best focus, and DOF was 160 nm at best dose using a 60 nm thick resist. By incorporating a spin-on underlayer, the process margin could be improved to 18.5% EL and 200 nm DOF. We also demonstrate ADT extendibility using a state-of-the-art EUV platform. A k1 ~0.556 resist process was demonstrated for 30 nm HP L/S patterns, providing a 13% EL, 160 nm DOF, and a common process window with isolated lines. 28 nm HP patterning for a k1 ~0.528 resist process could be feasible using a more advanced resist with improved DOF and resist collapse margin.

Keywords : Extreme ultraviolet lithography, EUVL, Photoresist, ADT (alpha-demo tool), 32nm hp Manufacturability, EUV Extendibility

1. INTRODUCTION EUV lithography (EUVL) is the most effective way to print sub-32nm features. High performance resists are crucial to EUV extendibility because the first generation of high volume manufacturing (HVM) scanners will have a small numerical aperture (NA) and conventional illumination. Several publications have outlined the characterization and improvement of EUV resist platforms.1-5 With the world’s leading-edge exposure tool for EUV resist learning, SEMATECH continues to enable the development of high performance resists to demonstrate EUV manufacturability. Using the 0.3NA SEMATECH Berkeley microfield exposure tool (MET), we have evaluated resists for potential use on full-field tools. On the Berkeley MET, several resists have demonstrated 22nm HP resolution with a rotated dipole illumination setting. Using one of these resists, we assessed EUV resist readiness for 32nm HP manufacturability as well as the ultimate performance of the ASML alpha demo tool (0.25NA, Conv. 0.5σ). A detailed process window analysis around 32nm HP patterning is reported, and the feasibility of a k1 ~0.593 resist process using ADT is characterized.

In this paper, we assess EUVL resist readiness for 32nm hp manufacturability using a full-field ADT scanner and demonstrate ADT extendibility using a state-of-the-art EUV resist platform. Process feasibility data such as resolution, depth of focus (DOF), line edge roughness/line width roughness (LER/LWR), mask error enhancement factor (MEEF), resist collapse, critical dimension (CD) uniformity, post-exposure delay stability (PED), and post-exposure bake (PEB) sensitivity are reported with state-of-the-art EUV resist.

*[email protected]; phone 1 518 649-1021; www.sematech.org

Alternative Lithographic Technologies, edited by Frank M. Schellenberg, Bruno M. La Fontaine Proc. of SPIE Vol. 7271, 727124 · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.814314

Proc. of SPIE Vol. 7271 727124-1

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2. EXPERIMENTAL RESULTS 2.1 Imaging results of SMT03 resist at the Berkeley MET

Fig. 1 shows the pattern fidelity of SMT03 resist using the Berkeley MET. A 45 degree rotated dipole having a sigma offset of 0.57 and sigma radius of 0.10 was used, and the coated resist thickness was 43nm on a 20nm thick spin-on underlayer (SMTUL1). As can be seen, 22nm HP patterns could be resolved using SMT03. Fig. 1a and Fig. 1b show top and cross-sectional views of SMT03 resist images from 20nm HP to 26nm HP L/S patterns respectively. Fig. 1c shows top-view images taken at a low magnification (22k magnification) to characterize the resist collapse margin.

Fig. 1. Imaging results of SMT03 at the Berkeley MET using a 45 degree rotated dipole (sigma offset = 0.57, sigma radius = 0.10). 2.2 Imaging performance of SMT03 resist using the ADT

2.2.1 Imaging results of L/S and contact patterns using the ADT

Fig. 2 shows the pattern fidelity of 80nm thick SMT03 resist as imaged on the ADT on a bare Si wafer. As can be seen from this figure, the 28nm HP L/S pattern and 28nm 1:1 dense contact pattern could be resolved. Fig. 3 demonstrates the resolution enhancement observed when a spin-on underlayer is used. Fig. 3a shows the top-view images without an underlayer, while Fig. 3b shows the pattern fidelity obtained when using the underlayer. The resolution limit for a given resist platform improved from 28nm HP to 26nm HP by using a spin-on underlayer. Fig. 4 shows the cross-sectional view of a SMT03 resist film patterned on a hardmask wafer using a SMTUL1 underlayer. The resist thickness after the post apply bake(PAB) was 60nm and the resulting patterned resist height for 30nm HP L/S patterns was 45nm. As shown in the cross-sectional view in Fig. 4, 28nm HP L/S pattern and a 27nm isolated line were demonstrated.

Fig. 2. Imaging results of SMT03 with 80nm thickness recorded on the ADT (0.25NA, Conv. 0.5σ).


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Fig. 4. Cross-sectional view of 60nm thick SMT03 with an underlayer.

2.2.2 Process window analysis at 32nm HP with the ADT

Fig. 5 shows the process window of 32nm HP pattern with 60nm thick SMT03 on a hardmask wafer. The exposure latitude (EL) was found to be 13% at best focus and DOF was 160nm at the dose of 21.6mJ/cm2 . The determined EL and DOF values are based on allowable CD changes of ±10% at a nominal after development inspection(ADI) CD. The images to the right in Fig. 5 were taken at low magnification (70K) to characterize resist collapse at the ADI CD of 29nm, which is the lower limit of CD tolerance for a 32nm HP L/S pattern. Due to a low pattern collapse margin, the process window is insufficient for manufacturing even with a resist thickness of 60nm after PAB.

Fig. 5. Process window for a 32nm HP pattern with 60nm resist thickness on a hardmask wafer.


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Fig. 6 shows the process window for a 32nm HP pattern with 60nm thick SMT03 on a hardmask wafer using a 20nm thick underlayer SMTUL1. EL was 18.5% and DOF was 200nm at a 24.4mJ/cm2 dose. LER and LWR were 3.2nm and 4.8nm, respectively, when using 60nm thick resist film on a hardmask wafer without an underlayer. LER and LWR improved to 2.9nm and 4.3nm, respectively, when using the SMTUL1 underlayer under the same process conditions.

Fig. 6. Process window of 32nm HP pattern using a 60nm thick resist on a SMTUL1 underlayer on a hardmask wafer.


Fig. 7 shows the process window for a 30nm HP pattern with 60nm thick SMT03 on a SMTUL1 underlayer on a hardmask wafer. EL was 13% and DOF was 160nm at a 25.2mJ/cm2 dose. Fig. 7b illustrates the status of the resist collapse margin. There was no resist collapse within the useful DOF at 30nm ADI CD, but the useful DOF was reduced to 80nm when considering resist collapse at a 27nm ADI CD, which is the lower CD limit of the 30nm HP design rule (with 10% CD tolerance). Fig. 7c shows the pattern fidelity of a 30nm 1:6 isolated line through focus. The DOF of the 30nm isolated line was 160nm at the ADI CD of 30nm, and DOF was reduced to 120nm at the ADI CD of 27nm, which again is the lower CD limit of the 30nm HP design rule (with 10% CD tolerance). Fig. 8 shows the process window of 30nm HP dense L/S pattern analyzed with ProData software. EL was calculated to be 13.2% with a DOF of 200nm based on the ADI CD analysis. This demonstrates the feasibility of 30nm HP patterning by the ADT.


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Fig. 8. Process window for a 30nm HP pattern analyzed by ProData software.


Fig. 9 shows the process window for a 28nm HP pattern with 60nm thick SMT03 on a SMTUL1 underlayer on a hardmask wafer. EL was 13% and DOF was 120nm at a 23.6mJ/cm2 dose. The Esize of the 28nm HP pattern was found to be lower than that of 30nm HP because of local mask environment differences between 28nm HP and 30nm HP patterns Fig. 9b shows the status of the resist collapse margin. The useful DOF was less than 40nm when considering resist collapse at the lower CD limit of 25.2nm which comes from assuming a 10% CD tolerance to 28nm HP design rule. 28nm HP patterning for a k1 ~0.528 resist process could be feasible for EUV extendibility at the ADT when using a more advanced resist with improved DOF and resist collapse margin.


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2.3 MEEF and CD linearity of SMT03 resist

Fig. 10a shows the MEEF values of various vertical 1:1 dense L/S patterns. The MEEF was 1.12, 1.33, 1.31, and 1.25 at 32, 30, 29, and 28nm HP patterns respectively. The data were not available at a mask bias of -4nm for 29nm HP and 28nm HP because of resist collapse at those points. Figure 10b shows CD linearity from 28nm HP to 100nm HP. The average percentage deviation of the measured ADI CD compared to the target CD was 3.4% when averaging deviations of 11 features from 28nm HP to 100nm HP. CD linearity meets the specification because it is within the 10% CD tolerance.

a. MEEF of 32nm HP Pattern b. CD linearity

Fig. 10. (a) MEEF and (b) CD linearity of the SMT03 resist at a 32nm HP L/S pattern density.


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We measured in-field CD uniformity, in-wafer CD uniformity, and wafer-to-wafer CD uniformity to analyze total CD uniformity. In-field CD uniformity of 32nm HP L/S patterns was 4.4nm (3 sigma) and 5.3nm (range). We measured 15 points in a field with 5 columns and 3 rows on the mask. Fig. 11 shows the measured CD distribution. The ADI CD of the edge pattern was larger by ~4nm than that of the center pattern. It could be improved by optimizing mask CD uniformity, dose uniformity, focus variation, and shadow effect.2 Fig. 12 also shows that slit uniformity can be improved by optimizing scanner conditions. Fig. 12b shows the CD trends for the 40nm HP pattern across the slit after scanner optimization. The slit CD uniformity was improved to 1.4nm (3 sigma) from >7nm (3 sigma) by optimizing the ADT. This continued improvement study as well as the demonstration of better in-field CD uniformity by measuring more fine grids is important to EUV manufacturability in terms of overall CD uniformity (CDU).

Fig. 11. In-field CD uniformity (CDU) of 32nm HP L/S pattern.

a. Bad slit CD uniformity of >7nm (3sigma) b. Good slit CD uniformity of 1.4nm (3sigma)

Fig. 12. Improved slit CD uniformity for a 40nm HP L/S pattern. Fig. 13 shows the in-wafer CD uniformity for a 32nm HP L/S pattern. In-wafer CD uniformity was 1.4nm (3 sigma) and 2.2nm (range) when measured in 57 fields on a single wafer. The Albany ADT is used as part of an inline system with an integrated ACT-12 track. In-wafer CD uniformity can be improved when using newer track systems with improved process control. Wafer-to-wafer CD uniformity was analyzed using a 45nm HP L/S pattern and 5 wafers. Wafer-to-wafer CD uniformity was calculated at 1.43nm after disregarding the data from an abnormal first wafer. The first wafer CD was 1.95nm lower than the average CD for the other 4 wafers. Wafer-to-wafer CD uniformity was 2.9nm when considering all 5 wafers. We believe the abnormal CD of the first wafer can be tuned by optimizing the process flow.


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Fig. 14 shows post exposure bake (PEB) sensitivity of the SMT03 resist collected using a 35nm 1:6 isolated line. The CD change caused by PEB temperature was 1.23nm/°C (~3.5%/°C) as determined by the average of 9 points per wafer for each PEB temperature.

(a) CD trends by PEB temp. (b) Top-view images and averaged CD by PEB temp.

Fig. 14. PEB sensitivity data of the SMT03 resist. Fig. 15 shows the post exposure delay (PED) stability of the SMT03 resist. In this experiment, the PED was achieved by placing the wafer on the cooling oven in the linked track system between the exposure and PEB step for the specified time. The data as determined by the average of 9 points per wafer for each PED time demonstrates that the CD change caused by PED stability is within measurement error within 40min. of exposure delay for this resist platform.

(a) CD trends according to PED (b) Top view images according to PED

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3. SUMMARY AND DISCUSSION Table 1 compares the performance of the SMT03 resist to the target specifications for 32nm HP manufacturing as outlined in the 2007 International Technology Roadmap for Semiconductors (ITRS).6 We assess the gap in manufacturing by normalizing to 1.00 as a target value for each line item. A gap value less than 1.00 indicates that it satisfies the ITRS specification for 32nm HP manufacturing. SMT03 resist with a resist thickness of 60 nm after PAB on the spin-on SMTUL1 underlayer was used to populate the resist performance specifications in Table 1. After considering resist collapse, common process margin with isolated line and CD linearity, the resolution was good for 32nm patterning Furthermore, 30nm HP patterning was also feasible with an acceptable process margin - 13% EL and 160nm DOF. PED stability was good within 40 min. delay. However, sensitivity, LWR, resist collapse, CD uniformity, and PEB sensitivity need to be improved to have a viable platform for 32nm HP manufacturing, as displayed in Table 1.

Table 2 summarizes the current resist performance status on the ADT as analyzed by the so-called Z-factor.7 “Resolution w/ PW” is defined as the resolution at which the process window is sufficient for manufacturing. Nano Z-factor,8 nZ32_DRAM, describes the normalized Z-factor by comparing it to the Z-factor required for 32nm HP DRAM specifications as shown in Table 2. When considering the Z-factor of 32nm HP DRAM, SMT03 requires an approximately 3.2X improvement to meet the specification.

Table 1. Summary of SMT03 resist performance

Table 2. Resist performance in terms of Z-factor analysis

Sensitivity and LWR need to be improved to realize EUV manufacturing targets. Recently, good progress has been demonstrated in improving photo sensitivity using the Berkeley MET. However, LWR still remains one of key issues where sufficient progress is lacking because of the challenge to address the resolution, line width, and sensitivity (RLS) trade-off. Post-processing after resist imaging has demonstrated an improvement in LWR, 8-9 and it looks like these will be necessary to achieve better LWR. There is another way to contribute to LWR. The LWR specification may be relaxed if CD uniformity which is better than the ITRS specification can be achieved. EUVL can have a strong point in controlling CD non-uniformity induced through mask CD error because EUVL has a relatively high k1 factor that results in a low MEEF value. Furthermore, advanced track systems can improve CD uniformity through improved process control. Table 3 shows the CD uniformity and LWR of the SMT03 resist and the potential relaxed LWR specification if


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total CD uniformity can be improved. As mentioned above, the current CD uniformity performance can be improved by using a state-of-the-art track system. The Albany ADT currently uses an ACT-12 track with known limitations. When excluding the first abnormal wafer in our wafer-to-wafer (WTW) CD uniformity experiment, total CD uniformity(TCDU) becomes 4.83nm, which is 1.9 times higher than the ITRS specification. By improving in-field CD uniformity (IFU) to 1.66nm (3 sigma), the TCDU can meet the ITRS specification for 32nm manufacturing. By combining TCDU and LWR, we can describe the real CD effect on device performance as a single parameter, effective total CD uniformity (ETCDU), as illustrated in Table 3. This means that it may be possible to manufacture with a higher LWR specification than current ITRS specification if the TCDU can be driven below 2.6nm. “CDU upgrade 1G” in table 2 refers to the first improved CDU generation as a result of improving the scanner and/or track system. If TCDU can be driven down to 2.2nm with CDU upgrade 2G, the LWR specification could be relaxed to 3.5nm for 32nm HP DRAM. Driving TCDU to 1.85nm with CDU upgrade 3G may allow the LWR specification to be relaxed further to 3.7nm for 32nm DRAM and 2.5nm for 32nm MPU gate applications.

Table 3. Summary of SMT03 resist performance.

4. CONCLUSION We have assessed EUV resist readiness for 32nm HP manufacturability, demonstrating the feasibility of 32nm HP L/S patterning with a k1 ~0.593 resist process using the Albany ASML ADT. EL was 13% at best focus, and DOF was 160nm at best dose for a resist thickness of 60nm after PAB. The process margin was improved to 18.5% (EL) and 200nm (DOF) by using a spin-on underlayer, SMTUL1. The feasibility of 30nm HP L/S pattern, using a k1 ~0.556 resist process was also demonstrated. EL was 13% and DOF was 160nm after considering the resist collapse margin and the common process window with a 1:6 isolated line at 30nm HP patterning. 28nm HP patterning for a k1 ~0.528 resist process could be feasible on the ADT using a more advanced resist with improved DOF and resist collapse margin.

5. ACKNOWLEDGEMENT We would like to thank seven major EUV resist suppliers, Dongjin, Fujifilm, JSR, Rohm and Hass, Shinetsu, Sumitomo, and TOK, for supplying the quality EUV resist samples and engaging in in-depth discussions that continue to enable our EUV resist cycles of learning. We also appreciate Brian Hoef, Gideon Jones, and Paul Denham for their continuous support on the Berkeley MET, and Dominic Ashworth, Emil Piscani, Khurshid Anwar, and Warren Montgomery for Albany Resist Material Development Center (RMDC) support. Brian Martinick, Lior Huli, Martin P. Rodgers, and Corbet S. Johnson provided CNSE support. We would like to express our gratitude to Pryool Kang and Haisub Na of Samsung Electronics for their technical support. We would also like to thank Bryan Rice and John Warlaumont of SEMATECH, Michael Tittnich of CNSE, and Kevin Cummings, Sang-In Han, Thomas Laursen, Brian Lee, Robert Routh, and Robert Watso of ASML for their support and encouragement throughout this work.

6. REFERENCES [1] Ma, A., Park, J., Dean, K., Wurm, S., Naulleau, P., “Benchmarking Commercial EUVL Resists at SEMATECH,”

Proc. SPIE 6921, 69213O (2008).

Proc. of SPIE Vol. 7271 727124-10

[2] Hendrickx, E., Goethals, A.M., Niroomand, A., et al., “Full field EUV lithography: Lessons learnt on EUV ADT imaging, EUV resist, and EUV reticles,” Proc. SPIE 7140, 714007 (2008).

[3] Kawamura, D., Kaneyama, K., Kobayashi, S., Oizumi, H., and Itani, T., “Current benchmarking results of EUV resist at Selete,” Proc. SPIE 7140, 714008 (2008).

[4] Koh, C., Wurm, S., Park, J., Ma, A., and Nalleau, P., “Sub-22nm Half-pitch (HP) EUV Resist Imaging Results,” EUVL Symposium (2008).

[5] Pierson, B., Wallow, T., Mizuno, H., et al., “EUV Resist Performance on the ASML ADT and LBNL MET,” EUVL Symposium (2008).

[6] http://www.itrs.net/ [7] Wallow, T., Higgins, C., Brainard, R., Petrillo, K., et al., “Evaluation of EUV resist materials for use at the 32 nm

half-pitch node,” Proc. SPIE 6921, 69211F (2008). [8] Younkin, T., “Optimizing RLS,” EUV Resist TWG at EUVL Symposium (2008). [9] Chandhok, M., Frasure, K., Putna, E.S., Younkin, T., Rachmady, W., Shah, U., and Yueh, W., “Improvement in

Linewidth Roughness by Postprocessing,” J. Vac. Sci. Technol. B 26 2265 (2008).

Proc. of SPIE Vol. 7271 727124-11

Assessment of EUV resist readiness for 32-nm hp manufacturing and extendibility study of EUV ADT using state-of-the-art resist

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