Outline Timing Requirements Area problem New Yield Formulations Die Cost Timing Requirements for SEl and clock signals Mostafa Said Sayed [email protected]June 4, 2013 Mostafa Said Sayed [email protected]Timing Requirements for SEl and clock signals
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SEL high period TH requirementsClock edge requirements
TH requirements
Assume that the delay of the transmission gate GT is tpand the delay of the TSV is tTSV .The SEL high period TH must maintain at 1 for at least tp tocatch the real value of V2.
Figure: TSV-BOX delays.Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
SEL high period TH requirementsClock edge requirements
TH requirements - Cont.
Both SEL and Vo signals will encounter a delay tTSVthrough the TSV to reach the top layerSince tTSV delay is common in both signals therefore it willnot affect the operation of the DeMUX.Vo will encounter another delay through the TG of theDeMUX equal to tp also.Therefore SEL must wait tp until Vo reaches DeMUX andanother tp until Vo passes through the TG of the DeMUX,so now:
TH − tp ≥ tp, (1)
therefore:TH ≥ 2tp. (2)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
SEL high period TH requirementsClock edge requirements
Clock edge requirements.
Suppose that both V1 and V2 will be the inputs of two DFFswith equal setup time tsu.Since V2 is delayed with 2tp+tTSV , then the clock risingedge for the DFF should rise at:
2tp + tTSV + tsu. (3)
But V1 is delayed with 2tp+tTSV +TH , so the clock risingedge of the other DFF should rise at:
2tp + tTSV + tsu + TH . (4)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
When DTSV is small there may be no reduction in areaThe critical or threshold value DTSVth is the value at whichno reduction in area occursTo determine the DTSVth Let A1=A2Then
Adie + NTSV ATSV = Adie +NTSV
2(ATSV + 2AMUX ) (6)
12
ATSV = AMUX− > ATSV = 2AMUX (7)
πr2 = 2AMUX (8)
r2 =2AMUX
π(9)
r =DTSV
2+ KOZavg =
√2AMUX
π(10)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
∴ For area reduction DTSV + 2KOZavg ≥ 9.654 µm (13)
For DTSV =8 µm –> KOZavg=3.25 µm∵ 8+6.5=14.5 > 9.654∴ there will be area reductionWhile for DTSV =5 µm –> KOZavg=0.75 µ∵ 5+1.5=6.5 < 9.654∴ there will be no area reduction
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
The solution for this problem is to decrease the MUX areaTo decrease the MUX area, it must be implemented usinglower dimension technology that we do not have here inEJUSTI am currently looking for a college that have TSMC 130nm technologyThe main problem is that area will affect also die yield andcost (as will be seen later) since it’s conversely depends ondie area
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
The die yield is modeled according to the distribution of therandom number of defects on the die.It has been shown that the defects are usually notrandomly distributed across the chip, but are alwaysclustered. The widely used formula is the Gamma functionbased yield model:
Ydie = (1 +DoAdie
α)−α. (18)
The parameter α is a constant depends upon thecomplexity of the manufacturing process, according to thereference α is typically 2
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
where Ybonding captures the yield loss of the chip due tofaults in the bonding processes and it’s independent of thenumber of TSVs and YTSV is the TSV yield discussedbefore.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
In [Modeling the Economics of Testing: A DFT Perspective]the die cost is
Ctest = Cprep + Cexec + Csilicon + Cquality (27)
Cprep captures fixed costs of test generation such as testerprogram creation and nonrecurring costs.Cexec consists of costs of test-related hardware such asprobe cards.Csilicon is the cost required to incorporate DFT features(here it will be zero).Cquality is the cost increase mainly due to the fault dies thatpass the test while they are real faulty.
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
Ctest gen is the test-pattern generation costCtest prog is the tester-program preparation cost,CDFT design is the additional design cost for DFT (will be setto zero)
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals
1 Cdie is not constant as was expected before2 Cdie is dependent on die area Adie
3 To compute Cdie there are still 2 parameters that’s notknown yet which I do not find in that paper βfail and Tsetup
4 One way to find them is that, Fig. 2 in the paper draws theTtest , so we can pick up 2 points on the curve and solvethat 2 unknown linear system to find those unknowns
Mostafa Said Sayed [email protected] Timing Requirements for SEl and clock signals