TI Maximizing SNR

Maximizing High Speed Data Converter Performance through Clocking, Power, and

SNRBoostMaximizing High Speed Data Converter Performance through Clocking, Power, and SNRBoost

Vera Mao Texas Instruments

Agenda

•

Sampling Theory–

Nyquist Rate–

Aliasing–

Under-sampling

•

Analog Signal Chain Interface -

ADC–

Passive Transformer Interface–

Buffer vs. Non-buffered Device–

Active Op-Amp Interface

•


DAC–

Proper Load for Current Sink DACs–

Interface Network to Quadrature Modulator–

Low Pass Filter Design Techniques

•

DAC Special Features–

Interpolation Filters–

Digital Signal Adjustments (QMC)–

NCO option–

DAC3283 Example Diagram

•

Real World Clocking Solutions–

Clock Jitter impact to Data Converter Performance

–

Jitter Impact as Related to Input Frequency–

TI High Performance Clocking Solutions–

Clock Improvement Techniques

•

Power Supply Considerations–

Utilizing DC-DC Converters for Efficient Supplies

–

Power Supply Noise Reduction Techniques

•

Special Section: China Export Restrictions and SNRBoost

–

Current Export Restrictions–

SNRBoost3G

noise shaper –

ADS58C48–

Out of band noise gain in SNRBoost

Administrator

Highlight

Sampling Theory

•

The Nyquist Rate is the minimum sampling rate required to avoid aliasing – Nyquist rate is simply twice the highest frequency

Fs/2 = 45

‘Nyquist’

Fs=90M67.5 112.5

“1st Nyquist”

135 180

“2nd Nyquist” “3rd Nyquist” “4th Nyquist” “etc……..”

SAMPLE/CLOCK RATE

What is Aliasing?

•

Aliasing -

two different sinusoids give the same digital samples–

If Fs

is the Sampling Frequency (clock rate)–

a high frequency Fred

= 10/9 * Fs–

and a low frequency at Fblue

= 1/9 * Fs

= Fred – Fs–

Both look like 1/9 * Fs

to the ADC–

Thus one might say, •

“the frequency at Fred is aliased down, or under-sampled, to be at frequency Fblue

at the ADC digital outputs in the spectral domain”

•

Or better yet, “the ADC can’t tell the difference”

example: Wikipedia.org

Under-sampling (Aliasing)

•

We just down-converted a signal from a high frequency to a lower frequency –

that sounds useful

–

This is called Under-sampling

•

This usually requires an analog frequency mixer

•

What is not always clear in the definition of the Nyquist Rate is that it refers to the bandwidth of the signal, not the frequency–

In the example given, the bandwidth of each signal is practically zero –

these are discrete tones at 1/9 and 10/9 of Fs

–

But signals with no bandwidth contain little information and are therefore not usually very useful for communication systems

–

So let’s look at aliasing with some bandwidth involved….

Bad Aliasing (graphically speaking)

Input to ADC Sampling at 90MSPS

Output of ADC Sampling at 90MSPS

After Aliasing, or Down-Converting,

45MHz of Bandwidth

Notice that the ‘red’ spectrum aliased on top of part of the ‘gray’ spectrum.

Notice also that the red horizontally inverted, while the gray did not

This would NOT be okay – a digital down-converter (DDC) would not be able to recover the information.

As drawn here, this is 1 modulated carrier with a BW = 45MHz, centered at 100MHz

Fs/2 = 45

‘Nyquist’

Fs=90M

Fs/2 = 45

‘Nyquist’Fs=90M

77.5 122.512.5

32.5

Good Aliasing

Fs/2 = 45

‘Nyquist’Fs=90M67.5 112.5

Fs/2 = 45





45MHz of Bandwidth

Notice that the spectrum is still continuous.

Notice that the color is not horizontally inverted – this is because we used an ‘odd’ nyquist zone (the 3rd). If we had used an ‘even’ zone, the color would reverse – it is spectrally inverted. This is not a bad thing, but might need to be known in order to process the band.

Many radio designs take full advantage of ‘good aliasing’ to eliminate an entire analog frequency down-conversion stage – saving board space, power, and money

As drawn here, this is 1 modulated carrier with a BW = 45MHz, centered at 112.5MHz, so all the energy is in one ‘Nyquist Zone’

135

22.5

Practical Aliasing Example

Fs/2 = 45


Fs/2 = 45





45MHz of Bandwidth

This is perfect – a digital down-converter (DDC) can recover the information with room for further practical digital filtering and digital frequency mixing – usually to baseband.

Many radio designs take full advantage of ‘good aliasing’ to eliminate an entire analog frequency down-conversion stage – saving board space, power, and money

As drawn here, this is 1 modulated carrier with a BW = 22.5MHz (Fs / 4), centered at 112.5MHz (it could be multiple sub-carriers in the same BW)

135

Analog BPF

In the real world, you need to bandpass filter the signal before going into the ADC so that frequency content outside of your signal of interest is not aliased into the ADC and adding noise – and BPF’s aren’t a brickwall – they require some room for proper roll-off

22.5

22.5

Can all ADCs Under-sample?

•

Pipeline ADCs are usually designed to have Input Bandwidth that exceeds the intended operating range or ‘Performance Bandwidth’

•

The ADS5463, with a 2GHz Input Bandwidth, could sample input frequencies up to 2GHz (carrier, not BW) at 500MSPS –

but the

performance is frequency dependent

•

There are ADCs that cannot under-sample, which are sometimes called Nyquist Converters, and are usually high precision and have much slower sample rates

Agenda

•

Sampling Theory–

Nyquist Rate–

Aliasing–

Under-sampling

•


ADC–




•


DAC–




•




NCO option–


•



–




•



–


•


–


SNRBoost3G

noise shaper –

ADS58C48–


Transformers

•

Benefits–

Isolated Input\Output –

does not pass DC!

–

Common Mode can be applied to the center tap to bias ADC inputs

–

Can provide voltage step-up or step down–

Can provide Single-ended to differential conversion

–

Provides best AC performance, particularly at high-IF

–

They are passive devices, no noise added

•

Limitations–

Phase Balance

–

Amplitude balance–

Flatness of bandwidth

–

Frequency Bandwidth

Transformers Example

•

Dual transformer–

Better balance of single ended to differential

•

Transformer is automatically AC coupled–

Can use VCM to bias at center tap, or at termination

•

Balun

is not AC coupled, need AC coupling external to balun

Input Circuit – Buffered vs. Non-buffered

•

TI BiCMOS

ADCs are generally buffered–

Input buffer presents high input impedance–

Prevents noise from sampling caps from getting out–

Often have internal biasing to VCM

•

TI CMOS ADCs are often non-buffered (but not always)–

Input is *not* constant impedance (i.e. not constant effective input capacitance vs. frequency)–

Sampling caps emit noise back onto the input signal at every edge of the sample clock–

Sampling glitch noise will have both single ended and common mode components

•

External filtering is often recommended to swallow up the sampling glitches–

External R-C-R filter across inputs•

Put pole of the filter higher than highest desired input frequency–

Low impedance termination to VCM to hold more tightly to VCM•

Ex: Two 25 Ohm terminations to VCM to terminate single 50 Ohm input–

Problem: Higher ratio transformers or amplifiers desire higher termination or load imp.–

Effect of inadequate filtering of sampling glitches => loss of SFDR–

Trick: for specific input frequencies and sample rates, tuned RLC circuit across inputs

•

Sampling glitches may wreak havoc with amplifier stability–

Same amplifier and filter that worked well with ADS5483 was unstable with ADS62P49

Amplifiers

•

Reasons to use an op-amp–

Provide the gain needed for driving the ADC at its full dynamic range

–

Used in DC or time domain applications–

Used in baseband applications!!

–

The CM input of the op-amp can be used to level shift the signal to the right level for the ADC

–

Used for SE to differential conversion

•

Considerations when using an op-amp–

For best overall performance, the input bandwidth should be limited, such that unwanted noise is also band-limited

–

Excellent performance can be achieved up to at least 100MHz or so of analog input

•

Amp + ADC *will* have worse AC performance than ADC itself–

Must decide on target specs and design amp/filter to meet it

Amplifiers

•

Filter–

Follow amp with bandpass

filter if possible

•

Input bandwidth of the ADC might be 2GHz or more–

Might represent many Nyquist zones•

Noise floor will fold back many times

•

SNR–

SNR of amp + filter combine with ADC by rms

sum of powers

•

Can never get better SNR than ADC data sheet numbers, but amp + filter can degrade it

•

SFDR–

SFDR of amp + filter combine with ADC linearly in voltage

Agenda

•

Sampling Theory–

Nyquist Rate–

Aliasing–

Under-sampling

•


ADC–




•


DAC–




•




NCO option–


•



–




•



–


•


–


SNRBoost3G

noise shaper –

ADS58C48–


Proper Load for Current Sink DACs

•

Max Current = 20 mA

•

Max Voltage Swing = 1Vpp each leg

•

Rload

= 50 ohms

Interface Network to Quadrature Modulator

•

Case 1: Utilizing 3.3V Vcm

Modulator like TRF370333–

Two resistor network (per leg)

–

No insertion loss

•

Case 2: Utilizing a Modulator with Vcm

< 3.3V like TRF370317–

3 resistor network (per leg)

–

Insertion loss dependant on delta common mode voltage

Case 1 Case 2

Low Pass Filter Design Technique

•

Typically utilize LPF to eliminate high frequency noise and clock images

•

Filter source impedance is set by R1, R2, R3

•

Filter Load impedance is set by R4

•

DAC Load impedance is set by R1, R2, R3, and R4

1 APCLRWR

A

Ref 10 dBm

Start 0 Hz Stop 614.4 MHz61.44 MHz/

Att 20 dB*

* RBW 10 kHz

VBW 30 kHz

SWT 6.2 s

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0

10

1

Marker 1 [T1 ]

-60.57 dBm

120.639589572 MHz

2

Marker 2 [T1 ]

-40.13 dBm

83.889230769 MHz

3

Marker 3 [T1 ]

-80.10 dBm

307.200000000 MHz

DAC Filter Design Example

•

Zin, Zout

= 50 ohms SE

•

5th

order Butterworth Filter

•

Desired Corner Frequency = 70 MHz

•

Designed Corner Frequency > 70 MHz –

account for filter roll-off due to Q limitation of the inductors

•

Modify to differential topology

1 APCLRWR

A

Ref 10 dBm

Start 0 Hz Stop 614.4 MHz61.44 MHz/

Att 20 dB*

* RBW 10 kHz

VBW 30 kHz

SWT 6.2 s

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0

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Marker 1 [T1 ]

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120.639589572 MHz

2

Marker 2 [T1 ]

-40.13 dBm

83.889230769 MHz

3

Marker 3 [T1 ]

-80.10 dBm

307.200000000 MHz

DAC Filter Example Schematic

Agenda

•

Sampling Theory–

Nyquist Rate–

Aliasing–

Under-sampling

•


ADC–




•


DAC–




•




NCO option–


•



–




•



–


•


–


SNRBoost3G

noise shaper –

ADS58C48–


Interpolation

•

Additional samples are created on-chip provided sampling at >2x on the input data

•

Benefits–

Run the interface slower (i.e. lower data clock rate)

–

get more distance between the signal of interest and the images, resulting in easier filtering.

–

Also get benefits of higher oversample rates which can improve SNR. (processing gain)

•

The Cost–

High speed logic to generate the interpolation filters

Administrator

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Interpolation Filters

•

We can use a digital filter to “create”

accurate interpolated

samples between the actual input sample

•

Convolving with the SINC function can create nearly perfect values

•

Ideal SINC function is infinite; must window in practice

Administrator

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Administrator

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Interpolation Filter Implementation

•

Utilize efficient shift and add circuitry.

•

The filters are designed with the minimum number of add and subtract operations to minimize hardware

limit

limit round

b0

b2

b4

-1

highpass

data_in

clk_1xclk_2x

data_out

0

1

0

1

Administrator

Highlight

Special Features

•

QMC Adjustments–

DC Offset Adjustment

•

Used to minimize LO Feedthrough–

QMC Gain

•

Adjust digital gain of the signal•

Adjust for I/Q amplitude imbalance–

QMC Phase

•

Adjust for I/Q phase imbalance–

QMC Delay

•

Adjust for I/Q delay imbalance

•

Coarse Mixer–

Adjust output to fs/2 or fs/4 to move signal to higher IF

•

NCO –

Numerically Controlled Oscillator–

Used to adjust output frequency to any arbitrary frequency

–

Programmable and adjustable on-the-fly–

Not limited to binary divisions of clock rate

DAC Block Diagram (DAC3283)10

010

0

Pat

tern

Te

st

De-

inte

rleav

e

8 Sa

mpl

e FI

FO

100

Coa

rse

Mix

erFs

/4, -

Fs/4

, Fs/

2

QM

CP

hase

and

Gai

n

ALA

RM

_SD

O

SDIO

SDEN

B

SCLK

TXEN

AB

LE

RES

ETB

CLK

VDD

18

DIG

VDD

18

VFU

SE

DA

CVD

D18

GN

D

100

Pro

gram

mab

le D

elay

(0-3

T)

Agenda

•

Sampling Theory–

Nyquist Rate–

Aliasing–

Under-sampling

•


ADC–




•


DAC–




•




NCO option–


•



–




•



–


•


–


SNRBoost3G

noise shaper –

ADS58C48–


Clock Jitter Impact to Data Converters

•

Random variation of the clock position compared to its ideal position with respect to time

•

As clock position varies, the position of the sampling point varies

•

Sampling at imprecise locations yield SNR degradation

•

Theoretical limit of SNR due to jitter:

where:fin

= input frequency

τj

= clock jitter

)2log(20 jinj fSNR τπ ⋅⋅−=

Jitter Impact with respect to Frequency

•

SNR is independent of sampling rate

•

SNR is dependent on input frequency–

For a given amount of jitter, SNR degrades as input frequency increases

•

Higher sampling rates indirectly lead to more stringent jitter requirements

)2log(20 jinj fSNR τπ ⋅⋅−=

Clock Jitter vs. Phase Noise

•

Jitter is related to the integrated phase noise performance over

a specified BW

Where:L(f) = SSB noise power spectral densityΦN

= Phase Noisef0

, f1

= frequency limits of integrationτj

= clock jitter

•

Phase Noise = Sum of the area under the curves

clkj

f

fN

f

dffLdBc

N

πτ

2102[sec]

)(][

10

1

0

Φ

⋅=

⋅=Φ ∫

Total Data Converter SNR Performance

•

SNR contributions–

Quantization noise:

•

6 * N# of bits + 1.76 dB–

Clock jitter

•

Jitter or Phase Noise Performance–

Aperture jitter

•

Value extracted from the datasheet–

Thermal Noise

•

Value estimated from SNR performance from the datasheet at lowest IF

•

Total jitter is determined by rms

sum of all individual contributions

•

Total SNR is vector sum of all individual SNR contributions

[ ]2∑=i

iT ττ

Administrator

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Administrator

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Determining Clocking Requirements

•

Given SNR target from customer or standards

•

Given ADC aperture jitter from device datasheet

•

Given center frequency from customer specifications

•

Calculate the clock jitter requirement

•

Jitter Calculator Worksheet: http://www.ti.com/litv/zip/slac133

http://www.ti.com/litv/zip/slac133

ADS61B49 (14-bit 250 MSPS) Example

•

Aperture Jitter:

170 fs

•

Fin:

450 MHz

•

SNR (from DS):

66 dB

•

Clock Jitter: 200 fs

(CDCE72010)

•

SNR :

62.6 dB

Calculate Jitter-limited SNRInput Frequency 450.00 MHzAperture Jitter 170.00 fs rmsExt Clock Jitter 200.00 fs rmsTotal Jitter 262.49 fs rmsSNR 62.59 dBc

Input Frequency 450.00 MHzAperture Jitter 170.00 fs rmsExt Clock Jitter 0.00 fs rmsTotal Jitter 170.00 fs rmsSNR 66.36 dBc

Calculate Jitter-limited SNRInput Frequency 450.00 MHzAperture Jitter 170.00 fs rmsExt Clock Jitter 200.00 fs rmsTotal Jitter 262.49 fs rmsSNR 62.59 dBc

ADS61B49 at 450 MHz IF

Measurements match predicted values within 0.5 dB

TI Clocking Solutions for Data Converters

•

CDCM7005•

External VCXO Ultra Low Jitter

•

5 output channels•

Programmable divider outputs

•

CDCE72010•

External VCXO Ultra Low Jitter

•

10 output channels•

Extended Programmable divider outputs

•

CDCE62005•

Integrated Low Jitter Frequency Synthesizer

•

5 output channel•

Wide range of programmable divider outputs

•

CDCE52005•

Integrated Dual PLL Ultra Low Jitter Synthesizer

TI Clocking Solutions for Data Converters

•

VCXO Dependent–

CDC7005

–

CDCE7005•

Jitter: ~180 –

250 fs

•

Internal VCO Dependent–

CDCE62005

•

Jitter: ~ 660 fs–

CDCE52005

•

Jitter: ~220 fs

With 400kHz PLL BW

CD

CE

7201

0C

DC

E62

005

DAC3283 ACPR/NSD Example

•

NSD (Noise Spectral Density) Relationship to ACPR (Adjacent Channel Power Ratio)–

ACPR [dBc] = Pout –

(NSN [dBc/Hz] * 10*log(BW))

–

Example•

NSN = -160 dBc/Hz

(from datasheet)•

BW = 3.84 MHz

(from standards)•

Pout = -7.7 dBm (at 70 MHz)•

Alt-ACPR [dBc] = 86.5 dBc

WCDMA ACPR Performance (DAC3283 EVM) over Frequency and Clock Jitter using External Clock and CDCE62005

A

Ref -14.5 dBm

**

*CLRWR

RBW 30 kHzVBW 300 kHzSWT 2 sAtt 10 dB*

1 RM

NOR

*

Center 259.32 MHz Span 25.5 MHz2.55 MHz/

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Tx Channel W-CDMA 3GPP FWD Bandwidth 3.84 MHz Power -9.26 dBm Adjacent Channel Bandwidth 3.84 MHz Lower -76.76 dB Spacing 5 MHz Upper -76.38 dB Alternate Channel Bandwidth 3.84 MHz Lower -79.37 dB Spacing 10 MHz Upper -78.78 dB

1

Marker 1 [T1 ] -103.58 dB 255.320000000 MHz

2

Marker 2 [T1 ] -103.58 dB 255.320000000 MHz

A

Ref -12.5 dBm

**

*CLRWR


1 RM

NOR

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Center 20 MHz Span 25.5 MHz2.55 MHz/

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Marker 1 [T1 ] -105.71 dB 24.000000000 MHz

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*CLRWR


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Ref -14.6 dBm

**

*CLRWR


1 RM

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Center 259.32 MHz Span 25.5 MHz2.55 MHz/

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Marker 1 [T1 ] -103.73 dB 255.320000000 MHz

2

Marker 2 [T1 ] -103.73 dB 255.320000000 MHz

20 MHz

259 MHzCDC Clock

CDC ClockExt Clock

Ext Clock

Example ADC SNR with Different CDC Devices

•

Test with ADC62C17 (11-bit)–

Engage SNR Boost

–

Measurement BW = ~ 20 MHz–

Fin = 150 MHz; Fclk

= 122.88 MHz

–

Expected SNR Performance with SNR_Boost1

= ~72 dBFS

(1) Extrapolated from SNR contour plots and expected SNR Boost improvement

Performance with Subpar Clock

•

CDCE62005–

Jitter = ~650 fs

–

SNR (20 MHz BW) = 62.4 dBFS

Performance with Realistic Clock

•

CDCE72010–

Jitter: ~300 fs

–

SNR = 71.1 dBFS

•

Dual PLL–

Jitter: ~220 fs

–

SNR = 72.3 dBFS

Clock Thermal Noise Impact to SNR

•

Thermal noise causes random variations in clock amplitude

•

Random variations alter zero-crossings or transition boundary location with respect to time (similar to jitter)

•

These variations yield SNR degradation.

Sinusoidal Clock Amplitude

•

Maximizing the clock amplitude increases the slope of the sinusoidal clock signal at the transition boundaries and reduces thermal noise impact

Band Limit Clock Phase Noise

•

Clock jitter performance integrated over entire clock input BW–

Input BW can be up to 1 GHz for high speed converters

–

Some band limiting filter needed

•

For very sensitive jitter requirements, add narrow band Crystal filter on output–

Requires CMOS output or amplifier to overcome insertion loss

–

Crystal Filter BW around 14 kHz–

Small SMT devices available

Agenda

•

Sampling Theory–

Nyquist Rate–

Aliasing–

Under-sampling

•


ADC–




•


DAC–




•




NCO option–


•



–




•



–


•


–


SNRBoost3G

noise shaper –

ADS58C48–


Power Supply

•

Most ADCs have separate supplies for analog and digital circuitry–

Analog supply must be kept ‘clean’

–

Check PSSR in datasheet, but normally <20mV ok

•

Traditionally an LDO regulator is used for each supply voltage–

“Safe”

approach

–

Still need good design, layout, and bypassing–

Degrades efficiency –

must dissipate power in LDO

•

Migrating toward use of DC-DC converters–

New converters are very small (smaller than LDOs)

–

Improved efficiency–

High switching frequencies yield to smaller inductors and easier

filtering

–

Yield good performance

Traditional ADC Power Supply

Typical LDO drop out voltage ~0.5V (with DC/DC)

Often LDO connected directly to the input rail

Drop out voltage of LDO 0.5V 1V 1.7V (5V) 1.5V (3.3V)

3.3V Output

1.8V Output

13%

22%

26%

36%

34%

45%

Ideal loss in the LDO

Tradeoff between number of regulators and efficiency

Best efficiency is to minimize drop across LDO

But lowest device count may be to drop from existing next highest voltage rail.

DC-DC Power Supplies

•

Included on EVMs

for newer lower power ADCs–

ADS41xx, ADS42xx, ADS58C48•

Option to compare DC-DC supply, LDO, and bench supply

•

Optimize power supply for max power efficiency while maintaining performance

Ferrite Bead Choice?

•

Ferrite bead after DC-DC (or LDO) provides filtering and supply isolation

•

LF202 ferrite provides highest impedance at switching frequency–

TPS62590 switching frequency is 2.25 MHz

•

Standard “ADC ferrite”

provides higher impedance at higher frequencies–

Useful for providing isolation from RF signals

LF202 ~75Ω

at switching frequency Standard ferrite beat on ADC EVMs

Power Supply Comparisons ADS4149 at 250MSPS

•

Negligible SFDR degradation with DC-DC

•

Negligible SNR degradation below 170 MHz

•

Only 0.3 dB SNR hit at 300 MHz IF

•

Ferrite bead choice is critical

SNR (dBFS) vs Fin (MHz) @ 250Msps

68.5

69

69.5

70

70.5

71

71.5

72

0 50 100 150 200 250 300

Fin (MHz)

1.8V Lab SupplyDCDC - LF202LDO - ADC ferriteDCDC - ADC ferrite

SFDR (dBc) vs Fin (MHz) @ 250Msps

70

75

80

85

90

95

0 50 100 150 200 250 300

Fin (MHz)

1.8V Lab SupplyDCDC - LF202LDO - ADC ferriteDCDC - ADC ferrite

Agenda

•

Sampling Theory–

Nyquist Rate–

Aliasing–

Under-sampling

•


ADC–




•


DAC–




•




NCO option–


•



–




•



–


•

China Export Restrictions and SNRBoost–


SNRBoost3G

noise shaper –

ADS58C48–


What are the export restrictions for ADCs?

Resolu tion

Max Fs

9 50011 20012 105

The export restrictions are updated periodically as data converter technology improves

Takes into account

commercial vs. military system needs

Supplier and government inputs

Multi-national negotiation (US, Europe, Japan) lengthens process

ADS58C48 Quad channel 11 Bit 200 MSPS withSNRBoost3G

– TI PATENTED TECHNOLOGY•

New and Improved SNRBoost3G: –

SNRboost3G

is the 3rd

generation ADC from TI.–

TI invented and patented SNRboost

technology.

–

New, optimized wideband modes (up to 60M @ 184.32 MSPS) for 3G wireless technology

–

Features flat noise performance inband.•

SNRBoost3G Bandwidth modes–

60M: Center frequency adjustable in 7 steps in 5.3M from Fs/4

–

40M: Center frequency adjustable in 9 steps in 6.5M from Fs/4–

30M: Center frequency adjustable in 10 steps in 7M from Fs/4

–

20M: Center frequency adjustable in 10 steps in 8M from Fs/4•

Specs and Features:–

Quad, 11-Bit resolution, 200MSPS

–

Ultra-low power technology: all 4ch on, the total Power Dissipation =1.1W–

Selectable DDR LVDS or CMOS output.

–

Pin control of SNRboost–

80 pin QFP

NDA Protected Material

Total Out of Band Noise Increases with % BW of Nyquist BW

2010/8/8 “TI Proprietary Information -

Strictly Private”

or similar placed here if applicable 55

Case #1FS=122.88M, BW=40M

Case #2 FS=184.32M, BW=40M

More total power for 65% occupied BW than for 43% occupied BW

Noise Gain in SNR Boost

0 5 10 15 20 250

5

10

15

20

25

30

Tap

Val

ue

Noise shaping INCREASES noise during shaping process

With no noise shaping, quantization has a maximumof 0.5 output LSBs

Noise shaping peak value increases by SUM(ABS(filter taps))

Increased headroom needed to avoid saturation with noise shapingadded to input signal

Noise Shaping Circuit

Filter taps

Current

Sample

Past quantization errors

0 20 40 60 80-40

-20

0

20

40

60

Frequency (MHz)

Res

pons

e (d

B)

Filter FFT

12 dB Suppression

Noise Gain in SNR BoostMore filter taps and larger total sum required for higher BW/Fs ratiosand filters offset from mid-band

Example at 184.32 MSPS

ADC input headroom required to prevent saturation

0 1 2 3 4 5x 104

-1000

-800

-600

-400

-200

0

200

400

600

800

1000

Sample

Cod

e

40 MHz centered

60 MHz centered

60 MHz offset 10 MHz

Noise shaped signal without ADC input signal

BW (MHz) Filter Sum Headroom (dB)20 6.9 0.0330 11.4 0.0540 29.7 0.1360 171 0.76

Thank You!

TI Maximizing SNR

Documents

china export

nco option

dac proper

ti clocking

band noise

entire analog

cdc clock

clock jitter