Through the Looking Glass Continued (III)pagiamt/kcsmith/... · employing 4.2-B transistors, and offers up to 2.5× higher socket per - formance over its 32 nm POWER7+ predecessor

isscc trends

IEEE SOLID-STATE CIRCUITS MAGAZINE winter 20 14 49

A

Through the Looking Glass Continued (III)Update to Trends in Solid-State Circuits and Systems from ISSCC 2014

A two-part article, “Through the Look-ing Glass II” was published last year (in the Winter 2013 and Spring 2013 issues of IEEE Solid-State Circuits Magazine) to discuss the trends in solid-state circuits and systems based on papers selected by the program subcommittees of IEEE International Solid-State Circuits Con-ference (ISSCC) 2013. This article high-lights additions to those trends based on technical papers that are selected to be presented at ISSCC 2014.

ISSCC continues to be the premier forum in which industry and aca-demic experts present and discuss the latest innovations in the world of solid-state circuits. The ISSCC Inter-national Technical Program Commit-tee is divided into ten subject areas: analog; data converters; energy-efficient digital; high-performance digital; imagers, microelectrome-chanical systems (MEMS), medical, and displays (IMMD); memory; radio frequency (RF); technology directions (TD); wireless; and wireline. Each year, each subcommittee updates its view of progress in its area of specialty, based on papers to be pre-sented at the upcoming ISSCC. Their complete compilation of trends for ISSCC 2014 are available for down-load at www.isscc.org. The following summary provides an overview of some of the changes seen this year.

Analog (Power Converters) Analog circuits serve as bridges between the digital computing world and the analog real world. But digital circuits such as microprocessors drive

the market; thus, semiconductor tech-nology has been optimized relent-lessly over the past 40 years to reduce the size, cost, and power consump-tion of digital circuits. These aspects of semiconductor technology explain two key divergent trends in analog circuits. One trend is to forgo the latest digital IC manufacturing tech-nologies, instead fabricating analog circuits in older technologies, which may be augmented to accommo-date the high voltages demanded by increasing markets in medical, auto-motive, industrial, and high-efficiency lighting applications. Other applica-tions dictate the full integration of analog and digital circuits together in our most modern digital semiconduc-tor technologies. For example, micro-processors with multiple cores can reduce their overall power consump-tion by dynamically scaling operating

voltage and frequency in response to time-varying computational demands. For this purpose, dc-dc voltage con-verters are embedded alongside the digital circuitry, driving research into the delivery of locally regulated power supplies with high efficiency and low die area, but without recourse to external components. These trends are captured by movement towards the top-right in Figure 1, including two representative publications in ISSCC 2014.

Data ConvertersData converters are specialized analog circuits that link the information pres-ent in the analog real world with the processing that occurs in the digital computing world. Key metrics such as signal-to-noise ratio, bandwidth, and power efficiency continue to be the dominant drivers for innovation, as

Digital Object Identifier 10.1109/MSSC.2013.2289636

Date of publication: 30 January 2014

95.0

90.0

85.0

80.0

75.0

70.0

65.0

Pea

k E

ffici

ency

(%

)

60.0

55.0

50.00.1 1 10 100 1,000

Power Density (mW/mm2)

10,000

CMOS 32 nm

SOI + 32 nm

90 nm

130 nm

ISSCC 2013 ISSCC 2014

ISSCC 2014ISSCC 2012

Trench Caps.

SOI + 32 nm, Deep Trench

Resonant,0.35 µm + MIM

90 nm + MIM

Efficiency ↔ Power Density

Figure 1: A comparison of integrated switched-capacitor power converters showing peak efficiency versus power density. recent advances achieve much higher power density with-out sacrificing efficiency (see the top right).

50 winter 20 14 IEEE SOLID-STATE CIRCUITS MAGAZINE

evidenced by the data converters to be presented at ISSCC 2014. Figure 2 is a survey of ADC power efficiency expressed as power dissipated rela-tive to the effective Nyquist rate as a function of signal-to-noise and dis-tortion ratio (SNDR). Figure 3 shows energy per conversion step versus the Nyquist sampling rate. Figure 4 plots

achieved bandwidth as a function of SNDR. Sampling jitter and aperture errors make the combination of high resolution and high bandwidth a par-ticularly difficult task. Just as in past years, in 2014, we see many examples setting a new standard in these met-rics, utilizing several different con-verter architectures.

Energy-Efficient Digital and Wireless (Smartphone and Wireless Trends)Figure 5 illustrates the major trends in energy efficiency of digital circuits for smartphones and tablets. A new trend for 2014 is the introduction of smart-phone application processors that sup-port wide quad extended graphics array (WQXGA) displays that have a resolu-tion of 3,200 × 1,600 in a 16:9 aspect ratio with as much as 2× increase in computational capacity from last year. Apart from this, the trends in wire-less connectivity include the growth of cellular wireless standards such as long-term evolution (LTE), with mul-tiple frequency bands, a wide range of channel bandwidths, and various duplexing and diversity schemes, as well as new features, such as carrier aggregation. In addition, WLAN data rates are increasing exponentially. At ISSCC 2014, a 60-GHz carrier commer-cial CMOS chip set achieves 4.6 Gb/s over 10-m links, while CMOS front-end solutions reach 28 Gb/s for proximity wireless communication.

High-Performance Digital (Processor Milestones)The relentless march of process tech-nology brings increasing integration and energy-efficient performance to enterprise and cloud servers.

ISSCC 2014 features include: ■ IBM 12-core, 96-thread POWER8

processor in 22-nm SOI, with 96 MB of eDRAM shared L3 cache, all employing 4.2-B transistors, and offers up to 2.5× higher socket per-formance over its 32 nm POWER7+ predecessor

■ Intel 15-core, 30-thread next-generation Xeon server processor in 22-nm trigate technology with 37.5 MB shared SRAM L3 cache integrates 4.31-B transistors

■ Intel Haswell processor in a 22-nm trigate process introduces a 128-MB multichip package eDRAM L4 cache to boost integrated graphics performance. Milestones reached at ISSCC 2014

include the crossing of the 4.3 billion mark in number of transistors and the 100 MB mark in cache size illustrated in Figures 6 and 7, respectively.

1.E–01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

P/f s

nyq(

pJ)

10 20 30 40 50 60 70SNDR at Nyquist (dB)

80 90 100 110 120

ISSCC 1997–2013VLSI 1997–2013FOMW = 10 fJ/conv-step

FOMS = 170 dBDelta-Sigma 2014Flash 2014

Other 2014Pipeline 2014SAR 2014

Figure 2: A survey of Adc power efficiency expressed as power dissipated relative to the effective nyquist rate as a function of sndr. new papers from isscc 2014 are highlighted.

Figure 3: the energy per conversion step versus the nyquist sampling rate. new papers from isscc 2014 are highlighted.

1.E–011.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

fsnyq(Hz)

ISSCC 1997–2013VLSI 1997–2013Delta-Sigma 2014Flash 2014

Other 2014Pipeline 2014SAR 2014

FO

MW

, hf(f

J/co

nv-s

tep)

IEEE SOLID-STATE CIRCUITS MAGAZINE winter 20 14 51

MemoryIn memory systems, we continue to see progressive scaling in embedded SRAM, DRAM, and floating-gate-based flash for very broad applications. Some state-of-the-art developments from ISSCC 2014 include:

■ 1-Gb eDRAM using a 22-nm trigate logic process and capable of being clocked at 2 GHz

■ 128-Gb 2-b-per-cell NAND-Flash design using three-dimensional cell technology with 24-WL stacked layers

■ 128-Gb 2 b-per-cell NAND-Flash design using 16-nm planar cell technology

■ 128-Mb SRAM designed in 14-nm FinFet CMOS using a 6T bitcell with Vmin-enhancement techniques

■ embedded ReRAM in 28-nm capa-ble of working down to 270 mV

■ 1-Gb eight-channel 128 GB/s high-bandwidth memory (HBM) DRAM

■ 3.2-Gb/s/pin 8-Gb 1.0-V LPDDR4 SDRAM with an integrated ECC engine.Milestones reached at ISSCC 2014

for SRAM bit-cell size, DRAM band-width, and NAND-flash-memory den-sity are shown in Figures 8–10, respectively.

Radio FrequencyAt ISSCC 2014, RF techniques are ex-tending both in innovation and integra-tion level, across the RF bands from a few gigahertz to above 500 GHz. For the first time, wireless receivers are being implemented in 28-nm CMOS. At ISSCC 2014, several distinct trends are apparent. Increasing levels of in-tegration are seen in all areas of RF design, from cellular and wireless sensors to mm-wave and imaging systems extending to the terahertz

10 20 30 40 50 60 70 80 90 100 110 1201.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

SNDR at fin, hf(dB)

f in, h

f(Hz)

ISSCC 1997–2013VLSI 1997–2013Jitter = 1 psrms

Jitter = 0.1 psrmsDelta-Sigma 2014Flash 2014

Other 2014Pipeline 2014SAR 2014

Figure 4: Bandwidth as a function of sndr. new papers from isscc 2014 are highlighted, including one high-speed Flash and two high-speed sAr data converters.

2-D, 3-D

16-b QVGA VGAWVGAat 60fps

SXGAat 60fps

DualCamera

20 M16 M10 M5~8 M3 M1–2 M

MP3 AAC AAC PlusWMA

Dolby 5.1Dolby

TrueHD/Digital+

Multicore(4–8)

SIMDMulticore (2–4)

FPUDSP

EGPRS0.4

UMTS0.4–2

HSPA1.8–7

HSPA+7–42

LTE100

LTE150–600

6,00012,000

2,4006,000

8002,400

500800

300500

–300

JPEG, MPEG-4H.264/AVC(VGA

H.264/AVC(D1)

H.264/AVC(Full HD)

H.265

WQXGAat 60fps

OpenGL(ES1.1)

OpenGL/VG/MAX(ES2.0)

AR(Augmented Reality)

Graphics

Display

Camera

Image/Video

Audio

Accelerator

Downlink(Mb/s)

CPU (MIPS)

H.264/MVCH.264/SVC

2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

Figure 5: smartphone application processor trends.

52 winter 20 14 IEEE SOLID-STATE CIRCUITS MAGAZINE

region. While there are several other exemplary accomplishments in RF cir-cuits, it is noteworthy that the output power level at sub-mm wave radio fre-quencies has reached record levels as illustrated by the 130-nm SiGe source shown in Figure 11.

WirelineWireline-focused circuits have been instrumental in enabling the incred-ible scaling of computer systems, ranging from handheld electron-ics to supercomputers. This year, at ISSCC 2014, notable accomplish-ments include:

■ the lowest-reported power long-range 28-Gb/s transceiver, achiev-ing 20 pJ/b and two DFE receivers operating at 0.25 pJ/b

■ a new coded signaling scheme that transmits 8 b over eight wires, enabling 96 Gb/s at 4.3 pJ/b/wire over 15-dB loss channels

■ an electrical-interconnected 28-Gb/s transceiver operating over a 30-dB loss channel

■ a 60-Gb/s transmitter, the highest transmit data-rate reported to date

■ an optical interconnect that uses a two-dimensional (12 × 5) optical array achieving an aggregate data-rate of 600 Gb/s.

IMMD and TD (Novel Circuits and Systems)A breakthrough concept in biomedical electronics has been the identification of the need for “anytime and any-where” human-monitoring systems using wearable/implantable devices.

Such devices will enable improved of quality of life through self-health checks, remote examination by

physicians, and continuous monitor-ing for acute diseases. Key technolo-gies for such system include:

10,00010

1,0009

1008

107

16

1992

1994

1996

1998

2000

2002

2004

2006

2008

2010

2012

2014

Tans

isto

r C

ount

(M

illio

ns)

Chip Complexity

4.3 Billion!!!

Figure 6: the transistor count.

Figure 8: srAM bit-cell and minimum-supply-voltage scaling.

Figure 7: the on-die cache size.

120

100

80

60

40

20

0

2000

2002

2004

2006

2008

2010

2012

2014

Cac

he S

ize

(MB

)

Total on-Die Change

General Trend

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.0090 65 45 40 32

Technology Node (nm)

Bit

Siz

e (µ

m2 )

28 22 20 16 14

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

1.20 1.201.10

1.00 0.950.999

1.001.00

0.900.85

0.85 0.80

0.0640.0730.0810.0920.1270.171

0.2420.346

0.525

VCC_UPVCC_HPCell Area

Vm

in(V

)

100

10

1

0.11997 1999 2001 2003 2005 2007

Year

Dat

a B

andw

idth

(G

B/s

)

2009 2011 2013 2015

HBM

GDDR(x)

WIO(x)

DDR(x)

LPDDR(x)

DDRDDR2DDR3DDR4GDDR3GDDR4GDDR5LPDDR2LPDDR3LPDDR4HBMWIO

Figure 9: drAM bandwidth.

IEEE SOLID-STATE CIRCUITS MAGAZINE winter 20 14 53

■ small-footprint devices and flex-ible electronics to improve the comfort of wearable devices

■ high-accuracy monitoring devices ■ low-power monitoring and com-

munication systems for long-duration autonomous operation.In the past few decades, many

new applications such as mobile devices and the Internet have driven the growth of high-performance computing systems. The next big application drivers will include cloud computing, big data, and the Internet of Things, which will require increasing performance demands on the backbone of the infrastructure. Important trends and future challenges requiring sys-tem innovation include

■ satisfying performance demands that increase at an exponential rate

■ containing the power dissipated in data centers whose electricity and cooling costs are skyrocketing.The CMOS-image-sensor business

is one of the fastest growing seg-ments of the semiconductor indus-try. Key applications include cell phone cameras, digital still cameras, camcorders, security cameras, auto-motive cameras, digital-cinema cam-eras, and gaming. The resolution and miniaturization races are ongoing, and while the performance require-ments stay constant, pixel size con-tinues to scale down. Images over 40 MP are commercially available.

A column-parallel approach based on pipelined and multiple-sampling implementations has become stan-dard for low-power, high-speed, low-noise camera and video applications. Backside illumination is now a main-stream technology for mobile imag-ing. Wafer stacking of the image array on a CMOS image signal processor will become common.

MEMS has now enabled the world’s smallest 32-kHz ultra-low-power tim-ing sources. Low-power timing has normally been supplied by quartz tuning forks, but miniaturization of that technology is proceeding slowly. MEMS oscillators are available a 1.5 × 0.8 mm2 die, in a chip-scale package, and consume under 1 μA supply current. Temperature com-pensation provides three parts per million accuracy over temperature.

ConclusionIn this article, we have highlighted some of the trends in solid-state circuits and systems identified by an international group of over 180 experts that serve as members of the ISSCC Technical Program Committee. Their analysis is based on the review and analysis of papers that were selected for presentation at ISSCC 2014, in the light of the collective expertise represented by each sub-committee’s membership. A more complete trend analysis is available for download at www.isscc.org.

AcknowledgmentsThe authors wish to acknowledge the creators of the original mate-rial from which this article has been structured. While the creation of trend material has been largely a team effort by several members of each subcommittee, each has oper-ated under the direction of his or her chair, as listed below:

■ Analog: Axel Thomsen, Silicon Laboratories

■ Data Converters: Boris Murmann, Stanford University

■ Energy-Efficient Digital: Stephen Kosonocky, AMD

■ High-Performance Digital: Stefan Rusu, Intel

■ IMMD: Roland Thewes, TU Berlin ■ Memory: Kevin Zhang, Intel ■ RF: Andreia Cathelin, STMicroelec-

tronics ■ TD: Eugenio Cantatore, Eindhoven

University of Technology ■ Wireless: Aarno Parssinen, Broadcom ■ Wireline: Daniel Friedman, IBM

T.J. Watson Research Center.

—Siva Narendra Tyfone, Portland, Oregon

—Laura C. Fujino

University of Toronto, Canada

—Kenneth C. Smith University of Toronto, Canada

Figure 10: nAnd flash memory density.

1,000

100

10

1

0.1

0.01

1994

1996

1998

2000

2002

2004

2006

2008

2010

2012

2014

x3/Year

1 b/Cell (SLC)2 b/Cell (MLC)3 b/Cell (TLC)4 b/Cell (16LC)

MB

/mm

2

–60

–50

–40

–30

–20

–10

0

10

150 200 250 300 350 400 450 500 550 600

Pow

er (

dBm

)

Frequency (GHz)

45 nm

130 nm

130 nm

65 nm 65 nm

45 nm

130 nm SiGe

90 nm

45 nm

45 nm 65 nm

InP

ISSCC2014130 nm SiGe

ISSCC201465 nm

InP

Figure 11: Output power versus frequency for mm-wave and sub-mm-wave sources.