This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
Lec. 91
This Week’s Subject
•DRAM & Flexible RRAM
•p-channel MOSFET (PMOS)
• CMOS: Complementary Metal Oxide Semiconductor
• CMOS Logic InverterNAND gateNOR gate
• CMOS Integration & Layout
• GaAs MESFET (JFET)
• Flexible Inorganic Semiconductor Technology
Lec. 92
DRAM (Dynamic Random Access Memory)
Schematic DRAM Chip Architecture:
PADRow Decoder
Col
. Dec
.
Memory Cell
Array
Col
. Dec
.
Col
. Dec
.
Col
. Dec
.
Row Decoder
Row Decoder
Row Decoder
RAS (row access strobe)Supplementary
Lec. 93
DRAM cell (Or Display)
Periphery circuits
∼1cm
Cell array(core) ∼
3cm
Word line
+ + + +
Transfer gate [access]B
it lin
e
- - - - Capacitor(or OLED )
I/O gate, CMOS TRData sense/amplifier
Data read Data refresh
Storage node
DRAM:
◎ Random access: row decoder → Select word linecolumn decoder → Select bit line
◎ Need to refresh the charge loss in the capacitor (μsec) Display (LCD or OLED):
◎ Active Matrix: with transistor in each cell. Fast speed, Large pixel
◎ Passive Matrix: w/o transistor. Slow respond speed(~250msec), small pixel
Lec. 94
p-channel MOSFET
Circuit diagram
Transfer curve (Id-Vg curve)
Id-Vd curve
-
-
-
-
-
-
Source electrode
Gate electrode
Drain electrode
n-type Si substrate
Source (p+) Drain (p+)
Gate
Gate oxide
p-channel MOSFET (PMOS)
-IDS
-VG-VTh=-0.5V
Vd=-1V
-1.8V0V
Lec. 95
CMOS Logic (Inverter)
Complementary Metal Oxide Semiconductor: NMOS+PMOS
Reference (Ground)
Reference
•Inverter : building block of integrated circuits
Vtn=-Vtp
Vgp=Vin-Vdd
Vgn=Vin
Vdsn=VoutVdsp=Vout-Vdd
1, 0 0, 1
Pull-down NMOS
Pull-up PMOS
Vin Vout
0 1
1 0
Pull-up PMOS
Lec. 96
CMOS Logic (Inverter)
Reference (Ground)
Reference(1.8V)
1.8V digital 1
1.8V
Vtn=0.5V on
Vtp=-0.5V off
Vgn=1.8V
Vgp= 0V
Pull down by NMOS 0V
0V digital 0
1 Ohm
100 Ohm
1.8V
0V
Digital 1 is inverted to digital 0
Vgp=Vin-Vdd
Lec. 97
CMOS Logic (Inverter)
Reference (Ground)
Reference(1.8V)
1.8V digital 1
0V
Vtn=0.5V off
Vtp=-0.5V on
Vgn=0V
Vgp= -1.8V
Pull up by PMOS 1.79V
0V digital 0
100 Ohm
1 Ohm
1.8V
1.79V
Digital 0 is inverted to digital 1
Vgp=Vin-Vdd
Lec. 98
CMOS Logic (NAND Gate)
VDD
The output is high when either of inputs A or B is high, or if neither is high. In other words, it is normally high, going low only if both A and B are high.
Pull-down NMOS
Pull-down NMOS
Pull-up PMOS
Lec. 99
CMOS Logic (NOR Gate)
VDD
The output is high only when neither A nor B is high. That is, it is normally high but any kind of non-zero input will take it low.
Pull-down NMOS
Pull-up PMOS
Pull-up PMOS
Lec. 910
CMOS Inverter Layout
Ref: CMOS VLSI Design, N.Weste, Addison Wiley,
Lec. 911
CMOS Inverter Mask Layout
Lec. 912
a) Starting Material•Dopant type : p-type (boron)•Orientation : (100)•Resistivity : 13±2•Wafer size : 4 inch
b) Initial oxidation•Temperature : 1000C 130min.•Thickness : 6000±6000Å
d) Well mask• PR coat, soft bake• Align, Exposure• Develop, • Hard bake