Think Fast: FPGA Design using C - NewAE … · Think Fast: FPGA Design using C Colin O’Flynn ... Zynq / MicroBlaze Integration ... 105MSPS ADC Spartan6 LX25 Module (NewAE.com)

Think Fast: FPGA Design using C

Colin O’Flynn

NewAE Technology Inc

#eelive

This Presentation in 60 Seconds

This Presentation in 60 Seconds

This Presentation in 60 Seconds

About Me

Programmable Logic in Practice (CC Column)

www.ProgrammableLogicInPractice.com (videos, etc)

Currently pursuing PhD, embedded security (power

analysis, clock glitching, etc). See YouTube channel

for cool examples!

HLS is NOT a way to convert

software blocks to hardware. You

cannot do that and get good results.

No matter what vendors tell you.

Introduction: What is *NOT* High Level Synthesis?

Introduction: What is High Level Synthesis?

• Use C/C++ as HDL-like language

• Ability to compile the C/C++ code to get bit-accurate versions of

code which ‘run’ on your computer (~1000x faster simulations)

• Possible to write C/C++ which can run as both a hardware block via

HLS, or a software block.

• An amazing tool for rapid prototyping

It’s a Design Tool

Introduction: What is High Level Synthesis?

• If using HLS for ‘Protocols’ (e.g. send this, receive that), need to use

special directive to control data clocking

• This is VERY useful as can implement complex state machine in a

few minutes

• Not enough time to explain – see example posted online (link in last

slide) and/or Feb 2014 issue of Circuit Cellar (I’ve got a few copies

with me for you)

Important Information I’m Skipping on Protocol Implementation

First Steps: Your Interface

Making your First Block

C++ Design

HDL Block

Source: Xilinx UG902

More Advanced: Zynq / MicroBlaze Integration

Specify an AXI4LITE Interface (other types supported too)

More Advanced: Zynq / MicroBlaze Integration

Generates a core for XPS

More Advanced: Zynq / MicroBlaze Integration

These functions were automatically made for me (I just called them)

Next Steps: Working with Fixed-Point Data

Fixed Point Options

Next Steps: Examples of Data Types

Hardware in Use

OpenDAC, 210MSPS DAC(NewAE.com)

OpenADC, 105MSPS ADC(NewAE.com)Spartan6 LX25 Module

(ZTEX.de)

Baseboard (PSU)

Alternate Hardware

Custom ADC/DAC Board

• Spartan 3 Based FPGA Module

• 1x ADC• 1x DAC

Alternate Hardware

Red Pitaya

• Zynq Based!• 2x ADC• 2x DAC

Base Project

• Generates 105 MHz clk

• Outputs clocks to ADC/DAC

– Uses ODDR2 Block for S6

• Links ADC to DAC

Measurement Setup

Using VNWA (Small PC-Based Vector Network Analyzer)

Measurement Setup

Alternate Measurement Setup

FIR Filter Theory

Filter Equation

1

0

][)(N

k

k knxbny

FIR Filter Theory

Filter Interpretation

y[2] = b0 * x[2] + b1*x[1] + b3*x[0]

FIR Filter Theory

Generating Coefficients

e.g. Using MATLAB or arc.id.au/FilterDesign.html

Live Demo Begins Now!

• I’m now going to implement the FIR filter

• Following slides are not used during presentation, but show rough

steps of implementation

VNA Results – Raw (using LNA Input)

VNA Results – Raw (using LNA Input)

VNA Results – After Cheating (Calibration)

Coding the FIR Filter 1/2

Coding the FIR Filter 2/2

Inserting Auto-Generated Code

Inserting the FIR Filter Code & Testing Results

Done!

• Working demo of implementing an FIR with fixed-point math

• See my YouTube channel for recording of project

More Information & Questions

• Check out February 2014 Issue of Circuit Cellar, covers HLS

• www.ProgrammableLogicInPractice.com/?p=87 has examples

• www.ColinOFlynn.com/eelive for material from this presentation

Contact me:

E-Mail: [email protected]

Twitter: colin.oflynn