ANALYTICAL MODELING AND SIMULATION OF SHORT-CHANNEL EFFECTS IN A FULLY DEPLETED DUAL-MATERIAL GATE (DMG) SOI MOSFET A dissertation submitted in partial fulfillment of the requirement for the degree of Master of Science (Research) by Anurag Chaudhry Under the Supervision of Dr. M. Jagadesh Kumar to the Department of Electrical Engineering Indian Institute of Technology Delhi December, 2003
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ANALYTICAL MODELING AND SIMULATION OF SHORT-CHANNEL EFFECTS IN A FULLY DEPLETED
DUAL-MATERIAL GATE (DMG) SOI MOSFET
A dissertation submitted in partial fulfillment of the requirement for the degree of Master of Science (Research)
by Anurag Chaudhry
Under the Supervision of Dr. M. Jagadesh Kumar
to the
Department of Electrical Engineering Indian Institute of Technology Delhi
December, 2003
CERTIFICATE
This is to certify that the thesis entitled ANALYTICAL MODELING AND
SIMULATION OF SHORT-CHANNEL EFFECTS IN A FULLY DEPLETED
DUAL-MATERIAL GATE (DMG) SOI MOSFET being submitted by Anurag
Chaudhry to the Indian Institute of Technology, Delhi, for the award of the degree of
Master of Science (Research) in Electrical Engineering Department is a bona fide
work carried out by him under my supervision and guidance. The research reports and
the results presented in this thesis have not been submitted in parts or in full to any other
University or Institute for the award of any other degree or diploma.
Dr. M. Jagadesh Kumar Date : 2 Dec 2003 Associate Professor Department of Electrical Engineering Indian Institute of Technology New Delhi - 110016
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ACKNOWLEDGEMENTS
I wish to express my sincere gratitude to my supervisor Dr. M. Jagadesh Kumar
for his invaluable guidance and advice during every stage of this endeavour. I am greatly
indebted to him for his continuing encouragement and support without which, it would
not have been possible for me to complete this undertaking successfully. His insightful
comments and suggestions have continually helped me to improve my understanding.
I am deeply indebted to Dr. Krishnan V. Pagalthivarthi for his genuine guidance
and encouragement. I am grateful to both Dr. and Mrs. Krishnan for their loving
guidance and support. Their personal living example has provided me an unfailing
direction to use my education in the service of humanity at large.
Special thanks are due to Prof. D. Nagchoudhuri for his valuable suggestions and
questions during my synopsis presentation.
I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory
facilities at all points of time.
I would also like to express my heartfelt gratitude to my friend Vipin who has
helped me with the typing of the thesis. My special thanks to my friends Rakesh,
Partheepan, Swadesh, Ramnarayan and others, who always inspired me and particularly
helped me in difficult times. Thanks are due to Ritesh Sharma for helping me in the lab.
My sincere thanks and acknowledgements are due to my mother and brother who
have constantly encouraged me for completing this project.
Anurag Chaudhry
v
ABSTRACT
Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the
last decade offering superior CMOS devices with higher speed, higher density, excellent
radiation hardness and reduced second order effects for submicron VLSI applications.
Recent experimental studies have invigorated interest in fully depleted (FD) SOI devices
because of their potentially superior scalability relative to bulk silicon CMOS devices.
Many novel device structures have been reported in literature to address the challenge of
short-channel effects (SCE) and higher performance for deep submicron VLSI
integration. However, most of the proposed structures do not offer simultaneous SCE
suppression and improved circuit performance. Others involve complicated processing
not amenable for easy integration into the present CMOS technology.
Dual-Material Gate (DMG) structure offers an alternative way of simultaneous
SCE suppression and improved device performance by careful control of the material
workfunction and length of the laterally amalgamated gate materials. A physics based
analytical model of surface potential along the channel in a FD DMG SOI MOSFET is
developed by solving 2-D Poisson’s equation. The model is used to investigate the
excellent immunity against SCE offered by the DMG structure. Further the model is
used to formulate an analytical expression of the threshold voltage, Vth. The results
clearly demonstrate the scaling potential of DMG SOI devices with a desirable threshold
voltage “roll-up” observed with decreasing channel lengths.
Numerical simulation studies were used to explore and compare the novel attributes
of DMG SOI MOSFET with a conventional single-material gate (SMG) device in terms
of circuit parameters like transconductance, drain conductance, voltage gain, leakage
current, on-current and Vth “roll-up”. An optimum gate length ratio of the two gate
lengths, L1/L2 = 1, and a workfunction difference, ∆W = 0.4 eV, between them
workfunctions is pointed by the simulation studies. In conclusion, we have demonstrated
the superior attributes offered by the DMG structure in FD SOI devices by developing a
simple analytical model and extensive simulation studies. The results presented in this
work are expected to provide incentive for further experimental exploration.
vii
TABLE OF CONTENTS
CERTIFICATE ............................................................................................................................................. iii
ABSTRACT ................................................................................................................................................. vii
TABLE OF CONTENTS ...............................................................................................................................ix
LIST OF TABLES .........................................................................................................................................xi
LIST OF ILLUSTRATIONS....................................................................................................................... xiii
1.1. MOTIVATION FOR PRESENT RESEARCH ........................................................................................1 1.2. NATURE OF THE PROBLEM............................................................................................................3
1.2.1 Threshold voltage model ..............................................................................................................3 1.3. RECENT RESEARCH RELEVANT TO THE PROBLEM.........................................................................5 1.4. RESEARCH PROBLEM STATEMENT ................................................................................................5 1.5. THESIS ORGANIZATION..................................................................................................................6
CHAPTER II ...............................................................................................................................................9
SHORT-CHANNEL EFFECTS IN SOI: A REVIEW ....................................................................................9
TWO-DIMENSIONAL MODEL OF SURFACE POTENTIAL IN A FULLY DEPLETED (FD) DMG SOI MOSFET......................................................................................................................................29
3.1. INTRODUCTION............................................................................................................................29 3.2. DMG SOI STRUCTURE AND ITS PARAMETERS............................................................................29 3.3. MATHEMATICAL FORMULATION .................................................................................................30 3.4. RESULTS AND DISCUSSION..........................................................................................................37
CHAPTER IV ............................................................................................................................................49
THRESHOLD VOLTAGE MODELING AND EVIDENCE FOR SUBDUED SHORT-CHANNEL EFFECTS ......................................................................................................................................................49
4.1. INTRODUCTION............................................................................................................................49 4.2. MATHEMATICAL FORMULATION .................................................................................................49 4.3. RESULTS AND DISCUSSION..........................................................................................................52
5.2.1 Performance comparison with SMG SOI MOSFET...................................................................63 5.2.2 Scaling characteristics at a fixed high workfunction gate length, L1 .........................................66 5.2.3 Effect of L1/L2 ratio at a fixed channel length, L ........................................................................67 5.2.4 Effect of workfunction difference (∆W) at a fixed channel length, L..........................................72
5.3. SUMMARY...................................................................................................................................75 CHAPTER VI ............................................................................................................................................77
LIST OF PUBLICATIONS...................................................................................................................................95
x
LIST OF TABLES
Table Page
Table 5.1 Device parameters used for simulation of DMG and SMG SOI MOSFET’s.
62
xi
LIST OF ILLUSTRATIONS
Figure Page
1.1 Cross-sectional view of the bulk-Si (left) and SOI (right) CMOS devices [1].
2
2.1 Surface potential variation along the position in channel for 0.1 V and 1.5 V drain voltages (linear and saturated case).
12
2.2 Three mechanisms determining SCE in SOI MOSFETs [24]. 12
2.3 Comparison of schematic energy band diagrams near the bottom of the body between the long and short-channel fully depleted (FD) nMOSFET’s [24].
13
2.4 Effects of the three mechanisms on threshold voltage dependence on gate length [24].
14
2.5 Short channel effect in a FD SOI NMOS device with front gate oxide of 9.2 nm, buried oxide of 400 nm, thin-film of 80 nm, with back gate bias of 0 and –5 V [16].
14
2.6 Threshold voltage roll-off of FD SOI NMOS device with a front gate oxide of 4.5 nm and various thin-film thicknesses [37].
15
2.7 Threshold voltage shift versus thin-film thickness for various channel doping densities, biased at (a) VDS = 0.05 V, and (b) 1.5 V [38].
16
2.8 Threshold voltage versus channel length of an SOI NMOS device with front gate oxide of 6 nm and a thin-film of 100 nm, and buried oxide of 100 nm and 400 nm [39].
17
2.9 Electric field lines from the drain [40]. 18
2.10 Comparison of device structures for (a) a conventional MOS and (b) a raised source/drain thin-body transistor. Thin-body device structure can effectively suppress sub-surface leakage current [44].
19
2.11 Threshold voltage versus channel length of an FD SOI NMOS device using polysilicon and tantalum gates [50].
21
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2.12 Threshold voltage roll-off due to DIBL and CS versus buried oxide permittivity [52].
21
2.13 Graded channel SOI MOSFET [53]. 22
2.14 Ground plane under (a) source and drain edge [57] or (b) channel region [58].
23
2.15 Double-gate, triple-gate, gate all around (GAA) and Π-gate SOI MOSFETs [70].
24
2.16 VTH roll-off and DIBL in double, triple, quadruple and Π-gate SOI MOSFETs. Device width and thickness = 30 nm [70].
24
2.17 Cross-section of a single-halo (SH) SOI nMOSFET [77]. 26
3.1 Cross-sectional view of an n-channel fully depleted DMG-SOI MOSFET.
30
3.2(a) Surface channel potential profiles of DMG-SOI MOSFET for different drain biases for a DMG fully depleted SOI with channel length L = 0.2 µm as obtained from the analytical model and 2-D MEDICI simulation. The screening effect is distinctly visible.
38
3.2(b) Surface channel potential profiles of SMG-SOI MOSFET for different drain biases with channel length L = 0.2 µm as obtained from the 2-D MEDICI simulation.
39
3.3 Surface potential versus position along channel for two different gate metal workfunction differences.
40
3.4 Plot of surface potential versus position in channel for different gate metal workfunctions φM1 and φM2 of M1 and M2, keeping the difference (φM1 - φM2) constant.
41
3.5 Variation of surface potential with position in channel for different combination of gate lengths L1 and L2, keeping the sum (L1+L2) constant.
42
3.6(a) Surface potential plot for two different substrate doping concentrations for a DMG SOI.
43
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3.6(b) Surface potential plot for two different substrate doping concentrations for a SMG SOI.
43
3.7 Variation of surface potential with position in channel for two different front-gate oxide thicknesses.
44
3.8 Variation of surface potential along the channel for two different thin-film thicknesses.
45
3.9 Variation of electric field along the channel shown for region close to drain.
46
4.1 Threshold voltage variation with channel length compared for DMG and SMG SOI devices. L1 is fixed at 0.1 µm for the DMG SOI device and φM = 4.77 V for the SMG SOI MOS.
52
4.2 Threshold voltage variation with channel length for DMG SOI devices.
53
4.3 Minimum surface potential as a function of channel length for two different thin-film thicknesses as extracted from MEDICI and the analytical model. L1 is kept fixed at 0.1 µm.
54
4.4 Threshold voltage variation with channel length for different substrate biasing.
55
4.5 Threshold voltage variation with channel length for substrate biasing of 0 V and -2 V with L1 fixed at 50 nm.
56
4.6 Threshold voltage variation with channel length for different body doping density.
57
4.7 Vth variation with channel length for different body doping density with L1 = 50 nm.
57
4.8 Threshold voltage variation with channel length for different buried oxide thickness.
58
4.9 Threshold voltage variation as a function of channel length for buried oxide thicknesses of 100 nm and 400 nm with L1 fixed at 50 nm.
59
4.10 Threshold voltage variation with gate workfunction difference at a fixed channel, L = 0.5 µm for two different L1/L2 ratio.
60
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5.1 Output characteristics compared for a DMG SOI with SMG SOI MOSFET.
63
5.2 Gate characteristics compared for a DMG SOI with SMG SOI MOSFET.
64
5.3(a) Electric field profile along the surface of the channel for DMG and SMG SOI MOSFET's.
65
5.3(b) Electron velocity profile along the surface of the channel for DMG and SMG SOI MOSFET's.
65
5.4 Comparison of threshold voltage variation with channel for DMG and SMG SOI MOSFET’s.
66
5.5 Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.
67
5.6 Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm. L1 = 0 corresponds to SMG SOI.
68
5.7(a) Variation of gm and gd with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3 µm. L1 = 0 corresponds to SMG SOI.
69
5.7(b) Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.3 µm. L1 = 0 corresponds to SMG SOI.
69
5.8 Variation of Vth,lin, Vth,sat and VDIBL with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm.
70
5.9 Variation of Ioff and Ion with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.
71
5.10(a) Variation of gm and gd with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.
71
xvi
5.10(b) Variation of voltage gain, gm/gd, with gate length L1 for a DMG SOI MOSFET at a fixed channel length, L = 0.2 µm. L1 = 0 corresponds to SMG SOI.
72
5.11 Variation of Vth,lin, Vth,sat and VDIBL with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.
73
5.12 Variation of Ioff and Ion with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.
74
5.13 Variation of gm and gd with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3µm.
74
5.14 Variation of voltage gain, gm/gd, with workfunction difference, ∆W for a DMG SOI MOSFET at a fixed channel length, L = 0.3 µm.
75
xvii
CHAPTER I
INTRODUCTION
1.1 Motivation For Present Research
In a conventional, bulk-silicon microcircuit, the active elements are located in a
thin surface layer (less than 0.5 µm of thickness) and are isolated from the silicon body
with a depletion layer of a p-n junction. The leakage current of this p-n junction
exponentially increases with temperature, and is responsible for several serious reliability
problems. Excessive leakage currents and high power dissipation limit the operation of
microcircuits at high temperatures. Parasitic n-p-n and p-n-p transistors formed in
neighboring insulating tubs can cause latch-up failures and significantly degrade circuit
performance.
Silicon-on-insulator (SOI) technology employs a thin layer of silicon (tens of
nanometers) isolated from a silicon substrate by a relatively thick (hundreds of
nanometers) layer of silicon oxide. The SOI technology dielectrically isolates
components and in conjunction with the lateral isolation, reduces various parasitic circuit
capacitances, and thus, eliminates the possibility of latch-up failures. Figure 1.1 shows
the cross-section of the bulk and SOI MOS devices. As shown in the figure, owing to the
buried oxide isolation structure, SOI technology offers superior devices with excellent
radiation hardness and high device density. Without the reverse-biased junctions used for
isolation as in bulk CMOS, leakage current is small. In addition, for scaling devices into
deep-submicron regime, SOI devices are more suitable with their steeper subthreshold
slope which facilitates scaling of the threshold voltage for low-voltage low-power
applications.
1
100 – 200 nm Buried Oxide
50 nm Si
n+ n+n+ poly p+ poly
p+ p+p n
Silicon Handle Wafer
5 – 8 nmGate oxide
n+n+n+ poly p+ poly
p+p+n - Wellp - epi
p+ Substrate
400 nmField oxide
100 – 200 nm Buried Oxide
50 nm Si
n+ n+n+ poly p+ poly
p+ p+p n
Silicon Handle Wafer
5 – 8 nmGate oxide
100 – 200 nm Buried Oxide
50 nm Si
n+ n+n+ poly p+ poly
p+ p+p n
Silicon Handle Wafer
5 – 8 nmGate oxide
n+n+n+ poly p+ poly
p+p+n - Wellp - epi
p+ Substrate
400 nmField oxide
n+n+n+ poly p+ poly
p+p+n - Wellp - epi
p+ Substrate
n+n+n+ poly p+ poly
p+p+n - Wellp - epi
p+ Substrate
400 nmField oxide
Fig. 1.1: Cross-sectional view of the bulk-Si (left) and SOI (right) CMOS devices [1].
Depending on the thickness of the silicon layer, MOSFETs will operate in fully
depleted (FD) or partially depleted (PD) regimes. When the channel depletion region
extends through the entire thickness of the silicon layer, the transistor operates in a FD
mode. PD transistors are built on relatively thick silicon layers with the depletion depths
of the fully powered MOS channel shallower than the thickness of the silicon layer. The
FD devices have several advantages compared to the PD devices: free from kink effect
[2], enhanced subthreshold swing [3], highest gains in circuit speed, reduced power
requirements and highest level of soft-error immunity [4]. Moreover it has been shown
that the total masks needed in the front-end process for FD SOI devices are less than half
that are required for bulk CMOS devices [5].
During the past decade, excellent high-speed and performance have been achieved
through improved design, use of high quality material and shrinking device dimensions
[6-7]. However, with the reduction of channel length, control of short-channel effects is
one of the biggest challenges in further down-scaling of the technology. The
predominating short-channel effects are a lack of pinch-off and a shift in threshold
voltage with decreasing channel length as well as drain induced barrier lowering (DIBL)
and hot-carrier effect at increasing drain voltage. In contrast to the bulk device, front
gate of the SOI device has better control over its active device region in the thin-film and
2
hence charge sharing effects from source/drain regions are reduced. However, the thin-
film thickness has to reduce to the order of 10 nm to significantly improve the device
performance, which becomes prohibitively difficult to manufacture and causes large
device external resistance due to shallow source/drain extension (SDE) depths.
Long et al [8-9] recently demonstrated that the application of dual-material gate
(DMG) in bulk MOSFET and HFET leads to a simultaneous transconductance
enhancement and suppression of short-channel effects due to the introduction of a step
function in the channel potential. In a DMG-MOSFET, the work function of metal gate 1
(M1) is greater than metal gate 2 (M2) i.e., φM1 > φM2 for an n-channel MOSFET and
vice-versa for a p-channel MOSFET. The aim of this work is, therefore, to study for the
first time the potential benefits offered by the DMG gate in suppressing the short-channel
effects in FD SOI MOSFETs using two-dimensional modeling and numerical simulation.
The model provides an efficient tool for further design and characterization of the novel
DMG-SOI MOSFET. The effects of varying device parameters can easily be
investigated using the simple models presented in this work.
1.2 Nature of the Problem
The present work involves two distinct features, viz. (a) Two-dimensional modeling
of surface potential and threshold voltage of a FD SOI with DMG and (b) Numerical
simulation studies using MEDICI [10] to investigate novel features offered by the DMG
in a fully depleted (FD) SOI MOSFET.
1.2.1 Threshold voltage model
One of the key parameters that characterize short-channel effects is the degradation
of the device threshold voltage with decreasing channel length. The optimization of the
3
threshold voltage reduction is very important for both process and device engineers, and
plays a major role for achieving a highly improved CMOS technology performance.
Several models for the threshold voltage of short-channel FD SOI MOSFETs have
been reported in the literature [11-16]. Veeraraghavan and Fossum [11] formulated a
charge sharing model predicting a L-1 threshold voltage dependence. The charge sharing
modeling scheme assumes a constant surface potential, regardless of any drain bias, and
therefore does not account for the drain bias associated drain induced barrier lowering
(DIBL). Additionally, because of the coupling effect between the front gate and the back
gate, the charge sharing model in [11] requires the use of a priori empirical fitting
parameters, and therefore is not well suited for circuit analysis or statistical modeling.
Woo et al. [11] and Guo et al. [14] developed short-channel threshold voltage
models by solving the two-dimensional (2D) Poisson's equation. However, due to the
complexity of the solution and complicated mathematical operations required, physical
insights into the dependence of short-channel effects on the device parameters are
masked. This dependence is an important factor needed by both process and device
engineers to optimize the device short-channel effects.
Banna et al. [15] used a quasi 2D approach and reported a threshold voltage model
but it requires the use of an empirical fitting parameter which needs additional accurate
measurements because small relative errors in measurements could give a large error in
the fitting parameter value.
In this work, a simple analytical model for the threshold voltage of short-channel
FD DMG SOI MOSFET is derived based on the approach suggested by Young [12] to
consider a parabolic trial function for the potential distribution in the silicon film.
4
1.3 Recent Research Relevant to the Problem
The concept of a Dual-Material Gate is similar to what was achieved by applying
different gate-bias in split-gate [17] structure first proposed by M. Shur. The challenge to
satisfactorily realize the split-gate FET is the inherent fringing capacitance between the
two metal gates which increases as the separation between them is reduced.
In 1999, Long et. al. [8] proposed a new gate structure called the dual material gate
(DMG)-MOSFET. Unlike the asymmetric structures employing doping engineering [18-
21] in which the channel field distribution is continuous, gate-material engineering with
different workfunctions introduces a field discontinuity along the channel, resulting in
simultaneous transport enhancement and suppressed SCEs. Zhou [22] suggested a way
in which the Hetero-Material Gate (HMG) MOSFET can be fabricated by inserting one
additional mask in the bulk CMOS processing technology and demonstrated the novel
characteristics of this new type of MOSFET by simulation studies.
However, with SOI rapidly emerging as the technology for next-generation VLSI,
the effect of DMG in submicron MOS technology remains to be investigated. In this
work, for the first time we have developed an analytical model for surface potential and
threshold voltage to aid in understanding the efficacy of DMG structure in suppressing
short channel effects in a FD SOI MOSFET. The model results are verified by numerical
simulations which are further used to extract the novel features offered by the new device
structure.
1.4 Research Problem Statement
In this dissertation, novel features offered by the introduction of a Dual-Material
Gate (DMG) in fully depleted silicon-on-insulator are studied by means of two-
5
dimensional analytical modeling and numerical simulation studies. This is accomplished
in terms of the following intermediate stages:
i) A physics based 2-D analytical model for the surface potential distribution in
the SOI thin-film of a fully depleted MOSFET is developed and verified
against numerical simulation results.
ii) Threshold voltage model for a fully-depleted DMG on SOI is developed
based on the surface potential model to show the efficacy of the DMG
structure in suppressing short-channel effects.
iii) Two-dimensional numerical simulation studies are used to investigate and
compare the benefits of DMG structure over a conventional single material
gate (SMG) in a fully-depleted SOI MOSFET.
1.5 Thesis Organization
The dissertation is divided into six chapters and its outline is described as given
below:
Chapter I: Introduction.
Fundamental concepts related to SOI devices and its advantages & disadvantages,
objectives of the project and outline of the thesis.
Chapter II: Short-channel effects in SOI: A review.
This chapter analyzes the origin and effect of the short-channel effects in SOI
MOSFETs. Various methods employed to overcome short-channel effects are also
summarized and the feasibility of dual-material gate (DMG) structure in suppressing
short-channel effects is discussed.
6
Chapter III: Two-dimensional model of the surface potential in a fully depleted
(FD) DMG-SOI MOSFET.
A physics based 2-D model for the surface potential variation along the channel in
fully depleted Dual-Material Gate silicon-on-insulator (DMG) SOI MOSFET’s is
developed. The model details the role of various MOS parameters like source/drain
and body doping concentrations, the lengths of the gate metals and their work
functions, applied drain and substrate biases, the thickness of the gate and buried
oxide in influencing the surface potential.
Chapter IV: Analytical modeling of threshold voltage and evidence for subdued
short-channel effects in thin-film DMG-SOI MOSFET.
This chapter demonstrates the development of threshold voltage model for the DMG
SOI MOSFET and illustrates the role of DMG structure in suppressing short-channel
effects.
Chapter V: Two-dimensional simulation studies.
This chapter presents the novel features offered by the DMG SOI to enhance the
MOSFET performance through 2-D numerical simulation studies. The characteristics
of DMG SOI MOSFET are compared with a conventional SMG SOI MOSFET.
Chapter VI: Conclusions.
7
CHAPTER II
SHORT-CHANNEL EFFECTS IN SOI: A REVIEW
2.1 Introduction
In order to realize higher-speed and higher-packing density MOS integrated
circuits, the dimensions of MOSFET’s have continued to shrink according to the scaling
law proposed by Dennard et al. [23]. However, the power consumption of modern
VLSI’s has become rather significant as a result of extremely large integration. Reducing
this power is strongly desired. Choosing a lower power supply voltage is an effective
method. However, it leads to the degradation of MOSFET current driving capability.
Consequently, scaling of MOS dimensions is important in order to improve the
drivability, and to achieve higher-performance and higher-functional VLSI’s.
We can say that the story of MOSFET scaling is the history of how to prevent
short-channel effects (SCE) [24]. SCE causes the dependence of device characteristics,
such as threshold voltage, upon channel length. This leads to the scatter of device
characteristics because of the scatter of gate length produced during the fabrication
process. Moreover, SCE degrades the controllability of the gate voltage to drain current,
which leads to the degradation of the subthreshold slope and the increase in drain off-
current. Thinning gate oxide and using shallow source/drain junctions are known to be
effective ways of preventing SCE.
The detrimental short-channel effects occur when the gate length is reduced to the
same order as the channel depth. When the channel length shrinks, the absolute value of
threshold voltage becomes smaller due to the reduced controllability of the gate over the
channel depletion region by the increased charge sharing from source/drain. The
9
predominating features of SCE are a lack of pinchoff and a shift in threshold voltage with
decreasing channel length as well as drain induced barrier lowering (DIBL) and hot-
carrier effect at increasing drain voltage. Increased charge sharing from source/drain
degrades the controllability of gate voltage over channel current. This degradation is
described as charge sharing by the gate and drain electric fields in the channel depletion
layer in Poon and Yau’s model [25], which was reported as the first SCE model.
This description can be applied to conventional MOSFET’s fabricated in a bulk
silicon wafer. What about thin-film SOI MOSFET’s ? They are attractive devices for
low-power high-speed VLSI applications because of their small parasitic capacitance
[26]. Young [12] analyzed the SCE using a device simulator, and concluded that SCE is
well suppressed in thin-film SOI MOSFET’s when compared to bulk MOSFET’s. In
general, it is believed that thin-film SOI MOSFET’s have a higher immunity to SCE
compared with bulk MOSFET’s. This may be due to the difference in source/drain
junction depths between the two kinds of devices. For instance, the thickness of the
silicon film, which corresponds to the source/drain junction depth of 50–100 nm, is
common in 0.25–0.35 µm SOI MOSFET’s. It is extremely shallow compared with the
junction depth of 100–200 nm in 0.25–0.35 µm gate bulk MOSFET’s. However, to take
advantage of the ameliorated SCEs in deep-submicron fully-depleted SOI, tSi must be
considerably smaller than the source/drain junction depth (tSi ∼ 10-15 nm). Moreover,
there exits a strong coupling through the buried oxide in thin-film devices consequently,
very thin buried oxides (tb ∼ 100 nm) are needed which trade-offs with junction
capacitance considerations. Hence, for small-geometry SOI CMOS devices, short-
channel effects are important [27]-[32].
10
2.2 Short-channel effects
Short-channel effects (SCE) can be physically explained by the so-called drain-
induced barrier lowering (DIBL) effect which causes a reduction in the threshold voltage
as the channel length decreases. But, in an SOI device, SCE is also influenced by thin-
film thickness, thin-film doping density, substrate biasing, buried oxide thickness and
processing technology.
2.2.1 Drain-Induced Barrier Lowering (DIBL)
In the weak inversion regime there is a potential barrier between the source and the
channel region. The height of this barrier is a result of the balance between drift and
diffusion current between these two regions. The barrier height for channel carriers
should ideally be controlled by the gate voltage to maximize transconductance. As
indicated in Fig. 2.1, drain-induced barrier lowering (DIBL) effect [33] occurs when the
barrier height for channel carriers at the edge of the source reduces due to the influence of
drain electric field, upon application of a high drain voltage. This increases the number
of carriers injected into the channel from the source leading to an increased drain off-
current. Thus the drain current is controlled not only by the gate voltage, but also by the
drain voltage.
For device modeling purposes this parasitic effect can be accounted for by a
threshold voltage reduction depending on the drain voltage [34].
11
0.15 0.20 0.25 0.30 0.35 0.40 0.450.2
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
barrier lowering
VDS = 1.5 V
VDS = 0.1 V
Lateral position, x (µm)
Surf
ace
Pote
ntia
l, φ S
(V)
0.15 0.20 0.25 0.30 0.35 0.40 0.450.2
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
barrier lowering
VDS = 1.5 V
VDS = 0.1 V
Lateral position, x (µm)
Surf
ace
Pote
ntia
l, φ S
(V)
Fig. 2.1: Surface potential variation along the position in channel for 0.1 V and 1.5 V drain
voltages (linear and saturated case).
In addition to the surface DIBL, there are two unique features determining SCEs in
thin-film SOI devices viz. (a) positive bias effect to the body due to the accumulation of
holes generated by impact ionization near the drain and (b) the DIBL effect on the barrier
height for holes at the edge of the source near the bottom, as illustrated in Fig. 2.2.
Fig. 5.14: Variation of voltage gain, gm/gd, with workfunction difference, ∆W for a DMG SOI
MOSFET at a fixed channel length, L = 0.3 µm.
The results thus obtained for a fully depleted DMG SOI MOSFET point out an
optimum metal gate length ratio, L1/L2 = 1 and a workfunction difference, ∆W = 0.4 eV.
5.3 Summary
The novel properties of fully depleted dual-material gate (DMG) SOI MOSFET
have been studied in the context of its potential integration in the current CMOS
technology. The unique features of the DMG which are not easily available in the
conventional SOI devices include: Vth “roll-up”, reduced DIBL and simultaneous
transconductance enhancement and SCE suppression which can be controlled by gate
material engineering.
One of the difficulties in integrating DMG structure in the present CMOS
technology maybe its asymmetric structure, but Zhou [22] suggested two fabrication
75
procedures requiring only one additional mask step. Moreover, the proposed DMG SOI
may also be employed in symmetric structures (like a LDD spacer). With the CMOS
processing technology already into the sub-100 nm regime [80], fabricating a 50 nm
feature gate length should not preclude the possibility of realizing the potential benefits
and excellent immunity against SCE’s that the DMG SOI MOSFET promises.
76
CHAPTER VI
CONCLUSIONS
The conclusions derived from the present work are divided into three categories,
namely, (a) Surface Potential Model for a fully depleted (FD) dual-material gate (DMG)
SOI MOSFET, (b) Analytical expression for Threshold voltage, and (c) 2-D numerical
simulation studies.
a) Surface Potential Model
Analytical model of surface potential along the channel in a FD DMG SOI MOS
device is modeled by solving the 2-D Poisson’s equation using a parabolic
approximation. The conclusions are:
1. The model predicts the creation of a step in the channel potential profile due to
the co-existence of two different gate materials having a finite workfunction
difference and controllable gate lengths. The existence of mobile carriers is
neglected.
2. The shift in the surface channel potential minima position is negligible with
increasing drain biases. This leads to excellent immunity against short-channel
effects (SCE) like drain-induced barrier lowering (DIBL) and channel length
modulation (CLM).
3. The electric field in the channel at the drain end is lowered leading to reduced
hot-carrier effect.
4. The channel potential profile can be tuned by “gate-material engineering”, i.e., the
dependence of surface potential on the difference between the gate material
workfunctions and the lengths of the two gate metals.
77
5. The model includes the effect of various MOS parameters like body doping
concentration, applied drain and substrate biases, the thickness of thin-film, gate
oxide and buried oxide.
b) Threshold Voltage
An analytical threshold voltage expression is derived based on the surface potential
model. The conclusions are:
1. Threshold voltage, Vth, rolls-up with decreasing channel length in a DMG SOI
down to 0.1 µm by carefully engineering the length and workfunction of the gate
materials.
2. Minimum channel potential and consequently Vth sensitivity to thin-film thickness
of a DMG SOI is reduced in comparison to a single material gate (SMG) SOI.
3. The effect of various MOS parameters like body doping density, applied substrate
bias, the thickness of thin-film, gate oxide and buried oxide on the threshold
voltage can be visualized with the help of the analytical expression.
c) Two-dimensional simulation studies
2-D MEDICI simulations were used to explore and compare the novel attributes
offered by the DMG structure with a conventional SMG SOI in terms of Vth variation
with decreasing channel length, drain-induced barrier-lowering (DIBL), leakage current,
drive current, transconductance, drain conductance and voltage gain. The conclusions
are:
1. The unique features of the DMG are: Vth roll-up with decreasing channel length,
reduced DIBL and simultaneous transconductance enhancement and SCE
suppression. These features can be controlled by a new way of gate material
78
engineering.
2. A gate length ratio of L1/L2 = 1 and a workfunction difference of ∆W = 0.4 eV is
found to be optimum for both logic and analog applications for a FD DMG SOI
MOSFET.
SCOPE FOR FUTURE WORK
This problem has several possible extensions that could be attempted as ongoing
research work. Some specific recommendations based on the present work are as
follows:
1. The present study can be well extended to partially depleted DMG SOI
MOSFETs.
2. A lot of scope lies in studying the effect of DMG structure on devices employing
wide bandgap materials like SiC.
3. Experimental results can provide further confirmation of the efficacy of the DMG
structure on SOI devices.
79
APPENDIX A
COMMENT Fully depleted DMG-SOI with channel length L = 0.2 µm COMMENT Specify a Rectangular Mesh MESH SMOOTH=1 COMMENT X-mesh: gate length of 0.2 µm. X.MESH X.MAX=0.25 H1=0.05 X.MESH X.MIN=0.25 H1=0.01 X.MAX=0.45 X.MESH X.MIN=0.45 H1=0.05 WIDTH=0.25 COMMENT Y-mesh: gate oxide of 5 nm, thin-film thickness of 50 nm. Y.MESH N=1 L=-0.0150 Y.MESH N=4 L=0 Y.MESH DEPTH=0.05 H1=0.0125 Y.MESH DEPTH=0.5 H1=0.0250 Y.MESH DEPTH=.5 H1=0.250 COMMENT Eliminate Some Unnecessary Substrate Nodes ELIMIN COLUMNS Y.MIN=0.05 X.MIN=0.3 X.MAX=0.8 COMMENT Specify Oxide and Silicon Regions REGION SILICON REGION OXIDE IY.MAX=4 REGION OXIDE Y.MIN=.05 Y.MAX=0.5 COMMENT Electrode Definition ELECTR NAME=Gate1 X.MIN=.25 X.MAX=0.35 IY.MIN=1 IY.MAX=3 ELECTR NAME=Gate2 X.MIN=.35001 X.MAX=0.45 IY.MIN=1 IY.MAX=3 ELECTR NAME=Substrate BOTTOM ELECTR NAME=Source X.MAX=.2 IY.MAX=4 ELECTR NAME=Drain X.MIN=0.5 IY.MAX=4 COMMENT Specify impurity profile in the source/drain and body region PROFILE P-TYPE N.PEAK=6E16 UNIFORM OUT.FILE=DMGSOI1DS_20 PROFILE N-TYPE N.PEAK=5E19 UNIFORM Y.MAX=.05 X.MIN=0 X.MAX=.25 PROFILE N-TYPE N.PEAK=5E19 Y.MAX=.05 X.MIN=.45 UNIFORM PLOT.2D GRID TITLE="INITIAL GRID" FILL SCALE COMMENT Gate workfunction specification CONTACT NAME=Gate1 WORKFUNC=4.77 CONTACT NAME=Gate2 WORKFUNC=4.1 COMMENT Specify Physical Models to use MODELS CONMOB SRFMOB CONSRH FLDMOB AUGER BGN
81
COMMENT Symbolic Factorization, Solve, Regrid on Potential SYMB CARRIERS=0 METHOD ICCG DAMPED SOLVE REGRID POTEN IGNORE=OXIDE RATIO=1.0 MAX=1 SMOOTH=1 + IN.FILE=DMGSOI1DS_20 + OUT.FILE=DMGSOI1MS_20 PLOT.2D GRID TITLE="SOI-NMOSFET - POTENTIAL REGRID" FILL SCALE COMMENT Solve using Refined Grid save solution for later use SYMB CARRIERS=0 SOLVE OUT.FILE=DMGSOI1S_20 PLOT.2D BOUND TITLE="SOI-NMOSFET - IMPURITY CONTOURS" FILL SCALE + DEPLETIO CONTOUR DOPING LOG MIN=16 MAX=20 DEL=.5 COLOR=2 CONTOUR DOPING LOG MIN=-16 MAX=-15 DEL=.5 COLOR=1 LINE=2 PLOT.2D BOUND TITLE="DMG-SOI" FILL SCALE DEPLETIO CONTOUR ELECTRON COLOR=2 CONTOUR HOLES COLOR=4 COMMENT Plot the potential at top and bottom Si/SiO2 interface at zero bias PLOT.1D POTENTIA CURVE COLOR=4 X.START=0.0 X.END=.7 Y.START=0.0 + Y.END=0.0 TITLE="SURFACE POTENTIAL DISTRIBUTION" PLOT.1D POTENTIA CURVE COLOR=2 X.START=0.0 X.END=.7 Y.START=.05 + Y.END=0.05 TITLE="BOTTOM POTENTIAL DISTRIBUTION" UNCHANGE
82
APPENDIX B
COMMENT Drain Characteristics for a DMG SOI with channel length, L = 0.2 µm. COMMENT Read in Simulation Mesh MESH IN.FILE=DMGSOI1MS_20 COMMENT Read in Initial Solution LOAD IN.FILE=DMGSOI1S_20 COMMENT Do a Poisson Solve only to Bias the Gate SYMB CARRIERS=0 METHOD ICCG DAMPED CONT.STK=8 SOLVE V(Gate1)=0 V(Gate2)=0 COMMENT Use Newton's Method and Solve for Electrons SYMB NEWTON CARRIERS=1 ELECTRONS COMMENT Set-up logfile for I-V data LOG OUT.FILE=DMGSOI1DI_20 COMMENT Ramp the Drain Voltage SOLVE V(DRAIN)=0 ELEC=DRAIN VSTEP=.25 NSTEP=6 COMMENT Plot IDS vs. VDS PLOT.1D Y.AXIS=I(DRAIN) X.AXIS=V(DRAIN) CURVE COLOR=4 + TITLE="DRAIN CHARACTERISTICS " IN.FILE=DMGSOI1DI_20
83
APPENDIX C
COMMENT Gate Characteristics for a 0.2 µm DMG SOI MOSFET. COMMENT Read in Simulation Mesh MESH IN.FILE=DMGSOI1MS_20 COMMENT Read in Saved Solution LOAD IN.FILE=DMDSOI1S_20 COMMENT Use Newton's Method for the solution SYMB NEWTON CARRIERS=1 ELECTRONS COMMENT Setup logfile for IV data LOG OUT.FILE=DMDSOI1GI_20 COMMENT Solve for VDS =0.05 V and then Ramp the Gate SOLVE V(DRAIN)=0.05 SOLVE V(GATE1)=0 V(GATE2)=0 ELEC=(Gate1,Gate2) VSTEP=.05 NSTEP=25 COMMENT Plot IDS vs VGSand save the data PLOT.1D Y.AXIS=I(DRAIN) X.AXIS=V(Gate1) CURVE COLOR=2 + TITLE="GATE CHARACTERISTICS" OUT.FILE=gate COMMENT Extract MOS parameters like the linear threshold voltage, channel length, etc. EXTRACT MOS.PARA IN.FILE=DMDSOI1GI_20 GATE=Gate1
84
APPENDIX D
COMMENT Extraction of Surface Electric Field, Mean Electron Velocity and Potential. COMMENT Read in Simulation Mesh MESH IN.FILE=DMGSOI1MS_20 COMMENT Read in Saved Solution LOAD IN.FILE=DMGSOI1S_20 COMMENT Use Newton's Method for the solution SYMB NEWTON CARRIERS=1 ELECTRONS METHOD ICCG DAMPED STACK=10 COMMENT Set-up logfile for IV data LOG OUT.FILE=DMGSOI1EI_20 COMMENT Solve for VDS =1 V and VGS = 0 V SOLVE V(Gate1)=0 V(Gate2)=0 V(Substrate)=0.0 V(DRAIN)=1 COMMENT Plot Surface Electric Field PLOT.1D E.FIELD CURVE COLOR=2 X.START=0.25 X.END=.45 Y.START=0.0 + Y.END=0.0 TITLE="ELECTRIC FIELD DISTRIBUTION" COMMENT Plot Mean Electron Velocity in the channel PLOT.1D ELE.VEL CURVE COLOR=2 X.START=0.25 X.END=.45 Y.START=0.0 + Y.END=0.0 TITLE="AVERAGE VELOCITY DISTRIBUTION" COMMENT Plot Surface Potential PLOT.1D POTENTIA CURVE COLOR=2 X.START=0.25 X.END=.45 Y.START=0.0 + Y.END=0.0 TITLE="SURFACE POTENTIAL DISTRIBUTION"
85
REFERENCES
[1] A. K. Sharma and Alexander Teverovsky, “Reliability Evaluation of Fully Depleted SOI (FDSOI) Technology for Space Applications,” NASA Electronics Parts and Packaging Program (NEPP) report, 14/9/2001.
[2] S.Cristoloveanu and S. Li, Electrical Characterization of SOI Materials and Devices, Kluwer Academic Publishers, 1995.
[3] R. Berger, J. Burns, C-L Chen, C. Chen, M. Fritze, P. Gouker, J. Knecht, A. Soares, V. Suntharalingam, P. Wyatt, D-R Yost, Craig L. Keast, “Low power, high performance, fully depleted SOI CMOS technology,” DARPAJMTO AME Review, 31/8/1999.
[4] M. I. Current, S. W. Bedell, I. J. Malik, L. M. Feng, F. J. Henley, “What is the future of sub-100nm CMOS: Ultrashallow junctions or ultrathin SOI ?,” Solid State Technology, Vol. 43, September, 2000.
[5] H. Onishi, K. Imai, H. Nakamura, Y. Matsubara, Y. Yamada, T. Tamura, T. Sakai, T. Horiuchi, “A 5-mask CMOS technology,” Symposium VLSI Tech., pp. 33-34, 1997.
[6] M. Yoshimi, M. Takahashi, S. Kambayashi, M. Kemmochi, H. Hazama, T. Wada, K. Kato, H. Tango, and K. Natori, “Electrical properties and Technological perspectives of Thin-Film SOI MOSFET’s,” IEICE Trans. Elec., vol. 74, No. 2, pp. 337-351, Feb 1991.
[7] S. Kawamura, “Ultra-Thin-Film SOI Technology and its application to next generation CMOS devices,” SOI Conf. Dig., pp. 6-7, 1993.
[8] W. Long, H. Ou, J.-M. Kuo, and K. K. Chin, “Dual material gate (DMG) Field Effect Transistor,” IEEE Trans. Electron Devices, Vol. 46, pp. 865-870, May 1999.
[9] X. Zhou and W. Long, “A Novel Hetero-Material Gate (HMG) MOSFET for deep-submicron ULSI technology,” IEEE Trans. Electron Devices, Vol. 45, pp. 2546-2548, December 1998.
[10] MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto, CA, 1997.
[11] S. Veeraraghavan, J. G. Fossum, “A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD,” IEEE Trans. Electron Devices, Vol. 35, pp. 1866-75, 1988.
[12] K. K. Young, “Short-channel effects in fully depleted SOI MOSFET's,” IEEE Trans. Electron Devices, Vol. 36, pp. 399-402, 1989.
[13] J. C. Woo, K. W. Terrill, P. K. Vasudev, “Two-dimensional analytic modeling of very thin SOI MOSFET's,” IEEE Trans. Electron Devices, Vol. 37, pp. 1999-2006, 1990.
[14] J. Y. Guo and C. Y. Wu, “A new 2D analytical threshold-voltage model for fully
87
depleted short-channel SOI MOSFET's,” IEEE Trans. Electron Devices, Vol. 40, pp. 1653-61, 1993.
[15] M. A. Imam, M. A. Osman, N. Nintunze, “Modeling the threshold voltage of short-channel silicon-on-insulator MOSFET's,” Electron Lett, vol. 29, 474-475, May 1993.
[16] S. R. Banna, P. C. H. Chan, P. K. Ko, C. T. Nguyen, M. Chan, “Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 42, pp. 1949-55, November 1995.
[17] M. Shur, “Split-gate field-effect transistor,” Appl. Phys. Lett., vol. 54, no. 2, pp. 162–164, 1989.
[18] A. Hiroki, S. Odanaka, and A. Hori, “A high performance 0.1 µm MOSFET with asymmetric channel profile,” in IEDM Tech. Dig., 1995, pp. 439–442.
[19] T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella, “Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance,” in IEDM Tech. Dig., 1989, pp. 617–620.
[20] T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, “An asymmetric sidewall process for high performance LDD MOSFET’s,” IEEE Trans. Electron Devices, Vol. 41, pp. 186–190, Feb. 1994.
[21] J. F. Chen, J. Tao, P. Fang, and C. Hu, “0.35-µm asymmetric and symmetric LDD device comparison using a reliability/speed/power methodology,” IEEE Electron Device Letters., Vol. 19, pp. 216–218, June 1998.
[22] X. Zhou, “Exploring the novel characteristics of Hetero-Material Gate Field-Effect transistors (HMGFET’s) with gate-material engineering,” IEEE Trans. Electron Devices, Vol. 47, pp.113-120, January 2000.
[23] R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bassous, and A. R. Leblanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, Vol. SC-9, pp.256–268, May 1974.
[24] T. Tsuchiya, Y. Sato, and M. Tomizawa, “Three Mechanisms Determining Short-Channel Effects in Fully-Depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, Vol. 45, pp 1116-1121, May 1998.
[25] H. C. Poon, L. D. Yau, R. L. Johnston, and D. Beecham, “DC model for short-channel IGFET’s,” in IEDM Tech. Dig., pp. 156–159, 1974.
[26] J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI, Amsterdam, Kluwer Academic Publishers, 1991.
[27] K. Hashimoto, T. I. Kamins, K. M. Cham and S. Y. Chiang, “Charcteristics of submicrometer CMOS transistors in Implanted-Buried-Oxide SOI films,” IEDM Tech. Dig., pp. 672-675, 1985.
[28] T. Tanaka, H. Horie, S. Ando, and S. Hijiya, “Analysis of p+ poly-Si Double-Gate thin-film SOI MOSFETS,” IEDM Tech. Dig., pp. 683-686, 1991.
88
[29] J. P. Coolinge, M. H. Gao, A. Romano, H. Maes and C. Claeys, “Silicon-on-Insulator “Gate-All-Around” MOS device,” SOI Conf. Dig., pp. 137-138, 1990.
[30] F. Balestra, S. Cristoloveanu, M. Menachir, J. Brini, and T. Elewa, “Double-Gate Silicon-on-Insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Letters, Vol. 8, pp. 410-412, September 1987.
[31] S. S. Chen and J. B. Kuo, “Deep submicrometer Double-Gate fully-depleted SOI PMOS devices: A concise short-channel effect threshold voltage model using a quasi-2D approach,” IEEE Trans. Electron Device, Vol. 43, pp. 1387-1393, September 1996.
[32] R. H. Yan, A. Ourmazd and K. F. Lee, “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Trans. Electron Device, Vol. 39, pp 1704-1710, July 1992.
[33] R. R. Troutman, “VLSI limitation from drain-induced barrier lowering,” IEEE Trans. Electron Devices, vol. ED-26, pp. 461–469, April 1979.
[34] Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, “A Physical and Scalable I-V Model in BSIM3v3 for Analog/Digital Circuit Simulation,” IEEE Trans. Electron Devices, Vol. 44, pp. 277-287, Feb. 1997.
[35] V. Verma and M. J. Kumar, “Study of the extended P+ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFETs,” IEEE Trans. on Electron Devices, Vol. 47, pp. 1678-1680, August, 2000.
[36] M. J. Kumar and V. Verma, “Elimination of bipolar induced drain breakdown and single transistor latch in submicron PD SOI MOSFETs,” IEEE Trans. on Reliability, Vol. 51, pp. 367-370, September 2002.
[37] K. Imai, H. Onishi, K. Yamaguchi, K. Inoue, Y. Matsubara, A. Ono, and T. Horiuchi, “A 0.18 µm Fully Depleted CMOS on 30 nm thick SOI for sub-1.0 V operation,” Symp. VLSI Tech. Dig., pp. 116-117, 1998.
[38] L. T. Su, J. B. Jacobs, J. E. Chaung, and D. A. Antoniadis, “Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET’,” IEEE Electron Device Letters, Vol. 15, pp. 366-369, September 1994.
[39] J. W. Lee, H. K. Kim, M. R. Oh, and Y. H. Koh, “Threshold voltage dependence of LOCOS isolated thin-film SOI NMOSFET on buried oxide thickness,” IEEE Electron Device Letters, Vol. 20, pp. 478-480, September 1999.
[40] J. P. Colinge, J. T. Park and C. A. Colinge, “SOI Devices for Sub-0.1µm Gate Lengths,” International Conf. Microelectronics (MIEL 2002), Vol. 1, pp. 109-113, 2002.
[41] B. Yu, Y.-J. Tung, S. Tang, E. Hui, T.-J. King, and C. Hu, “Ultra-thin-body SOI MOSFET’s for terabit-scale integration,” in International Semiconductor Device Research Symp., pp. 623–626, December 1997.
[42] V. Subramanian, J. Kedzierski, N. Lindert, H. Tam, Y. Su, J. McHale, K. Cao, T.-
89
J. King, J. Bokor, and C. Hu, “A bulk-Si-compatible ultrathin- body SOI technology for sub-100 nm MOSFETs,” in Device Research Conf., pp. 28–29, June 1999.
[43] H.-S. Wong and Y. Taur, “Three-dimensional ‘atomistic’ simulation of discrete microscopic random dopant distributions effects in sub-0.1 µm MOSFET’s,” in IEDM Tech. Dig., pp. 705–708, December 1993.
[44] Y. C. Yeo, V. Subramanian, J. Kedzierski, P. Xuan, T.-J. King, J. Bokor, and C. Hu, “Design and Fabrication of 50 nm thin-body p-MOSFETs with a SiGe Heterostructure Channel,” in IEEE Trans. Electron Devices, Vol. 49, pp. 279-286, February 2002.
[45] Y.-K. Choi, Y.-C. Jeon, P. Ranade, H. Takeuchi, T.-J. King, J. Bokor, and C. Hu, “30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S-D,” in Device Res. Conf., Denver, CO, pp. 23–24, June 2000.
[46] Y.-K. Choi, K. Asano, N. Lindert, V. Subramanium, T.-J. King, J. Bokor, and C. Hu, “Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron Device Letters, Vol. 21, pp. 254–256, May 2000.
[47] J. Kedzierski, M. Ieong, P. Xuan, J. Bokor, T. J. King, and C. Hu, “Design analysis of thin-body silicide source/drain devices,” SOI Conf., pp. 21-22, 2001.
[48] E. Dubois and G. Larrieu, “Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations,” ULIS’2001 Workshop, pp. 53, Grenoble, France, Jan. 2001.
[49] B. Maiti, et al., SPIE conference, p. 46, 1999.
[50] T. Ushiki, M. C. Yu, Y. Hirano, H. Shimada, M. Morita, and T. Ohmi, “Reliable Tantalum-Gate fully depleted SOI MOSFET technology featuring low-temperature processing,” IEEE Trans. Electron Devices, Vol. 44, pp. 1467-1472, September 1997.
[51] B. Cheng, et al., “Metal gates for advanced sub-80-nm SOI CMOS technology,” pp. 90-91, SOI Conf., 2001.
[52] A. Vandooren, et al., “Scaling assessment of fully-depleted SOI technology at the 30 nm gate length generation,” pp. 25-27, SOI Conf., 2002.
[53] A. O. Adam, K. Higashi, and Y. Fukushima, “Analytical threshold voltage model for ultra-thin SOI MOSFETs including short-channel and floating body effects,” IEEE Trans. Electron Devices, Vol. 46, pp. 729-737, April 1999.
[54] G. G. Shahidi, et al., “A room temperature 0.1 µm CMOS on SOI,” Symp. VLSI Tech. Dig., pp. 27-28, 1993.
[55] T. Ernst and S. Cristoloveanu, “The ground-plane concept for the reduction of short-channel effects in fully depleted SOI devices”, Electrochemical Society Proceedings, pp. 329-334, 1999.
[56] H.-S. P. Wong, D. J. Frank, and P. M. Solomon, “Device design considerations for
90
double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length generation,” IEDM Tech. Dig., pp. 407-410, 1998.
[57] Y. Omura, “Silicon-on-insulator (SOI) MOSFET structure for sub-50-nm channel regime,” in Silicon-on-Insulator technology and Devices X, Ed. by S. Cristoloveanu, P.L.F. Hemment, K. Izumi, G.K. Celler, F. Assaderaghi and Y.W. Kim, Electrochemical Society Proceedings, Vol. 2001-3, pp.205-210, 2001.
[58] W. Xiong and J. P. Colinge, “Self-aligned implanted ground-plane fully depleted SOI MOSFET,” Electronics Letters, Vol. 35, No. 23, IEE, pp. 2059-60, 1999.
[59] J. P. Colinge, X. Baie, V. Bayot, E. Grivei, “A silicon-on-insulator quantum wire,” Solid-State Electronics, Vol. 39, No.1, pp.49-51, 1996.
[60] X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Bokor, C. Hu, “Sub, 50-nm FinFET: PMOS,” IEDM Tech. Dig., pp. 67-70, 1999.
[61] Z. Jiao and C. A. T. Salama, “A fully depleted ∆-channel SOI nMOSFET,” Electrochemical Society Proceedings, pp. 403-408, 2001.
[62] D. Hisamoto, T. Kaga, Y. Kawamoto and E. Takeda, “A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET,” IEDM Tech. Dig., pp. 833, 1989.
[63] T. Hiramoto, “Nano-scale silicon MOSFET: towards nontraditional and quantum devices,” SOI Conf., pp. 8-10, 2001.
[64] C. P. Auth and J. D. Plummer, “A simple model for threshold voltage of surrounding-gate MOSFET’s,” IEEE Trans. Electron Devices, Vol. 45, pp. 2381-2383, November 1998.
[65] S. Miyano, M. Hirose, F. Masuoka, “Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA),” IEEE Trans. Electron Devices, Vol. 39, pp. 1876-1881, August 1992.
[66] T. Sekigawa and Y. Hayashi, “Calculated threshold voltage characteristics of an XMOS transistor having an additional bottom gate,” Solid-State Electronics, Vol. 27, No. 8-9, pp. 827-828, 1984.
[67] X. Baie and J. P. Colinge, “Two-dimensional confinement effects in gate-all-around (GAA) MOSFETS,” Solid-State Electronics, Vol. 42, pp. 499-504, April 1998.
[68] T. Su, J. P. Denton, and G. W. Neudeck, “New planar self-aligned double-gate fully depleted P-MOSFETs using epitaxial lateral overgrowth (ELO) and selectively grown source/drain (S/D),” SOI Conf., pp. 110-111, 2000.
[69] N. Lindert, L. Chang, Y.-K. Cho, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C.-M. Hu, “Sub-60-nm quasiplanar FinFET’s fabricated using a simplified process,” IEEE Electron Device Letters, Vol. 22, pp. 487–489, 2001.
[70] J. T. Park, C. A. Colinge, J. P. Colinge, “Comparison of Gate structures for short-
91
channel SOI MOSFETs,” SOI Conf., pp. 115-116, 2001.
[71] L. Vancaille, et al., “Influence of HALO implantation on analog performance and comparison between bulk, partially-depleted and fully-depleted MOSFETs,” IEEE SOI Conf., pp. 161-163, 2002.
[72] Y. Taur, et al., “25 nm CMOS Design Considerations,” IEDM Tech. Dig., pp. 789-792, 1998.
[73] S. Odanaka and A. Hiroki, “Potential Design and Transport Property of 0.1 - µm MOSFET with Asymmetric Channel Profile,” IEEE Trans. Electron Device, Vol. 44, pp. 595-600, 1997.
[74] B. Cheng, V. R. Rao, B. Ikegami, and J. C. S. Woo, “Realization of sub 100 nm asymmetric Channel MOSFETs with Excellent Short-Channel Performance and Reliability”, Technical Digest, 28th European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, 1998.
[75] B. Cheng, V. R. Rao, and J. C. S. Woo, “Sub 0.18 um SOI MOSFETs Using Lateral Asymmetric Channel Profile and Ge Pre-amorphization Salicide Technology”, Proceedings of the IEEE Int’l SOI Conf., pp.113-114, 1998.
[76] B. Cheng, A. Inani, V. R. Rao, and J. C. S. Woo, “Channel Engineering for High Speed Sub-1.0 V Power Supply Deep Sub-Micron CMOS”, Technical Digest, Symposium on VLSI Technology, pp.69-70, 1999.
[77] N. Hakim, V. R. Rao, and J. Vasi, “Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications,” 16th Int’l Conf. on VLSI Design, pp. 110-115, 2003.
[78] N. Hakim, M V Dunga, A. Kumar, V R. Rao and J. Vasi, “Characterization of Lateral Asymmetric Channel (LAC) Thin Film SOI MOSFET,” Proceedings 6th International conference on solid state and integrated circuit Technology (ICSICT), pp. 655-660, 2001.
[79] N. Hakim, M. V. Dunga, A. Kumar, J. Vasi, V. R. Rao B. Cheng, J. C. S. Woo “Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique” IEEE Electron Device Letters, Vol. 23, pp. 209-211, 2002.
[80] J. Hergenrother et al., “The vertical replacement-gate (VRG) MOSFET: A 50-nm vertical MOSFET with lithography-independent gate length,” pp. 75-79, IEDM Tech. Dig., 1999.
[81] X. Zhou and W. Long, “A Novel Hetero-Material Gate (HMG) MOSFET for deep-submicron ULSI technology,” IEEE Trans. Electron Devices, Vol. 45, pp. 2546-2548, December 1998.
[82] L. T. Su, J. B. Jacobs, J. E. Chung, D. A. Antoniadis, “Short-channel effects in deep-submicrometer SOI MOSFETS,” SOI Conf., pp. 112-113, 1993.
[83] B. Mazhari and D. E. Ioannou, “Surface potential at threshold in thin-film SOI
92
MOSFET’s,” IEEE Trans. Electron Devices, Vol. 40, pp.1129-1132, June 1993.
[84] F. Hsu and H. Grinolds, “Structure-enhanced MOSFET degradation due to hot electron injection,” IEEE Trans. Electron Device Letters, Vol. EDL-5, pp. 71–74, 1984.
[85] X. Zhou, K. Y. Lim, and D. Lim, “A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling,” IEEE Trans. Electron Devices, Vol. 46, pp. 807–809, April 1999.
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LIST OF PUBLICATIONS
1. “Two-dimensional analytical modeling of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET and Evidence for Diminished Short-channel Effects,” Accepted subject to appropriate revision in IEEE Transactions on Electron Devices, 2003.
2. “Analysis of Short-Channel Effects in SOI MOSFETs for sub-100nm CMOS Technology,” Accepted in the Proc. of the 12th International Workshop on Physics of Semiconductor Devices, IWPSD-2003, December 16th – 20th.
3. “Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies,” Accepted in the Proc. of the 17th International Conference on VLSI Design, January 5th – 9th, 2004.
4. “Investigation of the Novel Attributes of a Fully Depleted (FD) Dual-Material Gate (DMG) SOI MOSFET,” Accepted subject to appropriate revision in IEEE Transactions on Electron Devices, 2003.
5. “Controlling short-channel effects in deep submicron SOI MOSFETs for improved reliability: A Review,” Revised manuscript under review with IEEE Transactions on Device and Materials Reliability, 2003.