THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS F. Huret, E. Paleczny, P. Kennis F. Huret, E. Paleczny, P. Kennis Institut d ’Electronique et de Institut d ’Electronique et de Microélectronique Microélectronique du Nord, UMR CNRS 9929 du Nord, UMR CNRS 9929 D. Deschacht D. Deschacht , G. Servel , G. Servel Laboratoire Laboratoire d’Informatique, de Robotique d’Informatique, de Robotique et de et de Microélectronique, UMR CNRS 5506. Microélectronique, UMR CNRS 5506. SLIP ’2000, San Diego, April 8-9th. SLIP ’2000, San Diego, April 8-9th.
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THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS
THEORETICAL LIMITS FOR SIGNAL REFLECTIONS DUE TO INDUCTANCE FOR ON-CHIP INTERCONNECTIONS. F. Huret, E. Paleczny, P. Kennis Institut d ’Electronique et de Microélectronique du Nord, UMR CNRS 9929 D. Deschacht , G. Servel Laboratoire d’Informatique, de Robotique - PowerPoint PPT Presentation
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THEORETICAL LIMITS FOR SIGNAL
REFLECTIONS DUE TO INDUCTANCE
FOR ON-CHIP INTERCONNECTIONS
F. Huret, E. Paleczny, P. KennisF. Huret, E. Paleczny, P. Kennis
Institut d ’Electronique et de Microélectronique Institut d ’Electronique et de Microélectronique
du Nord, UMR CNRS 9929du Nord, UMR CNRS 9929
D. DeschachtD. Deschacht, G. Servel, G. Servel
Laboratoire d’Informatique, de RobotiqueLaboratoire d’Informatique, de Robotique
et de Microélectronique, UMR CNRS 5506.et de Microélectronique, UMR CNRS 5506.
SLIP ’2000, San Diego, April 8-9th.SLIP ’2000, San Diego, April 8-9th.
Illustration of the theoretical limits :- in frequency-domain- in time domain
Comparison with previous work
Conclusion
COMPARISON WITH PREVIOUS WORK
The two figures of merit can be combined into a two sided inequality that determines the range of the length of interconnect in which inductance effects are significant :
C
L
Rl
CL
tr
2
.2
« Figures of Merit to characterize the Importance of On-chip Inductance »DAC 98, June 1998
1st configuration :
R = 17300 /mC = 170 pF/mL = 490 nH/mG # 0
2nd configuration :
R = 17300 /mC = 63.6 pF/mL = 655 nH/mG # 0
1st configuration - L=2mm - Cu
0
0,5
1
1,5
2
2,5
3
3,5
4
0 50 100 150 200 250Time (ps)
Vo
ltag
e (
V)
Vin
Vout
1st configuration - L=1mm - Cu
0
0,5
1
1,5
2
2,5
3
3,5
4
0 50 100 150 200 250 300Time (ps)
Vo
ltag
e (
V)
Vin
Vout
1st configuration - L=10mm - Cu
0
0,5
1
1,5
2
2,5
3
3,5
4
0 100 200 300 400 500Time (ps)
Vo
ltag
e (
V)
Vin
Vout
COMPARISON
WITH PREVIOUS WORK
1st configuration - Copper
0
5
10
15
20
25
0 20 40 60 80 100 120 140 160 180 200tr (ps)
Lim
it (
mm
)
Upper limit
Lower limit
DAC Limit
2nd configuration - L=15mm - Cu
0
0,5
1
1,5
2
2,5
3
3,5
4
0 50 100 150 200 250 300 350 400Time (ps)
Vo
ltag
e (
V)
Vin
Vout
2nd configuration - L=25mm - Cu
0
0,5
1
1,5
2
2,5
3
3,5
4
0 100 200 300 400 500 600 700 800Time (ps)
Vo
ltag
e (
V)
Vin
Vout
2nd configuration - L=2mm - Cu
0
0,5
1
1,5
2
2,5
3
3,5
4
0 50 100 150 200 250Time (ps)
Vo
lta
ge
(V
)
Vin
Vout
COMPARISON
WITH PREVIOUS WORK
2nd configuration - Copper
0
5
10
15
20
25
30
35
40
0 20 40 60 80 100 120 140 160 180 200tr (ps)
Lim
it (
mm
)
Upper limit
Lower limit
DAC Limit
CONCLUSION
A full-wave electromagnetic analysis have been presented
to build accurate interconnect models,
including inductance effects.
New limits for signal reflections due to inductance
for on-chip interconnections have been proposed.
CONCLUSION
These limits have been illustrated
with typical interconnection geometries,
for Al and Cu wires.
This study shows evidence demonstrating that a range
exists for which inductance effects cannot be neglected