FEE 2018 1 The readout chip for the XFEL DSSC Detector: design and test Pradeep Kalavakuru, DESY for the DSSC ASIC design groups C. Fiorini 3 , P. Fischer 2 , K. Hansen 1 , F. Erdinger 2 , M. Kirchgessner 2 , M. Manghisoni 4 , M. Porro 5 , C. Reckleben 1 , J. Soldat 2 (DESY 1 , Heidelberg Univ. 2 , Politecnico di Milano 3 , Univ. de Bergamo 4 , European XFEL GmbH 5 )
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The readout chip for the XFEL DSSC Detector: design and test
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FEE 2018
1
The readout chip for the XFEL DSSC Detector:
design and test
Pradeep Kalavakuru, DESY
for the DSSC ASIC design groups
C. Fiorini3, P. Fischer2, K. Hansen1, F. Erdinger2, M. Kirchgessner2,M. Manghisoni4, M. Porro5, C. Reckleben1, J. Soldat2
(DESY1 , Heidelberg Univ.2, Politecnico di Milano3,
Univ. de Bergamo4, European XFEL GmbH 5)
FEE 2018
2
Outline
● Project Status
● Overview
● Characterization
ADC
Front-end
● Measurements with Sensor
Small format ASICS - X-ray sources
Focal Plane Module (FPM) - LED
● Summary
FEE 2018
3
DSSC Project Status - mini-SDD & DEPFET Cameras
Two camera types
active: DEPFET with gain compression
passive: miniaturized Silicon-Drift Cells / linear gain
mini-SDD
Mega-Pixel Camera in production Bare Modules almost
completed Focal-Plane Modules started Peripheral Electronics completed
Mechanics completed
This Work: Test of 1st Ladder (128x512) using 2nd
ASIC version
DEPFET
Mega-Pixel Camera starts soon Sensors in production ASIC in production
This Work:
Test of small-format Ladder using 1st ASIC version (64x64)
FEE 2018
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Overview: ASIC Layout
• 130-nm process, C4 Bumping
• Major changes in new ASIC→ Front-end (FE) based on Charge Sensitive
Amplifier (CSA)
→ Local references→ Uniform distribution of power pads
• Peripheral circuits→ Gray-code counter & TX per column to
distribute time-stamps for ADCs over transmission lines
→ 13-bit DAC for ADC characterization→ Temperature sensing circuit → Digital control logic
• Features (pixel-wise)→ Gain and Offset trimming→ Charge / Current injection circuits for FE
• Power cycling
FEE 2018
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Overview: Pixel-Readout Chain
SensorA
D
DigitalMemory
Front-end
Pixel
• DEPFET• Mini-SDD
• Trapezoidal Filter• CSA + Filter
• Single-slope ADC• References
SRAM
8
SerialReadout
• Gaincompression
• Linear
• I → V & Noise
shaping
• Q → V → I
• 8/9 bit • Bias, Gain & Offset
trimming
• 800 words• Readout in ~99ms
XFEL gaps
FEE 2018
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Overview: FE for active & passive Sensors
Two metal 4 masks either to connect CSA or DEPFET front-end (ASIC Prototype)