The NSEU Sensitivity of Static Latch Based FPGAs and Flash Storage CPLDs Joseph Fabula Jason Moore Austin Lesea Saar Drimer MAPLD200 4 This work has benefited from the use of the Los Alamos Neutron Science Center at the Los Alamos National Laboratory. This facility is funded by the US Department of Energy under Contract W-7405-ENG-36.
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The NSEU Sensitivity of Static Latch Based FPGAs and Flash Storage CPLDs Joseph Fabula Jason Moore Austin Lesea Saar Drimer MAPLD2004 This work has benefited.
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The NSEU Sensitivity of Static Latch Based FPGAs and
Flash Storage CPLDs
Joseph FabulaJason MooreAustin LeseaSaar Drimer
MAPLD2004This work has benefited from the use of the Los Alamos Neutron Science Center
at the Los Alamos National Laboratory. This facility is funded by the US Department of Energy under Contract W-7405-ENG-36.
Fabula_139 MAPLD20042
Objectives of this Study
• Measure the neutron single event upset cross section of various current CMOS processes- Utilizing accelerated neutron beams to:
• Test the upset potential of the static latches in FPGAs and CPLDs• Test the upset potential of the flash storage cells in CPLDs
- Utilizing applications atmospheric based tests to• Test the upset potential of the static latches in FPGAs• Calibrate the results of accelerated beam testing
• Compare findings with other independent researchers
Fabula_139 MAPLD20043
Test Facilities Used
• Accelerated Testing– Los Alamos Neutron Science Center– Hess spectrum accelerated neutron beam– Energy levels 1.5 to 600 MeV
• Applications Testing (natural flux)– Xilinx San Jose – sea level– Xilinx Albuquerque – 5,200 feet– White Mountain Research Center – 12,000 feet– Mauna Kea Observatory – 13,500 feet
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Devices Tested• Virtex II FPGA
– XC2V6000– 150 nM CMOS Static-Latch based technology
• Virtex II-Pro FPGA– XC2VP4 and XC2VP7– 130 nM CMOS Static-Latch based technology
• CoolRunner II CPLD– XC2C256– 150 nM CMOS FLASH based technology
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FPGA Test Fixtures
Virtex II
Virtex II-Pro Spartan 3
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CPLD Test Fixtures
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NSEU 101
• Neutron Single Event Upsets• Where do Neutrons come from?
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NSEU 101
• How does the Neutron density (flux) vary?– Major factors are altitude and latitude
A. Taber and E. Normand, “Single Event Upset in Avionics”, IEEE Trans. Nucl. Sci. NS-40, 120, 1993
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NSEU 101
• How do neutrons effect Integrated Circuits?
• Alpha particles have a high range and a low Linear Energy Transfer (LET). However, they are generated in the silicon, and can be in the vicinity of the sensitive areas of the IC.
Sinucleus
recoil nucleusalpha
p
neutron
p+
p-
n-
p+ n+ n++ -+ -+ -+ - Sensitive Area
VDD VSS0 1alpha+
I
V
R
V=IR
Fabula_139 MAPLD200410
NSEU 101
• Neutron Effects – from an digital designer’s point of view
ON
ONOFF
OFF
GND
VDD VDD
Sensitive Area
Sensitive Area I
t(nS)
Q Difff
ON
ON
OFF
OFF
Fabula_139 MAPLD200411
How we tested NSEU Sensitivity
• Accelerated Testing vs Atmospheric Testing– Accelerated
• Testing with Spallation Neutron sources– LANSCE spallation spectrum matches atmospheric neutrons– LANSCE source gives ~ 105 to 106 acceleration
– Atmospheric• We can use the natural radiation environment around us• Due to low rates, a very large number of devices are required • Testing times can be very long (many month to years)
– Acceleration (up to 10X) is achievable by testing at altitude(s)• However, this test is the ultimate correlation for all accelerated tests
– references • JEDEC Standard (JESD89) “Measurement and Reporting of Alpha Particles and
This work has benefited from the use of the Los Alamos Neutron Science Center at the Los Alamos National Laboratory.
This facility is funded by the US Department of Energy under
Contract W-7405-ENG-36.
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NSEU 101 (again) • How does the Neutron
density (flux) vary?– A. Taber and E. Normand, “Single Event Upset in
Avionics”, IEEE Trans. Nucl. Sci. NS-40, 120, 1993– E. Normand and T.J. Baker “Altitude and Latitude
Variations in Avionics SEU and Atmospheric Neutron Flux”, IEEE Trans. Nucl. Sci. 40, 1484, 1993
– J. Olsen, et al., “Neutron-Induced Single Event Upsets in Static RAMs observed at 10Km Flight Altitude”, IEEE Trans. Nucl. Sci. 40, 74, 1993
– J. Hewitt, et al., “Ames Collaborative Sutdy of Cosmic Ray Neutrons: Mid-Latitude Flights”, Health Physics, 34, 375, 1978
– O.C. Allkofer and P.K. Grieder, Physics Data: Cosmic Rays on Earth, Fachinformationszentrum Energie, Physik, Mathematik GmbH, Karlsruhe, 1984
– C.S. Dyer, et. al., “Measurements of the SEU Environment in the Upper Atmosphere”, IEEE Trans. Nucl. Sci. NS-36, 2275, 1989
– C.S. Dyer, et. al., “Measurements of Solar Flare Enhancements to the Single Event Upset Environment in the Upper Atmosphere”, IEEE Trans. Nucl. Sci., NS-37, 1929, 1990
Effects of Terrestrial Cosmic Rays, J.F. Zeigler,
United States Air Force Academy. http://www.srim.org/SER/SERTrends.htm
• What is Rosetta?– Atmospheric Test started in 7/2002– Rosetta stone provided correlation between
languages/scripts. Rosetta experiment provides correlation to LANSCE test results
– System of 100 2V6000s• Runs 24/7/365 – Internet Monitored• Read back and error logging 12 times a day• Each test contains >1.9 Gbits of config latches
– Test operating at 4 altitudes• Sea Level – San Jose• 5,200 feet – Albuquerque• 12,000 feet – White Mountain Research Center• 13,500 feet – Mauna Kea Observatory
– Additional testing started for VII-Pro (130 nM) and for Spartan-III (90 nM)
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Rosetta Board100 XC2V6000
1.9 Gbits
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Rosetta Test Results
• Data shown is accurate as of 5/6/04– 3.18e6 total device hours– Rosetta/LANSCE correlation factor is 1.51
• LANSCE is predicting worse results by a factor of 1.51
– Conservatively, we use a factor of 10 (SEUPI factor)
0 5 10 15 20 25 30 35 0
1
2
3
4
5
6
7
8
9
Feq
uenc
y (6
9 T
rial
s)
# of Configuration bit Upsets
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Logic Failures vs SEUs(SEUPI)
• Independent Confirmation– Work by BYU and LANL indicated that the logic upset multiplier can be
as high as 25 - 100 for specific designs in a V1000– By logical extension, the larger the FPGA the higher the multiplier for
any given logic implementation– BYU and LANL have developed a bit flip logic impact simulator for the
V1000 that has been verified in Proton testing– Xilinx has extensive data on PIP utilization from the many EasyPath
applications that we are supporting– Xilinx laboratories are developing software algorithms (SEUPI) to
identify “critical” bits which may affect user logic– SEUPI analysis of specific customer applications has shown SEUPI
factors from 10 to 80 with an mean of 42
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Comparison with Independent Data
• Actel commissioned IROC to independently test various FPGAs for NSEU Effects
• IROC tested Xilinx, Altera and Actel products– Test design was “n” 16x16 bit multipliers whose
values were muxed to a common output. Mux line was 7 bits -> up to 128 multipliers supported
– Pure combinatorial logic – no FFs!• “Focus was on configuration memory only”
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IROC Analysis
• Results– IROC unquivocally stated that Xilinx FPGAs do not exhibit
NSEL (Neutron Single Event Latch), a potentially destructive effect seen in some recent ASICs and RAMs
– IROC confirmed the existence of the SEUPI factor in Xilinx FPGAs – even though it was only in one design:
– VII (14MeV test) = 6.67– VII (LANSCE) = 10– S3 (LANSCE) = 4.54
– Reverse engineering of the IROC data confirmed Xilinx contention that the per-bit cross-section was improved by Xilinx in their 90nm technology vs their 150nm technology (see next slide)
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IROC Analysis
• 150nm (V-II) vs 90nm (S-3)– Using IROCs data for the Number of SEUs and the
Fluence (n/cm2) we can calculate the per-bit cross-section difference between technologies
• Conclusion: S-3 (90 nM) cross-section is smaller!
Conclusions• LANSCE data provides good correlation with atmospheric testing when the
correct energy model(s) are used• ROSETTA data indicates clear support for using the >10.0 MeV model for
current process technology• Independent IROC data confirmed three of Xilinx key assertions, namely:
– The sky is not falling as technology continues to shrink below 220 nM (Moore’s law still lives and our designers are smart)
– Xilinx logic upset rates are greatly improved due to the documented SEUPI factor
– Xilinx FPGAs do not exhibit Neutron Single Event Latch-up• The neutron cross sections have been stabilized as technology shrinks
(compensating a sensitivity increase by a probability decrease function)• Xilinx designers are increasing the robustness of our state of the art static
latches to the effects of atmospheric neutron flux• Current generations of Flash storage cells continue to be immune to neutron
upset
Appendix
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Virtex II MTBF Calculations
• Failure defined as incorrect operation of the FPGA– Time to Configuration Upset (Config Upset) =