The evolution of TMS, family of DSP\'s

The Evolution of TMS, Family of DSP’s

Presentation By:-

Ritul Sonania

2005H124416

BITS-Pilani

23rd Nov 2006

Instructor in charge:-

Prof. Sanjay Roy

Outline DSP Introduction DSP Tasks DSP Applications DSP vs. General Purpose MPU TMS DSP IC TMS DSP Types TMS Generations Conclusion

DSP Introduction

Digital Signal Processing: application of mathematical operations to digitally represented signals

Signals represented digitally as sequences of samples. Digital Signal Processor (DSP):

electronic system that processes digital signals

DSP tasks-

Most DSP tasks require: Repetitive numeric computations Real-time processing High memory System Flexibility

DSPs must perform these tasks efficiently while minimizing: Cost Power Memory use Development time

DSP Applications

Digital cellular phones Digital cameras Satellite communication Voice mail Music synthesis Modems RADAR

DSP vs. General Purpose MPU

DSPs tend to be written for 1 program, not many programs. Hence OSes are much simpler, there is no virtual memory

DSPs run real-time apps You must account for anything that could happen in a time slot All possible interrupts or exceptions must be noticed.

DSPs have an infinite continuous data stream

TMS DSP IC..

TMS 320 C5X TMX : Experimental device TMP : Prototype TMS : Qualified device C: CMOS Tech with on – chip non- volatile

memory as ROM E: CMOS tech with on-chip non – volatile

memory as EPROM nothing : NMOS tech with on-chip non –

volatile mem as ROM 5 : Generation X : Version number- 0,1,2,3,4x,5,6,7

TMS DSP Types… Fixed Point DSPs

TMS320C5x & 54x 16-bit DSPs

Floating Point DSPs TMS320C3x, 4x & 6x 16 & 32-bit DSPs

Multiprocessor DSPs TMS320C8x

TMS Product Generation

BASIC TMS320 ARCHITECTURE

A DSP has to perform fast arithmetic operations and should handle mathematical intensive algorithms in real time. This was achieved by these basic concepts- Harvard architecture ( increased memory access/cycle) extensive pipelining, dedicated hardware multiplier, special DSP instructions( DMOV – delay) fast instruction cycle

1st Generation TMS320C1x

Instruction cycle timing: -160 ns -200 ns -280 ns. 5 MIPS 20 MHz On chip data RAM: -144 words -256 words (TMS320C17). On chip program ROM: -1.5K words 4 K words (TMS320C17). 4K words of on chip program EPROM( TMS320E17). 16 x I6 bit multiplier with 32-bit result. 16-bit barrel shifter for shifting data memory words into the ALU. 4 x 12-bit stack. Two auxiliary registers for indirect addressing. Eight 16 bit I/O port Operating Temperature . . . 0°C to 70°C

2nd GenerationTMS320C2x

Reduced Instruction cycle timing: -100 ns (TMS320C25) 10 MIPS, 40 MHz 4K words of onchip masked ROM (TMS320C25). 544 words of onchip data RAM. 128K words of total program data memory space. Eight auxiliary registers with a dedicated arithmetic unit. Serial port for multiprocessing or interfacing to codecs. Bit-reversed addressing modes for fast Fourier trans-

forms (TMS320C25). Extended-precision arithmetic and adaptive filtering

support (TMS320C25).

3rd Generation TMS320C3x 60-ns single cycle execution time 20 -30 MIPS Two 1K x 32-bit single cycle dual-access RAM blocks. One 4K x 32-bit single cycle dual-access ROM block. 64 X 32-bit instruction cache. 32-bit instruction and data words, 24-bit addresses. 32*32 bit floating-point and integer multiplier ( 40 bit product ). 32-bit floating-point, integer, and logical ALU. 32-bit barrel shifter. Eight extended-precision registers. Two address-generators with eight auxiliary registers. On chip Direct Memory Access (DMA) controller. High-level language support.

4th Generation TMS320C4x

The TMS320C4x devices are 32-bit floating-point digital signal processors optimized for parallel processing.

33-/40-ns instruction cycle times 40 MIPS ANSI C compiler The ’C4x family accepts source code from the

TMS320C3x family of floating-point DSPs. Key applications of the ’C4x family include 3-dimensional

graphics, image processing, networking, and telecommunications base stations.

5th Generation TMS320C5x

Fixed Point DSP Power Efficient (1.15mA/MIPS) 20-50 MIPS 20-35ns single cycle execution time Bit reversed /index addressing mode for FFT Power Down modes 8 Auxiliary registers Single Cycle 16*16 bit parallel multiplier (32 bit product) 32 bit accumulator ,32 bit ALU

TMS320C54x

16-bit fixed point Power < 40 mW 300 to 532 MIPS 3 Power down modes RAM 16 Kb to 1280Kb(TMS320C5441-175) ROM max 256KB Applications –

Digital Cellular Base stations PDA’s Digital Cordless Phones Modems

TMS320C55x

16 & 32 bit fixed point Most power efficient in the industry with 0.12mW (stand by) 600 MIPS Dual Processor RAM 320Kb ROM 32 to 64Kb Newest in series TMSC5506-108 Applications –

2G,2.5G,3G cellular phones and base stations Digital audio players Digital still cameras GPS receivers Wireless modems

5th Generation …TMS320C2xx

The TMS320C2xx was introduced in 1995. Manufactured with triple-level metal and full complementary CMOS static logic, the ’C2xx provides 20-40 MIPS performance.

The ’C2xx, also available as a core for TI’s customizable DSPs, is the low-cost, fixed-point DSP of the future.

The TMS320C24x generation high-speed central processing unit (CPU) allows the use of advanced algorithms, yielding better performance and reducing system component count.

5th Generation....

TMS320C8x (1995) 1 Master Processor and up to 4 parallel processors More than 2 billion operations per second (BOPS) 50K bytes of on-chip RAM Video controller supports any display or capture resolution 32 bit RISC master processor with 120-MFLOPS Applications –

Desktop video conferencing, high-speed telecom, 3-dimensional and virtual reality graphics, digital audio and video compression .

6th Generation

TMS320C6x

First to feature VelociTI architecture. TMS320C62X

multi-channel, multi-function applications Advanced VLIW architecture Medical, industrial applications, digital imaging, 3D graphics,

speech recognition and voice-over packet. Frequency 150 to 300 MHz RAM up to 1 MB (min 128Kb) Greater than 1600 MIPS

6th Generation... TMS320C6x

TMS320C64x (highest level of performance ) Speeds up to 1GHz Up to 8000 MIPS digital communications infrastructure video and image processing

TMS320C67x (high-precision applications ) First floating point processor in 6x series 6 ns cycle timing 1billion floating point operations per second (Flops) audio, medical imaging, instrumentation and automotive.

Comparison of various generations

0

20

40

60

80

100

120

140

160

1X 2X 3X 4X 5X 6X 8X

Cycle Timing(ns)

Comparison on the basis of clock frequency

0100200300400500600700800900

1000

1x 2x 4x 54x 55x 64x

MHz

Conclusion

DSP performance has increased according to the applications involved.

DSP friendly ness is an important factor because the applications complexity is increasing.

References

http://www.ti.com http://www.bdti.com “DSP Architectures: Past, Present and Future”, Edwin J. Tan,

Wendi B. Heinzelman “The TMS320 Family of Digital Signal Processors”, KUN SHAN

LIN, GENE A. FRANTZ and RAY KUMAR,IEEE-1987