The End of CMOS Scaling will be Good for Space Computing Fault Tolerant Spaceborne Computing Employing New Technologies May 29, 2008 Sandia National Laboratories Erik DeBenedictis (Sandia) Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.
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The End of CMOS Scaling will be Good for Space Computing Fault Tolerant Spaceborne Computing Employing New Technologies May 29, 2008 Sandia National Laboratories.
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The End of CMOS Scaling will beGood for Space Computing
Fault Tolerant Spaceborne ComputingEmploying New Technologies
May 29, 2008
Sandia National Laboratories
Erik DeBenedictis (Sandia)
Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for theUnited States Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.
Overview
HPCParallel
EmbeddedLow Power
COTS/DesktopDevelopment $
Productivity Tools
FutureLow Power
ParallelHeterogeneous
Productivity Tools
Space Computing
Rad-Hard
?
Clock Rate Flat Lined
• Clock rate flat lined a couple years ago, as vendors put excess resources into multiple cores
• This is a historical fact and evident to everybody, so there is little reason to comment on the cause
• However, it has profound architectural consequences (later slide)
1990 20102005
Year
100 MHz
1 GHz
10 GHz
2 GHz4 GHz
ITRS Process Integration Spreadsheet
• Big Spreadsheet– Columns are years– Rows are 100+
transistor parameters– Manual entry of process
parameters by year– Excel computes
operating parameters– Extra degrees of
freedom go to making Moore’s Law smooth – not the best computers
Ene
rgy
(log
scal
e) f
or
Tec
hnol
ogy
crea
ted
in
Gov
ernm
ent
Fab
Year
Moore’s Law
kT100kT
kT Limit ModeratesOptimism for Perpetual Exponential Growth
2008
ITRS 2008 Update – April, Konigswinter, Germany
International Technology Roadmap for Semiconductors
A.Allan, Rev 2, [notes on IRC/CTSG More Moore, More than Moore, Beyond CMOS 04/04/08]
Industry’s Plans
Industry’s Plans
The Architecture Game
• This is my diagram from a paper to illustrate CMOS architecture in light of CMOS scaling limits
• [Discuss]
100% CPU Efficiency (can’t do better)
Com
mer
cial
Spe
ed
Tar
get
100%
50%
25%
12%
6%
3%
1980 201020001990 2020
Year log(throughput)
Pow
er
effi
ci-
ency
Next Moves: Switch to Vector Arch. Switch to SIMD Arch. Add Coprocessor Scale LinewidthIncrease Parallelism Increase Cache More Superscalar Raise Vdd and Clk
Next Moves
Finish
1
2
2008 2009 2010Year
Performance B
Traditional P with big budget
P with big budget but
clock rate and power
handicap
A Better Idea but with a small
budget
Special Architectures Go Mainstream
• Conclusions– Mainstream and
embedded technology will become more similar
• Power• Parallelism
– Architectures will become more special purpose
• General systems may be comprised of multiple special purpose sections
EXOCHI: Architecture and Programming Environment forA Heterogeneous Multi-coreMultithreaded System
Perry H. Wang1, Jamison D. Collins1, Gautham N. Chinya1, Hong Jiang2, Xinmin Tian3, Milind Girkar3, Nick Y. Yang2,
Guei-Yuan Lueh2, and Hong Wang1
Microarchitecture Research Lab, Microprocessor Technology Labs, Intel Corporation1